Commit | Line | Data |
---|---|---|
5e120f6e BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
760285e7 | 25 | #include <drm/drmP.h> |
5e120f6e BS |
26 | #include "nouveau_drv.h" |
27 | #include "nouveau_dma.h" | |
c420b2dc | 28 | #include "nouveau_fifo.h" |
5e120f6e BS |
29 | #include "nouveau_ramht.h" |
30 | #include "nouveau_fence.h" | |
31 | ||
32 | struct nv84_fence_chan { | |
33 | struct nouveau_fence_chan base; | |
34 | }; | |
35 | ||
36 | struct nv84_fence_priv { | |
37 | struct nouveau_fence_priv base; | |
38 | struct nouveau_gpuobj *mem; | |
39 | }; | |
40 | ||
41 | static int | |
42 | nv84_fence_emit(struct nouveau_fence *fence) | |
43 | { | |
44 | struct nouveau_channel *chan = fence->channel; | |
45 | int ret = RING_SPACE(chan, 7); | |
46 | if (ret == 0) { | |
47 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
48 | OUT_RING (chan, NvSema); | |
49 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
50 | OUT_RING (chan, upper_32_bits(chan->id * 16)); | |
51 | OUT_RING (chan, lower_32_bits(chan->id * 16)); | |
52 | OUT_RING (chan, fence->sequence); | |
53 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
54 | FIRE_RING (chan); | |
55 | } | |
56 | return ret; | |
57 | } | |
58 | ||
906c033e | 59 | |
5e120f6e | 60 | static int |
906c033e BS |
61 | nv84_fence_sync(struct nouveau_fence *fence, |
62 | struct nouveau_channel *prev, struct nouveau_channel *chan) | |
5e120f6e BS |
63 | { |
64 | int ret = RING_SPACE(chan, 7); | |
65 | if (ret == 0) { | |
66 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
67 | OUT_RING (chan, NvSema); | |
68 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
906c033e BS |
69 | OUT_RING (chan, upper_32_bits(prev->id * 16)); |
70 | OUT_RING (chan, lower_32_bits(prev->id * 16)); | |
5e120f6e BS |
71 | OUT_RING (chan, fence->sequence); |
72 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); | |
73 | FIRE_RING (chan); | |
74 | } | |
75 | return ret; | |
76 | } | |
77 | ||
78 | static u32 | |
79 | nv84_fence_read(struct nouveau_channel *chan) | |
80 | { | |
81 | struct nv84_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE); | |
82 | return nv_ro32(priv->mem, chan->id * 16); | |
83 | } | |
84 | ||
85 | static void | |
86 | nv84_fence_context_del(struct nouveau_channel *chan, int engine) | |
87 | { | |
88 | struct nv84_fence_chan *fctx = chan->engctx[engine]; | |
89 | nouveau_fence_context_del(&fctx->base); | |
90 | chan->engctx[engine] = NULL; | |
91 | kfree(fctx); | |
92 | } | |
93 | ||
94 | static int | |
95 | nv84_fence_context_new(struct nouveau_channel *chan, int engine) | |
96 | { | |
97 | struct nv84_fence_priv *priv = nv_engine(chan->dev, engine); | |
98 | struct nv84_fence_chan *fctx; | |
99 | struct nouveau_gpuobj *obj; | |
100 | int ret; | |
101 | ||
102 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
103 | if (!fctx) | |
104 | return -ENOMEM; | |
105 | ||
106 | nouveau_fence_context_new(&fctx->base); | |
107 | ||
108 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY, | |
109 | priv->mem->vinst, priv->mem->size, | |
110 | NV_MEM_ACCESS_RW, | |
111 | NV_MEM_TARGET_VRAM, &obj); | |
112 | if (ret == 0) { | |
113 | ret = nouveau_ramht_insert(chan, NvSema, obj); | |
114 | nouveau_gpuobj_ref(NULL, &obj); | |
115 | nv_wo32(priv->mem, chan->id * 16, 0x00000000); | |
116 | } | |
117 | ||
118 | if (ret) | |
119 | nv84_fence_context_del(chan, engine); | |
120 | return ret; | |
121 | } | |
122 | ||
123 | static int | |
124 | nv84_fence_fini(struct drm_device *dev, int engine, bool suspend) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static int | |
130 | nv84_fence_init(struct drm_device *dev, int engine) | |
131 | { | |
132 | return 0; | |
133 | } | |
134 | ||
135 | static void | |
136 | nv84_fence_destroy(struct drm_device *dev, int engine) | |
137 | { | |
138 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
139 | struct nv84_fence_priv *priv = nv_engine(dev, engine); | |
140 | ||
141 | nouveau_gpuobj_ref(NULL, &priv->mem); | |
142 | dev_priv->eng[engine] = NULL; | |
143 | kfree(priv); | |
144 | } | |
145 | ||
146 | int | |
147 | nv84_fence_create(struct drm_device *dev) | |
148 | { | |
c420b2dc | 149 | struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO); |
5e120f6e | 150 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
5e120f6e BS |
151 | struct nv84_fence_priv *priv; |
152 | int ret; | |
153 | ||
154 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
155 | if (!priv) | |
156 | return -ENOMEM; | |
157 | ||
158 | priv->base.engine.destroy = nv84_fence_destroy; | |
159 | priv->base.engine.init = nv84_fence_init; | |
160 | priv->base.engine.fini = nv84_fence_fini; | |
161 | priv->base.engine.context_new = nv84_fence_context_new; | |
162 | priv->base.engine.context_del = nv84_fence_context_del; | |
163 | priv->base.emit = nv84_fence_emit; | |
164 | priv->base.sync = nv84_fence_sync; | |
165 | priv->base.read = nv84_fence_read; | |
166 | dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine; | |
167 | ||
168 | ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels, | |
169 | 0x1000, 0, &priv->mem); | |
170 | if (ret) | |
171 | goto out; | |
172 | ||
173 | out: | |
174 | if (ret) | |
175 | nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE); | |
176 | return ret; | |
177 | } |