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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
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25 | #include <core/object.h> |
26 | #include <core/class.h> | |
27 | ||
02a841d4 | 28 | #include <engine/fifo.h> |
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29 | |
30 | #include "nouveau_drm.h" | |
31 | #include "nouveau_dma.h" | |
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32 | #include "nouveau_fence.h" |
33 | ||
34 | struct nv84_fence_chan { | |
35 | struct nouveau_fence_chan base; | |
36 | }; | |
37 | ||
38 | struct nv84_fence_priv { | |
39 | struct nouveau_fence_priv base; | |
40 | struct nouveau_gpuobj *mem; | |
41 | }; | |
42 | ||
43 | static int | |
44 | nv84_fence_emit(struct nouveau_fence *fence) | |
45 | { | |
46 | struct nouveau_channel *chan = fence->channel; | |
ebb945a9 | 47 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
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48 | int ret = RING_SPACE(chan, 7); |
49 | if (ret == 0) { | |
50 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
51 | OUT_RING (chan, NvSema); | |
52 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
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53 | OUT_RING (chan, upper_32_bits(fifo->chid * 16)); |
54 | OUT_RING (chan, lower_32_bits(fifo->chid * 16)); | |
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55 | OUT_RING (chan, fence->sequence); |
56 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
57 | FIRE_RING (chan); | |
58 | } | |
59 | return ret; | |
60 | } | |
61 | ||
906c033e | 62 | |
5e120f6e | 63 | static int |
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64 | nv84_fence_sync(struct nouveau_fence *fence, |
65 | struct nouveau_channel *prev, struct nouveau_channel *chan) | |
5e120f6e | 66 | { |
ebb945a9 | 67 | struct nouveau_fifo_chan *fifo = (void *)prev->object; |
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68 | int ret = RING_SPACE(chan, 7); |
69 | if (ret == 0) { | |
70 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
71 | OUT_RING (chan, NvSema); | |
72 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
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73 | OUT_RING (chan, upper_32_bits(fifo->chid * 16)); |
74 | OUT_RING (chan, lower_32_bits(fifo->chid * 16)); | |
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75 | OUT_RING (chan, fence->sequence); |
76 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); | |
77 | FIRE_RING (chan); | |
78 | } | |
79 | return ret; | |
80 | } | |
81 | ||
82 | static u32 | |
83 | nv84_fence_read(struct nouveau_channel *chan) | |
84 | { | |
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85 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
86 | struct nv84_fence_priv *priv = chan->drm->fence; | |
87 | return nv_ro32(priv->mem, fifo->chid * 16); | |
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88 | } |
89 | ||
90 | static void | |
e193b1d4 | 91 | nv84_fence_context_del(struct nouveau_channel *chan) |
5e120f6e | 92 | { |
e193b1d4 | 93 | struct nv84_fence_chan *fctx = chan->fence; |
5e120f6e | 94 | nouveau_fence_context_del(&fctx->base); |
e193b1d4 | 95 | chan->fence = NULL; |
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96 | kfree(fctx); |
97 | } | |
98 | ||
99 | static int | |
e193b1d4 | 100 | nv84_fence_context_new(struct nouveau_channel *chan) |
5e120f6e | 101 | { |
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102 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
103 | struct nv84_fence_priv *priv = chan->drm->fence; | |
5e120f6e | 104 | struct nv84_fence_chan *fctx; |
ebb945a9 | 105 | struct nouveau_object *object; |
f589be88 | 106 | int ret, i; |
5e120f6e | 107 | |
e193b1d4 | 108 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); |
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109 | if (!fctx) |
110 | return -ENOMEM; | |
111 | ||
112 | nouveau_fence_context_new(&fctx->base); | |
113 | ||
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114 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, |
115 | NvSema, 0x0002, | |
116 | &(struct nv_dma_class) { | |
117 | .flags = NV_DMA_TARGET_VRAM | | |
118 | NV_DMA_ACCESS_RDWR, | |
119 | .start = priv->mem->addr, | |
120 | .limit = priv->mem->addr + | |
121 | priv->mem->size - 1, | |
122 | }, sizeof(struct nv_dma_class), | |
123 | &object); | |
5e120f6e | 124 | |
f589be88 | 125 | /* dma objects for display sync channel semaphore blocks */ |
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126 | for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { |
127 | struct nouveau_bo *bo = nv50sema(chan->drm->dev, i); | |
128 | ||
129 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | |
130 | NvEvoSema0 + i, 0x003d, | |
131 | &(struct nv_dma_class) { | |
132 | .flags = NV_DMA_TARGET_VRAM | | |
133 | NV_DMA_ACCESS_RDWR, | |
134 | .start = bo->bo.offset, | |
135 | .limit = bo->bo.offset + 0xfff, | |
136 | }, sizeof(struct nv_dma_class), | |
137 | &object); | |
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138 | } |
139 | ||
5e120f6e | 140 | if (ret) |
e193b1d4 | 141 | nv84_fence_context_del(chan); |
ebb945a9 | 142 | nv_wo32(priv->mem, fifo->chid * 16, 0x00000000); |
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143 | return ret; |
144 | } | |
145 | ||
5e120f6e | 146 | static void |
ebb945a9 | 147 | nv84_fence_destroy(struct nouveau_drm *drm) |
5e120f6e | 148 | { |
ebb945a9 | 149 | struct nv84_fence_priv *priv = drm->fence; |
5e120f6e | 150 | nouveau_gpuobj_ref(NULL, &priv->mem); |
ebb945a9 | 151 | drm->fence = NULL; |
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152 | kfree(priv); |
153 | } | |
154 | ||
155 | int | |
ebb945a9 | 156 | nv84_fence_create(struct nouveau_drm *drm) |
5e120f6e | 157 | { |
ebb945a9 | 158 | struct nouveau_fifo *pfifo = nouveau_fifo(drm->device); |
5e120f6e | 159 | struct nv84_fence_priv *priv; |
ebb945a9 | 160 | u32 chan = pfifo->max + 1; |
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161 | int ret; |
162 | ||
ebb945a9 | 163 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
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164 | if (!priv) |
165 | return -ENOMEM; | |
166 | ||
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167 | priv->base.dtor = nv84_fence_destroy; |
168 | priv->base.context_new = nv84_fence_context_new; | |
169 | priv->base.context_del = nv84_fence_context_del; | |
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170 | priv->base.emit = nv84_fence_emit; |
171 | priv->base.sync = nv84_fence_sync; | |
172 | priv->base.read = nv84_fence_read; | |
5e120f6e | 173 | |
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174 | ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0, |
175 | &priv->mem); | |
5e120f6e | 176 | if (ret) |
ebb945a9 | 177 | nv84_fence_destroy(drm); |
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178 | return ret; |
179 | } |