drm/nouveau/dma: convert to new-style nvkm_engine
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / gm100.c
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3f204647
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
9719047b 24#include "priv.h"
3f204647 25
3f204647 26int
9719047b 27gm100_identify(struct nvkm_device *device)
3f204647
BS
28{
29 switch (device->chipset) {
30 case 0x117:
2a5e5fa7
MP
31
32#if 0
3f204647 33#endif
05c7145d 34 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
f84aff4e 35 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
b8bf04e1 36 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
3f204647 37 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
3f204647 38#if 0
3f204647 39#endif
3f204647 40#if 0
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BS
41#endif
42 break;
43 case 0x124:
7e547adc
SH
44#if 0
45 /* looks to be some non-trivial changes */
7e547adc 46 /* priv ring says no to 0x10eb14 writes */
7e547adc 47#endif
7e547adc 48#if 0
7e547adc 49#endif
89025bd4 50 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
7e547adc 51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
3fed3ea9 52 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
7e547adc 53 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
b44881e4 54#if 0
7e547adc
SH
55#endif
56 break;
57 case 0x126:
083dba02
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58#if 0
59 /* looks to be some non-trivial changes */
083dba02 60 /* priv ring says no to 0x10eb14 writes */
083dba02 61#endif
083dba02 62#if 0
083dba02 63#endif
5dd7fb77 64 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
f84aff4e 65 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
426b20e4 66 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
083dba02 67 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
985826bc 68#if 0
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69#endif
70 break;
d10ae271 71 case 0x12b:
d10ae271 72
d10ae271
AC
73 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
74 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
75 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
d10ae271 76 break;
3f204647 77 default:
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78 return -EINVAL;
79 }
80
81 return 0;
82}
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