[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / gm100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>

#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>

int
gm100_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x117:
		device->cname = "GM107";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  gk104_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  gf110_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk104_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;

#if 0
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
#endif
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
#endif
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
#endif
		break;
	case 0x124:
		device->cname = "GM204";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  gk104_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  gm204_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
#if 0
		/* looks to be some non-trivial changes */
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;
		/* priv ring says no to 0x10eb14 writes */
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
#endif
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk104_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
#if 0
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
#endif
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gm204_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
#endif
		break;
	case 0x126:
		device->cname = "GM206";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  gk104_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  gm204_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
#if 0
		/* looks to be some non-trivial changes */
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;
		/* priv ring says no to 0x10eb14 writes */
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
#endif
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk104_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
#if 0
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
#endif
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gm206_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
#endif
		break;
	case 0x12b:
		device->cname = "GM20B";

		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk20a_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &gk20a_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gm20b_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gm20b_gr_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
		break;
	default:
		nv_fatal(device, "unknown Maxwell chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
3f204647 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9719047b	24	#include "priv.h"
3f204647 BS	25
	26	#include <subdev/bios.h>
	27	#include <subdev/bus.h>
	28	#include <subdev/gpio.h>
	29	#include <subdev/i2c.h>
3ca6cd43	30	#include <subdev/fuse.h>
f3867f43	31	#include <subdev/clk.h>
3f204647 BS	32	#include <subdev/therm.h>
	33	#include <subdev/mxm.h>
	34	#include <subdev/devinit.h>
	35	#include <subdev/mc.h>
	36	#include <subdev/timer.h>
	37	#include <subdev/fb.h>
95484b57	38	#include <subdev/ltc.h>
3f204647 BS	39	#include <subdev/ibus.h>
3f204647 BS	40	#include <subdev/instmem.h>
5ce3bf3c	41	#include <subdev/mmu.h>
3f204647	42	#include <subdev/bar.h>
ebb58dc2	43	#include <subdev/pmu.h>
3f204647 BS	44	#include <subdev/volt.h>
3f204647 BS	45
3f204647 BS	46	#include <engine/dmaobj.h>
3f204647 BS	47	#include <engine/fifo.h>
8700287b	48	#include <engine/sw.h>
b8bf04e1	49	#include <engine/gr.h>
3f204647	50	#include <engine/disp.h>
aedf24ff	51	#include <engine/ce.h>
3f204647	52	#include <engine/bsp.h>
eccf7e8a	53	#include <engine/msvld.h>
37a5d028	54	#include <engine/mspdec.h>
fd8666f7	55	#include <engine/msppp.h>
d5752b9b	56	#include <engine/pm.h>
3f204647 BS	57
3f204647 BS	58	int
9719047b	59	gm100_identify(struct nvkm_device *device)
3f204647 BS	60	{
	61	switch (device->chipset) {
	62	case 0x117:
	63	device->cname = "GM107";
9719047b	64	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
4e7659fc	65	device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
b9ec1424	66	device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
3ca6cd43	67	device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
7632b30e	68	device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
808a188a	69	device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
3f204647 BS	70	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
3f204647 BS	71	device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
7d155dac	72	device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
5f8824de	73	device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
3f204647 BS	74	device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
3f204647 BS	75	device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
95484b57	76	device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
5ecfadeb	77	device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
3f204647	78	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
42594600	79	device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
245dcfe9	80	device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
21b13791	81	device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
2a5e5fa7 MP	82
2a5e5fa7 MP	83	#if 0
3f204647 BS	84	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
3f204647 BS	85	#endif
5b85057a	86	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	87	device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
f84aff4e	88	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
b8bf04e1	89	device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
3f204647	90	device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
bd6c5cab	91	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
3f204647	92	#if 0
bd6c5cab	93	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
3f204647	94	#endif
bd6c5cab	95	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
3f204647	96	#if 0
87c33f4e	97	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	98	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	99	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
083dba02 BS	100	#endif
	101	break;
	102	case 0x124:
	103	device->cname = "GM204";
9719047b	104	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
7e547adc SH	105	device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
	106	device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
	107	device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
	108	#if 0
	109	/* looks to be some non-trivial changes */
	110	device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
	111	/* priv ring says no to 0x10eb14 writes */
	112	device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
	113	#endif
	114	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
	115	device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
	116	device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
	117	device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
	118	device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
	119	device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
	120	device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
	121	device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
	122	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
	123	device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
	124	device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
	125	device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
	126	#if 0
	127	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
	128	#endif
	129	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
89025bd4	130	device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
7e547adc	131	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
3fed3ea9	132	device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
7e547adc	133	device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
7e547adc SH	134	device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
	135	device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
	136	device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
b44881e4	137	#if 0
7e547adc SH	138	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
	139	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
	140	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
	141	#endif
	142	break;
	143	case 0x126:
	144	device->cname = "GM206";
	145	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
4e7659fc	146	device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
083dba02 BS	147	device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
	148	device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
	149	#if 0
	150	/* looks to be some non-trivial changes */
7632b30e	151	device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
083dba02 BS	152	/* priv ring says no to 0x10eb14 writes */
	153	device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
	154	#endif
	155	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
	156	device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
	157	device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
5f8824de	158	device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
083dba02 BS	159	device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
	160	device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
	161	device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
5ecfadeb	162	device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
083dba02	163	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
42594600	164	device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
245dcfe9	165	device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
21b13791	166	device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
083dba02 BS	167	#if 0
	168	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
	169	#endif
5b85057a	170	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
5dd7fb77	171	device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
f84aff4e	172	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
426b20e4	173	device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
083dba02	174	device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
aedf24ff BS	175	device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
	176	device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
	177	device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
985826bc	178	#if 0
87c33f4e	179	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	180	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	181	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
3f204647 BS	182	#endif
3f204647 BS	183	break;
d10ae271 AC	184	case 0x12b:
	185	device->cname = "GM20B";
	186
	187	device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
	188	device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
	189	device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
	190	device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
	191	device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
	192	device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
	193	device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
	194	device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
	195	device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
	196	device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
	197	device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
	198	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
	199	device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
	200	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
	201	device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
	202	device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
	203	break;
3f204647 BS	204	default:
	205	nv_fatal(device, "unknown Maxwell chipset\n");
	206	return -EINVAL;
	207	}
	208
	209	return 0;
	210	}