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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b | 24 | #include "priv.h" |
9274f4a9 | 25 | |
9274f4a9 | 26 | int |
9719047b | 27 | nv30_identify(struct nvkm_device *device) |
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28 | { |
29 | switch (device->chipset) { | |
30 | case 0x30: | |
16c4f227 | 31 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 32 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 33 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; |
a8f8b489 | 34 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
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35 | break; |
36 | case 0x35: | |
16c4f227 | 37 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 38 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 39 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; |
a8f8b489 | 40 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
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41 | break; |
42 | case 0x31: | |
16c4f227 | 43 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 44 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 45 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; |
ebb945a9 | 46 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 47 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
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48 | break; |
49 | case 0x36: | |
16c4f227 | 50 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 51 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 52 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; |
ebb945a9 | 53 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 54 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
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55 | break; |
56 | case 0x34: | |
16c4f227 | 57 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 58 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 59 | device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; |
ebb945a9 | 60 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 61 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
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62 | break; |
63 | default: | |
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64 | return -EINVAL; |
65 | } | |
66 | ||
67 | return 0; | |
68 | } |