[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv40.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

int
nv40_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x40:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x41:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x42:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x43:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x45:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x47:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x49:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4b:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x44:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x46:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4a:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4c:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4e:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x63:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x67:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x68:
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9719047b	24	#include "priv.h"
9274f4a9	25
9274f4a9	26	int
9719047b	27	nv40_identify(struct nvkm_device *device)
9274f4a9 BS	28	{
	29	switch (device->chipset) {
	30	case 0x40:
16c4f227	31	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	32	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	33	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
ebb945a9	34	device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489	35	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	36	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	37	break;
9274f4a9 BS	38	case 0x41:
16c4f227	39	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	40	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	41	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
ebb945a9	42	device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489	43	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	44	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	45	break;
9274f4a9 BS	46	case 0x42:
16c4f227	47	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	48	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	49	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
ebb945a9	50	device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489	51	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	52	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	53	break;
9274f4a9 BS	54	case 0x43:
16c4f227	55	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	56	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	57	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
ebb945a9	58	device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489	59	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	60	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	61	break;
9274f4a9 BS	62	case 0x45:
16c4f227	63	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	64	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	65	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	66	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	67	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	68	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	69	break;
9274f4a9 BS	70	case 0x47:
16c4f227	71	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	72	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	73	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	74	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	75	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	76	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	77	break;
9274f4a9 BS	78	case 0x49:
16c4f227	79	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	80	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	81	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	82	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	83	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	84	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	85	break;
9274f4a9 BS	86	case 0x4b:
16c4f227	87	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	88	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	89	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	90	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	91	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	92	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	93	break;
9274f4a9 BS	94	case 0x44:
16c4f227	95	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	96	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	97	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	98	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	99	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	100	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	101	break;
9274f4a9 BS	102	case 0x46:
16c4f227	103	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	104	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	105	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	106	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	107	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	108	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	109	break;
9274f4a9 BS	110	case 0x4a:
16c4f227	111	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	112	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	113	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	114	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	115	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	116	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	117	break;
9274f4a9 BS	118	case 0x4c:
16c4f227	119	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	120	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	121	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	122	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	123	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	124	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	125	break;
9274f4a9 BS	126	case 0x4e:
16c4f227	127	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	128	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	129	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	130	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	131	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	132	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	133	break;
9274f4a9 BS	134	case 0x63:
16c4f227	135	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	136	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	137	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	138	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	139	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	140	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	141	break;
9274f4a9 BS	142	case 0x67:
16c4f227	143	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	144	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	145	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	146	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	147	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	148	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	149	break;
9274f4a9 BS	150	case 0x68:
16c4f227	151	device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
8700287b	152	device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
b8bf04e1	153	device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
5fa75430	154	device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489	155	device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
d5752b9b	156	device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
9274f4a9 BS	157	break;
9274f4a9 BS	158	default:
9274f4a9 BS	159	return -EINVAL;
	160	}
	161
	162	return 0;
	163	}