[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

int
nv50_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x50:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
		break;
	case 0x84:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x86:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x92:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x94:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x96:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x98:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa0:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
		break;
	case 0xaa:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xac:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa3:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa5:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa8:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xaf:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9719047b	24	#include "priv.h"
9274f4a9	25
9274f4a9	26	int
9719047b	27	nv50_identify(struct nvkm_device *device)
9274f4a9 BS	28	{
	29	switch (device->chipset) {
	30	case 0x50:
bc98540b	31	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227	32	device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
8700287b	33	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	34	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9	35	device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
a8f8b489	36	device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
d5752b9b	37	device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
9274f4a9 BS	38	break;
9274f4a9 BS	39	case 0x84:
bc98540b	40	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	41	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	42	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	43	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	44	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	45	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	46	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	47	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	48	break;
9274f4a9 BS	49	case 0x86:
bc98540b	50	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	51	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	52	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	53	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	54	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	55	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	56	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	57	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	58	break;
9274f4a9 BS	59	case 0x92:
bc98540b	60	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	61	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	62	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	63	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	64	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	65	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	66	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	67	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	68	break;
9274f4a9 BS	69	case 0x94:
bc98540b	70	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	71	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	72	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	73	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	74	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	75	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	76	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	77	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	78	break;
9274f4a9 BS	79	case 0x96:
bc98540b	80	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	81	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	82	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	83	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	84	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	85	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	86	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	87	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	88	break;
9274f4a9 BS	89	case 0x98:
bc98540b	90	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	91	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	92	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	93	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	94	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	95	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	96	break;
9274f4a9 BS	97	case 0xa0:
bc98540b	98	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	99	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	100	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	101	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	102	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
ccdfdf21	103	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
878da15a	104	device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
06b7972d	105	device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
9274f4a9 BS	106	break;
9274f4a9 BS	107	case 0xaa:
bc98540b	108	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	109	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	110	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	111	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	112	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	113	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	114	break;
9274f4a9 BS	115	case 0xac:
bc98540b	116	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	117	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	118	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	119	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	120	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	121	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	122	break;
9274f4a9 BS	123	case 0xa3:
bc98540b	124	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	125	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	126	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	127	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	128	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
878da15a	129	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	130	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	131	break;
9274f4a9 BS	132	case 0xa5:
bc98540b	133	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	134	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	135	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	136	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	137	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	138	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	139	break;
9274f4a9 BS	140	case 0xa8:
bc98540b	141	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	142	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	143	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	144	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	145	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	146	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	147	break;
9274f4a9 BS	148	case 0xaf:
bc98540b	149	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	150	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	151	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	152	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
878da15a	153	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	154	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	155	break;
9274f4a9 BS	156	default:
9274f4a9 BS	157	return -EINVAL;
	158	}
	159
	160	return 0;
	161	}