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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b | 24 | #include "priv.h" |
9274f4a9 | 25 | |
9274f4a9 | 26 | int |
9719047b | 27 | nv50_identify(struct nvkm_device *device) |
9274f4a9 BS |
28 | { |
29 | switch (device->chipset) { | |
30 | case 0x50: | |
16c4f227 | 31 | device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; |
8700287b | 32 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 33 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
ebb945a9 | 34 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; |
a8f8b489 | 35 | device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; |
d5752b9b | 36 | device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; |
9274f4a9 BS |
37 | break; |
38 | case 0x84: | |
05c7145d | 39 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 40 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 41 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 42 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 43 | device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; |
4d34686e | 44 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
45 | break; |
46 | case 0x86: | |
05c7145d | 47 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 48 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 49 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 50 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 51 | device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; |
4d34686e | 52 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
53 | break; |
54 | case 0x92: | |
05c7145d | 55 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 56 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 57 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 58 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 59 | device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; |
4d34686e | 60 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
61 | break; |
62 | case 0x94: | |
05c7145d | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 64 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 65 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 66 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 67 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
4d34686e | 68 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
69 | break; |
70 | case 0x96: | |
05c7145d | 71 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 72 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 73 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 74 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 75 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
4d34686e | 76 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
77 | break; |
78 | case 0x98: | |
05c7145d | 79 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 80 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 81 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 82 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
4d34686e | 83 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
84 | break; |
85 | case 0xa0: | |
05c7145d | 86 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 87 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 88 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 89 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 90 | device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass; |
06b7972d | 91 | device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; |
9274f4a9 BS |
92 | break; |
93 | case 0xaa: | |
05c7145d | 94 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 95 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 96 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 97 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
4d34686e | 98 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
99 | break; |
100 | case 0xac: | |
05c7145d | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 102 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 103 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 104 | device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; |
4d34686e | 105 | device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; |
9274f4a9 BS |
106 | break; |
107 | case 0xa3: | |
05c7145d | 108 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 109 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 110 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
e7c29683 | 111 | device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; |
878da15a | 112 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
4d34686e | 113 | device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; |
9274f4a9 BS |
114 | break; |
115 | case 0xa5: | |
05c7145d | 116 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 117 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 118 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 119 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
4d34686e | 120 | device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; |
9274f4a9 BS |
121 | break; |
122 | case 0xa8: | |
05c7145d | 123 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 124 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 125 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 126 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
4d34686e | 127 | device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; |
9274f4a9 BS |
128 | break; |
129 | case 0xaf: | |
05c7145d | 130 | device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; |
8700287b | 131 | device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; |
b8bf04e1 | 132 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; |
878da15a | 133 | device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; |
4d34686e | 134 | device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; |
9274f4a9 BS |
135 | break; |
136 | default: | |
9274f4a9 BS |
137 | return -EINVAL; |
138 | } | |
139 | ||
140 | return 0; | |
141 | } |