drm/nouveau/cipher: namespace + nvidia gpu names (no binary change)
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / hdanva3.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
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25#include <core/client.h>
26#include <nvif/unpack.h>
27#include <nvif/class.h>
a4feaf4e 28
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29#include <subdev/timer.h>
30
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31#include "nv50.h"
32
33int
120b0c39 34nva3_hda_eld(NV50_DISP_MTHD_V1)
a4feaf4e 35{
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36 union {
37 struct nv50_disp_sor_hda_eld_v0 v0;
38 } *args = data;
39 const u32 soff = outp->or * 0x800;
40 int ret, i;
a4feaf4e 41
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42 nv_ioctl(object, "disp sor hda eld size %d\n", size);
43 if (nvif_unpack(args->v0, 0, 0, true)) {
44 nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version);
45 if (size > 0x60)
46 return -E2BIG;
47 } else
48 return ret;
49
50 if (size && args->v0.data[0]) {
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51 if (outp->info.type == DCB_OUTPUT_DP) {
52 nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
53 nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
54 }
a4feaf4e 55 for (i = 0; i < size; i++)
120b0c39 56 nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
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57 for (; i < 0x60; i++)
58 nv_wr32(priv, 0x61c440 + soff, (i << 8));
a4feaf4e 59 nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003);
a4feaf4e 60 } else {
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61 if (outp->info.type == DCB_OUTPUT_DP) {
62 nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000);
63 nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000);
64 }
65 nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
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66 }
67
68 return 0;
69}
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