Commit | Line | Data |
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ebb945a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
878da15a | 24 | #include "nv50.h" |
2a7909c0 | 25 | #include "rootnv50.h" |
ebb945a9 | 26 | |
bf0eb898 | 27 | #include <core/client.h> |
117e1633 | 28 | #include <core/enum.h> |
2a7909c0 | 29 | #include <core/gpuobj.h> |
186ecad2 | 30 | #include <subdev/bios.h> |
186ecad2 BS |
31 | #include <subdev/bios/disp.h> |
32 | #include <subdev/bios/init.h> | |
33 | #include <subdev/bios/pll.h> | |
88524bc0 | 34 | #include <subdev/devinit.h> |
70cabe4a | 35 | |
70aa8670 BS |
36 | static const struct nvkm_disp_oclass * |
37 | nv50_disp_root_(struct nvkm_disp *base) | |
38 | { | |
39 | return nv50_disp(base)->func->root; | |
40 | } | |
41 | ||
42 | static int | |
43 | nv50_disp_outp_internal_crt_(struct nvkm_disp *base, int index, | |
44 | struct dcb_output *dcb, struct nvkm_output **poutp) | |
45 | { | |
46 | struct nv50_disp *disp = nv50_disp(base); | |
47 | return disp->func->outp.internal.crt(base, index, dcb, poutp); | |
48 | } | |
49 | ||
50 | static int | |
51 | nv50_disp_outp_internal_tmds_(struct nvkm_disp *base, int index, | |
52 | struct dcb_output *dcb, | |
53 | struct nvkm_output **poutp) | |
54 | { | |
55 | struct nv50_disp *disp = nv50_disp(base); | |
56 | return disp->func->outp.internal.tmds(base, index, dcb, poutp); | |
57 | } | |
58 | ||
59 | static int | |
60 | nv50_disp_outp_internal_lvds_(struct nvkm_disp *base, int index, | |
61 | struct dcb_output *dcb, | |
62 | struct nvkm_output **poutp) | |
63 | { | |
64 | struct nv50_disp *disp = nv50_disp(base); | |
65 | return disp->func->outp.internal.lvds(base, index, dcb, poutp); | |
66 | } | |
67 | ||
68 | static int | |
69 | nv50_disp_outp_internal_dp_(struct nvkm_disp *base, int index, | |
70 | struct dcb_output *dcb, struct nvkm_output **poutp) | |
71 | { | |
72 | struct nv50_disp *disp = nv50_disp(base); | |
73 | if (disp->func->outp.internal.dp) | |
74 | return disp->func->outp.internal.dp(base, index, dcb, poutp); | |
75 | return -ENODEV; | |
76 | } | |
77 | ||
78 | static int | |
79 | nv50_disp_outp_external_tmds_(struct nvkm_disp *base, int index, | |
80 | struct dcb_output *dcb, | |
81 | struct nvkm_output **poutp) | |
82 | { | |
83 | struct nv50_disp *disp = nv50_disp(base); | |
84 | if (disp->func->outp.external.tmds) | |
85 | return disp->func->outp.external.tmds(base, index, dcb, poutp); | |
86 | return -ENODEV; | |
87 | } | |
88 | ||
89 | static int | |
90 | nv50_disp_outp_external_dp_(struct nvkm_disp *base, int index, | |
91 | struct dcb_output *dcb, struct nvkm_output **poutp) | |
92 | { | |
93 | struct nv50_disp *disp = nv50_disp(base); | |
94 | if (disp->func->outp.external.dp) | |
95 | return disp->func->outp.external.dp(base, index, dcb, poutp); | |
96 | return -ENODEV; | |
97 | } | |
98 | ||
79ca2770 | 99 | static void |
70aa8670 | 100 | nv50_disp_vblank_fini_(struct nvkm_disp *base, int head) |
79ca2770 | 101 | { |
70aa8670 BS |
102 | struct nv50_disp *disp = nv50_disp(base); |
103 | disp->func->head.vblank_fini(disp, head); | |
79ca2770 BS |
104 | } |
105 | ||
106 | static void | |
70aa8670 | 107 | nv50_disp_vblank_init_(struct nvkm_disp *base, int head) |
79ca2770 | 108 | { |
70aa8670 BS |
109 | struct nv50_disp *disp = nv50_disp(base); |
110 | disp->func->head.vblank_init(disp, head); | |
111 | } | |
112 | ||
113 | static void | |
114 | nv50_disp_intr_(struct nvkm_disp *base) | |
115 | { | |
116 | struct nv50_disp *disp = nv50_disp(base); | |
117 | disp->func->intr(disp); | |
118 | } | |
119 | ||
120 | static void * | |
121 | nv50_disp_dtor_(struct nvkm_disp *base) | |
122 | { | |
123 | struct nv50_disp *disp = nv50_disp(base); | |
124 | nvkm_event_fini(&disp->uevent); | |
125 | return disp; | |
79ca2770 BS |
126 | } |
127 | ||
70aa8670 BS |
128 | static const struct nvkm_disp_func |
129 | nv50_disp_ = { | |
130 | .dtor = nv50_disp_dtor_, | |
131 | .intr = nv50_disp_intr_, | |
132 | .root = nv50_disp_root_, | |
133 | .outp.internal.crt = nv50_disp_outp_internal_crt_, | |
134 | .outp.internal.tmds = nv50_disp_outp_internal_tmds_, | |
135 | .outp.internal.lvds = nv50_disp_outp_internal_lvds_, | |
136 | .outp.internal.dp = nv50_disp_outp_internal_dp_, | |
137 | .outp.external.tmds = nv50_disp_outp_external_tmds_, | |
138 | .outp.external.dp = nv50_disp_outp_external_dp_, | |
139 | .head.vblank_init = nv50_disp_vblank_init_, | |
140 | .head.vblank_fini = nv50_disp_vblank_fini_, | |
79ca2770 BS |
141 | }; |
142 | ||
70aa8670 BS |
143 | int |
144 | nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, | |
145 | int index, int heads, struct nvkm_disp **pdisp) | |
146 | { | |
147 | struct nv50_disp *disp; | |
148 | int ret; | |
149 | ||
150 | if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL))) | |
151 | return -ENOMEM; | |
152 | INIT_WORK(&disp->supervisor, func->super); | |
153 | disp->func = func; | |
154 | *pdisp = &disp->base; | |
155 | ||
156 | ret = nvkm_disp_ctor(&nv50_disp_, device, index, heads, &disp->base); | |
157 | if (ret) | |
158 | return ret; | |
159 | ||
160 | return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent); | |
161 | } | |
162 | ||
163 | void | |
164 | nv50_disp_vblank_fini(struct nv50_disp *disp, int head) | |
165 | { | |
166 | struct nvkm_device *device = disp->base.engine.subdev.device; | |
167 | nvkm_mask(device, 0x61002c, (4 << head), 0); | |
168 | } | |
169 | ||
170 | void | |
171 | nv50_disp_vblank_init(struct nv50_disp *disp, int head) | |
172 | { | |
173 | struct nvkm_device *device = disp->base.engine.subdev.device; | |
174 | nvkm_mask(device, 0x61002c, (4 << head), (4 << head)); | |
175 | } | |
176 | ||
878da15a | 177 | static const struct nvkm_enum |
117e1633 BS |
178 | nv50_disp_intr_error_type[] = { |
179 | { 3, "ILLEGAL_MTHD" }, | |
180 | { 4, "INVALID_VALUE" }, | |
181 | { 5, "INVALID_STATE" }, | |
182 | { 7, "INVALID_HANDLE" }, | |
183 | {} | |
184 | }; | |
186ecad2 | 185 | |
878da15a | 186 | static const struct nvkm_enum |
117e1633 BS |
187 | nv50_disp_intr_error_code[] = { |
188 | { 0x00, "" }, | |
189 | {} | |
190 | }; | |
186ecad2 | 191 | |
117e1633 | 192 | static void |
fd166a18 | 193 | nv50_disp_intr_error(struct nv50_disp *disp, int chid) |
117e1633 | 194 | { |
84407824 BS |
195 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
196 | struct nvkm_device *device = subdev->device; | |
2fde1f1c BS |
197 | u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08)); |
198 | u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08)); | |
117e1633 BS |
199 | u32 code = (addr & 0x00ff0000) >> 16; |
200 | u32 type = (addr & 0x00007000) >> 12; | |
201 | u32 mthd = (addr & 0x00000ffc); | |
878da15a | 202 | const struct nvkm_enum *ec, *et; |
117e1633 | 203 | |
878da15a | 204 | et = nvkm_enum_find(nv50_disp_intr_error_type, type); |
878da15a | 205 | ec = nvkm_enum_find(nv50_disp_intr_error_code, code); |
117e1633 | 206 | |
84407824 BS |
207 | nvkm_error(subdev, |
208 | "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n", | |
209 | type, et ? et->name : "", code, ec ? ec->name : "", | |
210 | chid, mthd, data); | |
117e1633 | 211 | |
0ce41e3c | 212 | if (chid < ARRAY_SIZE(disp->chan)) { |
9cf6ba20 BS |
213 | switch (mthd) { |
214 | case 0x0080: | |
0ce41e3c | 215 | nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); |
9cf6ba20 BS |
216 | break; |
217 | default: | |
218 | break; | |
219 | } | |
220 | } | |
221 | ||
2fde1f1c BS |
222 | nvkm_wr32(device, 0x610020, 0x00010000 << chid); |
223 | nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000); | |
186ecad2 BS |
224 | } |
225 | ||
415f12ef | 226 | static struct nvkm_output * |
fd166a18 | 227 | exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, |
415f12ef | 228 | u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
186ecad2 BS |
229 | struct nvbios_outp *info) |
230 | { | |
84407824 BS |
231 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
232 | struct nvkm_bios *bios = subdev->device->bios; | |
415f12ef BS |
233 | struct nvkm_output *outp; |
234 | u16 mask, type; | |
186ecad2 | 235 | |
415f12ef | 236 | if (or < 4) { |
186ecad2 BS |
237 | type = DCB_OUTPUT_ANALOG; |
238 | mask = 0; | |
476e84e1 | 239 | } else |
415f12ef | 240 | if (or < 8) { |
186ecad2 BS |
241 | switch (ctrl & 0x00000f00) { |
242 | case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; | |
243 | case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; | |
244 | case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; | |
245 | case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; | |
246 | case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; | |
247 | case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; | |
248 | default: | |
84407824 | 249 | nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl); |
415f12ef | 250 | return NULL; |
186ecad2 | 251 | } |
415f12ef | 252 | or -= 4; |
476e84e1 | 253 | } else { |
415f12ef | 254 | or = or - 8; |
476e84e1 BS |
255 | type = 0x0010; |
256 | mask = 0; | |
257 | switch (ctrl & 0x00000f00) { | |
fd166a18 | 258 | case 0x00000000: type |= disp->pior.type[or]; break; |
476e84e1 | 259 | default: |
84407824 | 260 | nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl); |
415f12ef | 261 | return NULL; |
476e84e1 | 262 | } |
186ecad2 BS |
263 | } |
264 | ||
265 | mask = 0x00c0 & (mask << 6); | |
415f12ef | 266 | mask |= 0x0001 << or; |
186ecad2 BS |
267 | mask |= 0x0100 << head; |
268 | ||
fd166a18 | 269 | list_for_each_entry(outp, &disp->base.outp, head) { |
415f12ef BS |
270 | if ((outp->info.hasht & 0xff) == type && |
271 | (outp->info.hashm & mask) == mask) { | |
272 | *data = nvbios_outp_match(bios, outp->info.hasht, | |
273 | outp->info.hashm, | |
274 | ver, hdr, cnt, len, info); | |
275 | if (!*data) | |
276 | return NULL; | |
277 | return outp; | |
278 | } | |
279 | } | |
476e84e1 | 280 | |
415f12ef | 281 | return NULL; |
186ecad2 BS |
282 | } |
283 | ||
1ae5a62b | 284 | static struct nvkm_output * |
fd166a18 | 285 | exec_script(struct nv50_disp *disp, int head, int id) |
186ecad2 | 286 | { |
70aa8670 BS |
287 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
288 | struct nvkm_device *device = subdev->device; | |
2fde1f1c | 289 | struct nvkm_bios *bios = device->bios; |
415f12ef | 290 | struct nvkm_output *outp; |
186ecad2 | 291 | struct nvbios_outp info; |
186ecad2 | 292 | u8 ver, hdr, cnt, len; |
415f12ef | 293 | u32 data, ctrl = 0; |
b969fa52 | 294 | u32 reg; |
186ecad2 BS |
295 | int i; |
296 | ||
476e84e1 | 297 | /* DAC */ |
70aa8670 | 298 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++) |
2fde1f1c | 299 | ctrl = nvkm_rd32(device, 0x610b5c + (i * 8)); |
186ecad2 | 300 | |
476e84e1 | 301 | /* SOR */ |
c684cef7 | 302 | if (!(ctrl & (1 << head))) { |
70aa8670 BS |
303 | if (device->chipset < 0x90 || |
304 | device->chipset == 0x92 || | |
305 | device->chipset == 0xa0) { | |
b969fa52 | 306 | reg = 0x610b74; |
c684cef7 | 307 | } else { |
b969fa52 | 308 | reg = 0x610798; |
c684cef7 | 309 | } |
70aa8670 | 310 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) |
2fde1f1c | 311 | ctrl = nvkm_rd32(device, reg + (i * 8)); |
b969fa52 | 312 | i += 4; |
186ecad2 BS |
313 | } |
314 | ||
476e84e1 BS |
315 | /* PIOR */ |
316 | if (!(ctrl & (1 << head))) { | |
70aa8670 | 317 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++) |
2fde1f1c | 318 | ctrl = nvkm_rd32(device, 0x610b84 + (i * 8)); |
476e84e1 BS |
319 | i += 8; |
320 | } | |
321 | ||
186ecad2 | 322 | if (!(ctrl & (1 << head))) |
1ae5a62b | 323 | return NULL; |
c684cef7 | 324 | i--; |
186ecad2 | 325 | |
fd166a18 | 326 | outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); |
415f12ef | 327 | if (outp) { |
186ecad2 | 328 | struct nvbios_init init = { |
70aa8670 | 329 | .subdev = subdev, |
186ecad2 BS |
330 | .bios = bios, |
331 | .offset = info.script[id], | |
415f12ef | 332 | .outp = &outp->info, |
186ecad2 BS |
333 | .crtc = head, |
334 | .execute = 1, | |
335 | }; | |
336 | ||
1ae5a62b | 337 | nvbios_exec(&init); |
186ecad2 BS |
338 | } |
339 | ||
1ae5a62b | 340 | return outp; |
186ecad2 BS |
341 | } |
342 | ||
415f12ef | 343 | static struct nvkm_output * |
fd166a18 | 344 | exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) |
186ecad2 | 345 | { |
70aa8670 BS |
346 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
347 | struct nvkm_device *device = subdev->device; | |
2fde1f1c | 348 | struct nvkm_bios *bios = device->bios; |
415f12ef | 349 | struct nvkm_output *outp; |
186ecad2 BS |
350 | struct nvbios_outp info1; |
351 | struct nvbios_ocfg info2; | |
352 | u8 ver, hdr, cnt, len; | |
415f12ef | 353 | u32 data, ctrl = 0; |
b969fa52 | 354 | u32 reg; |
186ecad2 BS |
355 | int i; |
356 | ||
476e84e1 | 357 | /* DAC */ |
70aa8670 | 358 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++) |
2fde1f1c | 359 | ctrl = nvkm_rd32(device, 0x610b58 + (i * 8)); |
186ecad2 | 360 | |
476e84e1 | 361 | /* SOR */ |
c684cef7 | 362 | if (!(ctrl & (1 << head))) { |
70aa8670 BS |
363 | if (device->chipset < 0x90 || |
364 | device->chipset == 0x92 || | |
365 | device->chipset == 0xa0) { | |
b969fa52 | 366 | reg = 0x610b70; |
c684cef7 | 367 | } else { |
b969fa52 | 368 | reg = 0x610794; |
c684cef7 | 369 | } |
70aa8670 | 370 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) |
2fde1f1c | 371 | ctrl = nvkm_rd32(device, reg + (i * 8)); |
b969fa52 | 372 | i += 4; |
186ecad2 BS |
373 | } |
374 | ||
476e84e1 BS |
375 | /* PIOR */ |
376 | if (!(ctrl & (1 << head))) { | |
70aa8670 | 377 | for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++) |
2fde1f1c | 378 | ctrl = nvkm_rd32(device, 0x610b80 + (i * 8)); |
476e84e1 BS |
379 | i += 8; |
380 | } | |
381 | ||
186ecad2 | 382 | if (!(ctrl & (1 << head))) |
415f12ef | 383 | return NULL; |
c684cef7 | 384 | i--; |
186ecad2 | 385 | |
fd166a18 | 386 | outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); |
ba5e01b0 | 387 | if (!outp) |
415f12ef | 388 | return NULL; |
186ecad2 | 389 | |
bc9139d2 | 390 | *conf = (ctrl & 0x00000f00) >> 8; |
415f12ef BS |
391 | if (outp->info.location == 0) { |
392 | switch (outp->info.type) { | |
476e84e1 | 393 | case DCB_OUTPUT_TMDS: |
16ef53a9 | 394 | if (*conf == 5) |
415f12ef | 395 | *conf |= 0x0100; |
476e84e1 BS |
396 | break; |
397 | case DCB_OUTPUT_LVDS: | |
bc9139d2 | 398 | *conf |= disp->sor.lvdsconf; |
476e84e1 | 399 | break; |
476e84e1 | 400 | default: |
476e84e1 BS |
401 | break; |
402 | } | |
403 | } else { | |
415f12ef | 404 | *conf = (ctrl & 0x00000f00) >> 8; |
476e84e1 | 405 | pclk = pclk / 2; |
186ecad2 BS |
406 | } |
407 | ||
bc9139d2 BS |
408 | data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8, |
409 | &ver, &hdr, &cnt, &len, &info2); | |
0a0afd28 | 410 | if (data && id < 0xff) { |
186ecad2 BS |
411 | data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); |
412 | if (data) { | |
413 | struct nvbios_init init = { | |
70aa8670 | 414 | .subdev = subdev, |
186ecad2 BS |
415 | .bios = bios, |
416 | .offset = data, | |
415f12ef | 417 | .outp = &outp->info, |
186ecad2 BS |
418 | .crtc = head, |
419 | .execute = 1, | |
420 | }; | |
421 | ||
46c13c13 | 422 | nvbios_exec(&init); |
186ecad2 BS |
423 | } |
424 | } | |
425 | ||
415f12ef | 426 | return outp; |
186ecad2 BS |
427 | } |
428 | ||
429 | static void | |
fd166a18 | 430 | nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head) |
186ecad2 | 431 | { |
fd166a18 | 432 | exec_script(disp, head, 1); |
16d4c031 | 433 | } |
186ecad2 | 434 | |
16d4c031 | 435 | static void |
fd166a18 | 436 | nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head) |
16d4c031 | 437 | { |
46484438 | 438 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
fd166a18 | 439 | struct nvkm_output *outp = exec_script(disp, head, 2); |
1ae5a62b BS |
440 | |
441 | /* the binary driver does this outside of the supervisor handling | |
442 | * (after the third supervisor from a detach). we (currently?) | |
443 | * allow both detach/attach to happen in the same set of | |
444 | * supervisor interrupts, so it would make sense to execute this | |
445 | * (full power down?) script after all the detach phases of the | |
446 | * supervisor handling. like with training if needed from the | |
447 | * second supervisor, nvidia doesn't do this, so who knows if it's | |
448 | * entirely safe, but it does appear to work.. | |
449 | * | |
450 | * without this script being run, on some configurations i've | |
451 | * seen, switching from DP to TMDS on a DP connector may result | |
452 | * in a blank screen (SOR_PWR off/on can restore it) | |
453 | */ | |
454 | if (outp && outp->info.type == DCB_OUTPUT_DP) { | |
f2c906fc | 455 | struct nvkm_output_dp *outpdp = nvkm_output_dp(outp); |
1ae5a62b | 456 | struct nvbios_init init = { |
46484438 BS |
457 | .subdev = subdev, |
458 | .bios = subdev->device->bios, | |
1ae5a62b BS |
459 | .outp = &outp->info, |
460 | .crtc = head, | |
461 | .offset = outpdp->info.script[4], | |
462 | .execute = 1, | |
463 | }; | |
464 | ||
465 | nvbios_exec(&init); | |
466 | atomic_set(&outpdp->lt.done, 0); | |
467 | } | |
186ecad2 BS |
468 | } |
469 | ||
470 | static void | |
fd166a18 | 471 | nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head) |
16d4c031 | 472 | { |
2fde1f1c BS |
473 | struct nvkm_device *device = disp->base.engine.subdev.device; |
474 | struct nvkm_devinit *devinit = device->devinit; | |
475 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; | |
16d4c031 | 476 | if (pclk) |
151abd44 | 477 | nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk); |
16d4c031 BS |
478 | } |
479 | ||
480 | static void | |
fd166a18 | 481 | nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, |
16d4c031 | 482 | struct dcb_output *outp, u32 pclk) |
186ecad2 | 483 | { |
84407824 BS |
484 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
485 | struct nvkm_device *device = subdev->device; | |
186ecad2 BS |
486 | const int link = !(outp->sorconf.link & 1); |
487 | const int or = ffs(outp->or) - 1; | |
488 | const u32 soff = ( or * 0x800); | |
489 | const u32 loff = (link * 0x080) + soff; | |
2fde1f1c | 490 | const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8)); |
186ecad2 | 491 | const u32 symbol = 100000; |
2fde1f1c BS |
492 | const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff; |
493 | const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff; | |
494 | const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff; | |
495 | u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); | |
496 | u32 clksor = nvkm_rd32(device, 0x614300 + soff); | |
186ecad2 BS |
497 | int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; |
498 | int TU, VTUi, VTUf, VTUa; | |
499 | u64 link_data_rate, link_ratio, unk; | |
500 | u32 best_diff = 64 * symbol; | |
c354080d | 501 | u32 link_nr, link_bw, bits; |
9506140f BS |
502 | u64 value; |
503 | ||
504 | link_bw = (clksor & 0x000c0000) ? 270000 : 162000; | |
505 | link_nr = hweight32(dpctrl & 0x000f0000); | |
506 | ||
507 | /* symbols/hblank - algorithm taken from comments in tegra driver */ | |
508 | value = vblanke + vactive - vblanks - 7; | |
509 | value = value * link_bw; | |
510 | do_div(value, pclk); | |
511 | value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); | |
2fde1f1c | 512 | nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value); |
9506140f BS |
513 | |
514 | /* symbols/vblank - algorithm taken from comments in tegra driver */ | |
515 | value = vblanks - vblanke - 25; | |
516 | value = value * link_bw; | |
517 | do_div(value, pclk); | |
518 | value = value - ((36 / link_nr) + 3) - 1; | |
2fde1f1c | 519 | nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value); |
9506140f BS |
520 | |
521 | /* watermark / activesym */ | |
bf2c886a BS |
522 | if ((ctrl & 0xf0000) == 0x60000) bits = 30; |
523 | else if ((ctrl & 0xf0000) == 0x50000) bits = 24; | |
524 | else bits = 18; | |
525 | ||
186ecad2 BS |
526 | link_data_rate = (pclk * bits / 8) / link_nr; |
527 | ||
528 | /* calculate ratio of packed data rate to link symbol rate */ | |
529 | link_ratio = link_data_rate * symbol; | |
c354080d | 530 | do_div(link_ratio, link_bw); |
186ecad2 BS |
531 | |
532 | for (TU = 64; TU >= 32; TU--) { | |
533 | /* calculate average number of valid symbols in each TU */ | |
534 | u32 tu_valid = link_ratio * TU; | |
535 | u32 calc, diff; | |
536 | ||
537 | /* find a hw representation for the fraction.. */ | |
538 | VTUi = tu_valid / symbol; | |
539 | calc = VTUi * symbol; | |
540 | diff = tu_valid - calc; | |
541 | if (diff) { | |
542 | if (diff >= (symbol / 2)) { | |
543 | VTUf = symbol / (symbol - diff); | |
544 | if (symbol - (VTUf * diff)) | |
545 | VTUf++; | |
546 | ||
547 | if (VTUf <= 15) { | |
548 | VTUa = 1; | |
549 | calc += symbol - (symbol / VTUf); | |
550 | } else { | |
551 | VTUa = 0; | |
552 | VTUf = 1; | |
553 | calc += symbol; | |
554 | } | |
555 | } else { | |
556 | VTUa = 0; | |
557 | VTUf = min((int)(symbol / diff), 15); | |
558 | calc += symbol / VTUf; | |
559 | } | |
560 | ||
561 | diff = calc - tu_valid; | |
562 | } else { | |
563 | /* no remainder, but the hw doesn't like the fractional | |
564 | * part to be zero. decrement the integer part and | |
565 | * have the fraction add a whole symbol back | |
566 | */ | |
567 | VTUa = 0; | |
568 | VTUf = 1; | |
569 | VTUi--; | |
570 | } | |
571 | ||
572 | if (diff < best_diff) { | |
573 | best_diff = diff; | |
574 | bestTU = TU; | |
575 | bestVTUa = VTUa; | |
576 | bestVTUf = VTUf; | |
577 | bestVTUi = VTUi; | |
578 | if (diff == 0) | |
579 | break; | |
580 | } | |
581 | } | |
582 | ||
583 | if (!bestTU) { | |
84407824 | 584 | nvkm_error(subdev, "unable to find suitable dp config\n"); |
186ecad2 BS |
585 | return; |
586 | } | |
587 | ||
588 | /* XXX close to vbios numbers, but not right */ | |
589 | unk = (symbol - link_ratio) * bestTU; | |
590 | unk *= link_ratio; | |
c354080d BS |
591 | do_div(unk, symbol); |
592 | do_div(unk, symbol); | |
186ecad2 BS |
593 | unk += 6; |
594 | ||
2fde1f1c BS |
595 | nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2); |
596 | nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | | |
186ecad2 BS |
597 | bestVTUf << 16 | |
598 | bestVTUi << 8 | unk); | |
599 | } | |
600 | ||
601 | static void | |
fd166a18 | 602 | nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) |
186ecad2 | 603 | { |
2fde1f1c | 604 | struct nvkm_device *device = disp->base.engine.subdev.device; |
415f12ef | 605 | struct nvkm_output *outp; |
2fde1f1c | 606 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
16d4c031 BS |
607 | u32 hval, hreg = 0x614200 + (head * 0x800); |
608 | u32 oval, oreg; | |
415f12ef | 609 | u32 mask, conf; |
0a0afd28 | 610 | |
fd166a18 | 611 | outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); |
415f12ef BS |
612 | if (!outp) |
613 | return; | |
186ecad2 | 614 | |
55f083c3 BS |
615 | /* we allow both encoder attach and detach operations to occur |
616 | * within a single supervisor (ie. modeset) sequence. the | |
617 | * encoder detach scripts quite often switch off power to the | |
618 | * lanes, which requires the link to be re-trained. | |
619 | * | |
620 | * this is not generally an issue as the sink "must" (heh) | |
621 | * signal an irq when it's lost sync so the driver can | |
622 | * re-train. | |
623 | * | |
624 | * however, on some boards, if one does not configure at least | |
625 | * the gpu side of the link *before* attaching, then various | |
626 | * things can go horribly wrong (PDISP disappearing from mmio, | |
627 | * third supervisor never happens, etc). | |
628 | * | |
629 | * the solution is simply to retrain here, if necessary. last | |
630 | * i checked, the binary driver userspace does not appear to | |
631 | * trigger this situation (it forces an UPDATE between steps). | |
632 | */ | |
b17932c0 | 633 | if (outp->info.type == DCB_OUTPUT_DP) { |
415f12ef | 634 | u32 soff = (ffs(outp->info.or) - 1) * 0x08; |
b17932c0 BS |
635 | u32 ctrl, datarate; |
636 | ||
637 | if (outp->info.location == 0) { | |
2fde1f1c | 638 | ctrl = nvkm_rd32(device, 0x610794 + soff); |
b17932c0 BS |
639 | soff = 1; |
640 | } else { | |
2fde1f1c | 641 | ctrl = nvkm_rd32(device, 0x610b80 + soff); |
b17932c0 BS |
642 | soff = 2; |
643 | } | |
415f12ef BS |
644 | |
645 | switch ((ctrl & 0x000f0000) >> 16) { | |
0713b451 BS |
646 | case 6: datarate = pclk * 30; break; |
647 | case 5: datarate = pclk * 24; break; | |
415f12ef BS |
648 | case 2: |
649 | default: | |
0713b451 | 650 | datarate = pclk * 18; |
415f12ef | 651 | break; |
186ecad2 | 652 | } |
186ecad2 | 653 | |
55f083c3 | 654 | if (nvkm_output_dp_train(outp, datarate / soff, true)) |
f2c906fc | 655 | OUTP_ERR(outp, "link not trained before attach"); |
415f12ef BS |
656 | } |
657 | ||
fd166a18 | 658 | exec_clkcmp(disp, head, 0, pclk, &conf); |
415f12ef BS |
659 | |
660 | if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { | |
661 | oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; | |
662 | oval = 0x00000000; | |
663 | hval = 0x00000000; | |
664 | mask = 0xffffffff; | |
665 | } else | |
666 | if (!outp->info.location) { | |
667 | if (outp->info.type == DCB_OUTPUT_DP) | |
fd166a18 | 668 | nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk); |
415f12ef BS |
669 | oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; |
670 | oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; | |
671 | hval = 0x00000000; | |
672 | mask = 0x00000707; | |
673 | } else { | |
674 | oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; | |
675 | oval = 0x00000001; | |
676 | hval = 0x00000001; | |
677 | mask = 0x00000707; | |
16d4c031 | 678 | } |
415f12ef | 679 | |
2fde1f1c BS |
680 | nvkm_mask(device, hreg, 0x0000000f, hval); |
681 | nvkm_mask(device, oreg, mask, oval); | |
186ecad2 BS |
682 | } |
683 | ||
684 | /* If programming a TMDS output on a SOR that can also be configured for | |
685 | * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. | |
686 | * | |
687 | * It looks like the VBIOS TMDS scripts make an attempt at this, however, | |
688 | * the VBIOS scripts on at least one board I have only switch it off on | |
689 | * link 0, causing a blank display if the output has previously been | |
690 | * programmed for DisplayPort. | |
691 | */ | |
692 | static void | |
fd166a18 | 693 | nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, |
878da15a | 694 | struct dcb_output *outp) |
186ecad2 | 695 | { |
2fde1f1c BS |
696 | struct nvkm_device *device = disp->base.engine.subdev.device; |
697 | struct nvkm_bios *bios = device->bios; | |
186ecad2 BS |
698 | const int link = !(outp->sorconf.link & 1); |
699 | const int or = ffs(outp->or) - 1; | |
700 | const u32 loff = (or * 0x800) + (link * 0x80); | |
701 | const u16 mask = (outp->sorconf.link << 6) | outp->or; | |
5838ae61 | 702 | struct dcb_output match; |
186ecad2 BS |
703 | u8 ver, hdr; |
704 | ||
5838ae61 | 705 | if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) |
2fde1f1c | 706 | nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000); |
186ecad2 BS |
707 | } |
708 | ||
709 | static void | |
fd166a18 | 710 | nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head) |
186ecad2 | 711 | { |
2fde1f1c | 712 | struct nvkm_device *device = disp->base.engine.subdev.device; |
415f12ef | 713 | struct nvkm_output *outp; |
2fde1f1c | 714 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
415f12ef | 715 | u32 conf; |
16d4c031 | 716 | |
fd166a18 | 717 | outp = exec_clkcmp(disp, head, 1, pclk, &conf); |
415f12ef BS |
718 | if (!outp) |
719 | return; | |
720 | ||
721 | if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) | |
fd166a18 | 722 | nv50_disp_intr_unk40_0_tmds(disp, &outp->info); |
186ecad2 BS |
723 | } |
724 | ||
5cc027f6 BS |
725 | void |
726 | nv50_disp_intr_supervisor(struct work_struct *work) | |
186ecad2 | 727 | { |
fd166a18 BS |
728 | struct nv50_disp *disp = |
729 | container_of(work, struct nv50_disp, supervisor); | |
84407824 BS |
730 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
731 | struct nvkm_device *device = subdev->device; | |
2fde1f1c | 732 | u32 super = nvkm_rd32(device, 0x610030); |
16d4c031 | 733 | int head; |
186ecad2 | 734 | |
84407824 | 735 | nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super); |
186ecad2 | 736 | |
fd166a18 | 737 | if (disp->super & 0x00000010) { |
0ce41e3c | 738 | nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); |
70aa8670 | 739 | for (head = 0; head < disp->base.head.nr; head++) { |
16d4c031 BS |
740 | if (!(super & (0x00000020 << head))) |
741 | continue; | |
742 | if (!(super & (0x00000080 << head))) | |
743 | continue; | |
fd166a18 | 744 | nv50_disp_intr_unk10_0(disp, head); |
16d4c031 BS |
745 | } |
746 | } else | |
fd166a18 | 747 | if (disp->super & 0x00000020) { |
70aa8670 | 748 | for (head = 0; head < disp->base.head.nr; head++) { |
16d4c031 BS |
749 | if (!(super & (0x00000080 << head))) |
750 | continue; | |
fd166a18 | 751 | nv50_disp_intr_unk20_0(disp, head); |
16d4c031 | 752 | } |
70aa8670 | 753 | for (head = 0; head < disp->base.head.nr; head++) { |
16d4c031 BS |
754 | if (!(super & (0x00000200 << head))) |
755 | continue; | |
fd166a18 | 756 | nv50_disp_intr_unk20_1(disp, head); |
16d4c031 | 757 | } |
70aa8670 | 758 | for (head = 0; head < disp->base.head.nr; head++) { |
16d4c031 BS |
759 | if (!(super & (0x00000080 << head))) |
760 | continue; | |
fd166a18 | 761 | nv50_disp_intr_unk20_2(disp, head); |
16d4c031 BS |
762 | } |
763 | } else | |
fd166a18 | 764 | if (disp->super & 0x00000040) { |
70aa8670 | 765 | for (head = 0; head < disp->base.head.nr; head++) { |
16d4c031 BS |
766 | if (!(super & (0x00000080 << head))) |
767 | continue; | |
fd166a18 | 768 | nv50_disp_intr_unk40_0(disp, head); |
16d4c031 BS |
769 | } |
770 | } | |
771 | ||
2fde1f1c | 772 | nvkm_wr32(device, 0x610030, 0x80000000); |
186ecad2 BS |
773 | } |
774 | ||
70cabe4a | 775 | void |
70aa8670 | 776 | nv50_disp_intr(struct nv50_disp *disp) |
ebb945a9 | 777 | { |
2fde1f1c BS |
778 | struct nvkm_device *device = disp->base.engine.subdev.device; |
779 | u32 intr0 = nvkm_rd32(device, 0x610020); | |
780 | u32 intr1 = nvkm_rd32(device, 0x610024); | |
ebb945a9 | 781 | |
117e1633 BS |
782 | while (intr0 & 0x001f0000) { |
783 | u32 chid = __ffs(intr0 & 0x001f0000) - 16; | |
fd166a18 | 784 | nv50_disp_intr_error(disp, chid); |
117e1633 | 785 | intr0 &= ~(0x00010000 << chid); |
186ecad2 BS |
786 | } |
787 | ||
b38a2322 BS |
788 | while (intr0 & 0x0000001f) { |
789 | u32 chid = __ffs(intr0 & 0x0000001f); | |
fd166a18 | 790 | nv50_disp_chan_uevent_send(disp, chid); |
b38a2322 BS |
791 | intr0 &= ~(0x00000001 << chid); |
792 | } | |
793 | ||
186ecad2 | 794 | if (intr1 & 0x00000004) { |
fd166a18 | 795 | nvkm_disp_vblank(&disp->base, 0); |
2fde1f1c | 796 | nvkm_wr32(device, 0x610024, 0x00000004); |
ebb945a9 BS |
797 | } |
798 | ||
186ecad2 | 799 | if (intr1 & 0x00000008) { |
fd166a18 | 800 | nvkm_disp_vblank(&disp->base, 1); |
2fde1f1c | 801 | nvkm_wr32(device, 0x610024, 0x00000008); |
ebb945a9 BS |
802 | } |
803 | ||
186ecad2 | 804 | if (intr1 & 0x00000070) { |
fd166a18 BS |
805 | disp->super = (intr1 & 0x00000070); |
806 | schedule_work(&disp->supervisor); | |
2fde1f1c | 807 | nvkm_wr32(device, 0x610024, disp->super); |
186ecad2 | 808 | } |
ebb945a9 BS |
809 | } |
810 | ||
70aa8670 | 811 | static const struct nv50_disp_func |
0ce41e3c | 812 | nv50_disp = { |
70aa8670 BS |
813 | .intr = nv50_disp_intr, |
814 | .uevent = &nv50_disp_chan_uevent, | |
815 | .super = nv50_disp_intr_supervisor, | |
0ce41e3c | 816 | .root = &nv50_disp_root_oclass, |
70aa8670 BS |
817 | .head.vblank_init = nv50_disp_vblank_init, |
818 | .head.vblank_fini = nv50_disp_vblank_fini, | |
819 | .head.scanoutpos = nv50_disp_root_scanoutpos, | |
820 | .outp.internal.crt = nv50_dac_output_new, | |
821 | .outp.internal.tmds = nv50_sor_output_new, | |
822 | .outp.internal.lvds = nv50_sor_output_new, | |
823 | .outp.external.tmds = nv50_pior_output_new, | |
824 | .outp.external.dp = nv50_pior_dp_new, | |
825 | .dac.nr = 3, | |
826 | .dac.power = nv50_dac_power, | |
827 | .dac.sense = nv50_dac_sense, | |
828 | .sor.nr = 2, | |
829 | .sor.power = nv50_sor_power, | |
830 | .pior.nr = 3, | |
831 | .pior.power = nv50_pior_power, | |
0ce41e3c BS |
832 | }; |
833 | ||
70aa8670 BS |
834 | int |
835 | nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) | |
ebb945a9 | 836 | { |
70aa8670 | 837 | return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp); |
ebb945a9 | 838 | } |