[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / rootgf119.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "rootnv50.h"
#include "dmacnv50.h"

#include <core/client.h>
#include <core/ramht.h>
#include <subdev/timer.h>

#include <nvif/class.h>
#include <nvif/cl5070.h>
#include <nvif/unpack.h>

int
gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
{
	struct nvkm_device *device = disp->base.engine.subdev.device;
	const u32 total  = nvkm_rd32(device, 0x640414 + (head * 0x300));
	const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300));
	const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300));
	union {
		struct nv50_disp_scanoutpos_v0 v0;
	} *args = data;
	int ret;

	nvif_ioctl(object, "disp scanoutpos size %d\n", size);
	if (nvif_unpack(args->v0, 0, 0, false)) {
		nvif_ioctl(object, "disp scanoutpos vers %d\n",
			   args->v0.version);
		args->v0.vblanke = (blanke & 0xffff0000) >> 16;
		args->v0.hblanke = (blanke & 0x0000ffff);
		args->v0.vblanks = (blanks & 0xffff0000) >> 16;
		args->v0.hblanks = (blanks & 0x0000ffff);
		args->v0.vtotal  = ( total & 0xffff0000) >> 16;
		args->v0.htotal  = ( total & 0x0000ffff);
		args->v0.time[0] = ktime_to_ns(ktime_get());
		args->v0.vline = /* vline read locks hline */
			nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
		args->v0.time[1] = ktime_to_ns(ktime_get());
		args->v0.hline =
			nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
	} else
		return ret;

	return 0;
}

void
gf119_disp_root_fini(struct nv50_disp_root *root)
{
	struct nvkm_device *device = root->disp->base.engine.subdev.device;
	/* disable all interrupts */
	nvkm_wr32(device, 0x6100b0, 0x00000000);
}

int
gf119_disp_root_init(struct nv50_disp_root *root)
{
	struct nv50_disp *disp = root->disp;
	struct nvkm_device *device = disp->base.engine.subdev.device;
	u32 tmp;
	int i;

	/* The below segments of code copying values from one register to
	 * another appear to inform EVO of the display capabilities or
	 * something similar.
	 */

	/* ... CRTC caps */
	for (i = 0; i < disp->base.head.nr; i++) {
		tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
		nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
		tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
		nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp);
		tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
		nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp);
	}

	/* ... DAC caps */
	for (i = 0; i < disp->func->dac.nr; i++) {
		tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
		nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
	}

	/* ... SOR caps */
	for (i = 0; i < disp->func->sor.nr; i++) {
		tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
		nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
	}

	/* steal display away from vbios, or something like that */
	if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
		nvkm_wr32(device, 0x6100ac, 0x00000100);
		nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
		if (nvkm_msec(device, 2000,
			if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
				break;
		) < 0)
			return -EBUSY;
	}

	/* point at display engine memory area (hash table, objects) */
	nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);

	/* enable supervisor interrupts, disable everything else */
	nvkm_wr32(device, 0x610090, 0x00000000);
	nvkm_wr32(device, 0x6100a0, 0x00000000);
	nvkm_wr32(device, 0x6100b0, 0x00000307);

	/* disable underflow reporting, preventing an intermittent issue
	 * on some gk104 boards where the production vbios left this
	 * setting enabled by default.
	 *
	 * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
	 */
	for (i = 0; i < disp->base.head.nr; i++)
		nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);

	return 0;
}

static const struct nv50_disp_root_func
gf119_disp_root = {
	.init = gf119_disp_root_init,
	.fini = gf119_disp_root_fini,
	.dmac = {
		&gf119_disp_core_oclass,
		&gf119_disp_base_oclass,
		&gf119_disp_ovly_oclass,
	},
	.pioc = {
		&gf119_disp_oimm_oclass,
		&gf119_disp_curs_oclass,
	},
};

static int
gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
		    void *data, u32 size, struct nvkm_object **pobject)
{
	return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
				   data, size, pobject);
}

const struct nvkm_disp_oclass
gf119_disp_root_oclass = {
	.base.oclass = GF110_DISP,
	.base.minver = -1,
	.base.maxver = -1,
	.ctor = gf119_disp_root_new,
};
Commit	Line	Data
2a7909c0 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24	#include "rootnv50.h"
	25	#include "dmacnv50.h"
	26
	27	#include <core/client.h>
	28	#include <core/ramht.h>
	29	#include <subdev/timer.h>
	30
	31	#include <nvif/class.h>
7568b106	32	#include <nvif/cl5070.h>
2a7909c0 BS	33	#include <nvif/unpack.h>
	34
	35	int
	36	gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
	37	{
	38	struct nvkm_device *device = disp->base.engine.subdev.device;
	39	const u32 total = nvkm_rd32(device, 0x640414 + (head * 0x300));
	40	const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300));
	41	const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300));
	42	union {
7568b106	43	struct nv50_disp_scanoutpos_v0 v0;
2a7909c0 BS	44	} *args = data;
	45	int ret;
	46
	47	nvif_ioctl(object, "disp scanoutpos size %d\n", size);
	48	if (nvif_unpack(args->v0, 0, 0, false)) {
	49	nvif_ioctl(object, "disp scanoutpos vers %d\n",
	50	args->v0.version);
	51	args->v0.vblanke = (blanke & 0xffff0000) >> 16;
	52	args->v0.hblanke = (blanke & 0x0000ffff);
	53	args->v0.vblanks = (blanks & 0xffff0000) >> 16;
	54	args->v0.hblanks = (blanks & 0x0000ffff);
	55	args->v0.vtotal = ( total & 0xffff0000) >> 16;
	56	args->v0.htotal = ( total & 0x0000ffff);
	57	args->v0.time[0] = ktime_to_ns(ktime_get());
	58	args->v0.vline = /* vline read locks hline */
	59	nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
	60	args->v0.time[1] = ktime_to_ns(ktime_get());
	61	args->v0.hline =
	62	nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
	63	} else
	64	return ret;
	65
	66	return 0;
	67	}
	68
0ce41e3c BS	69	void
0ce41e3c BS	70	gf119_disp_root_fini(struct nv50_disp_root *root)
2a7909c0	71	{
0ce41e3c BS	72	struct nvkm_device *device = root->disp->base.engine.subdev.device;
	73	/* disable all interrupts */
	74	nvkm_wr32(device, 0x6100b0, 0x00000000);
	75	}
	76
	77	int
	78	gf119_disp_root_init(struct nv50_disp_root *root)
	79	{
	80	struct nv50_disp *disp = root->disp;
2a7909c0	81	struct nvkm_device *device = disp->base.engine.subdev.device;
2a7909c0	82	u32 tmp;
0ce41e3c	83	int i;
2a7909c0 BS	84
	85	/* The below segments of code copying values from one register to
	86	* another appear to inform EVO of the display capabilities or
	87	* something similar.
	88	*/
	89
	90	/* ... CRTC caps */
70aa8670	91	for (i = 0; i < disp->base.head.nr; i++) {
2a7909c0 BS	92	tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
	93	nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
	94	tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
	95	nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp);
	96	tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
	97	nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp);
	98	}
	99
	100	/* ... DAC caps */
70aa8670	101	for (i = 0; i < disp->func->dac.nr; i++) {
2a7909c0 BS	102	tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
	103	nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
	104	}
	105
	106	/* ... SOR caps */
70aa8670	107	for (i = 0; i < disp->func->sor.nr; i++) {
2a7909c0 BS	108	tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
	109	nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
	110	}
	111
	112	/* steal display away from vbios, or something like that */
	113	if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
	114	nvkm_wr32(device, 0x6100ac, 0x00000100);
	115	nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
	116	if (nvkm_msec(device, 2000,
	117	if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
	118	break;
	119	) < 0)
	120	return -EBUSY;
	121	}
	122
	123	/* point at display engine memory area (hash table, objects) */
0ce41e3c	124	nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) \| 9);
2a7909c0 BS	125
	126	/* enable supervisor interrupts, disable everything else */
	127	nvkm_wr32(device, 0x610090, 0x00000000);
	128	nvkm_wr32(device, 0x6100a0, 0x00000000);
	129	nvkm_wr32(device, 0x6100b0, 0x00000307);
	130
	131	/* disable underflow reporting, preventing an intermittent issue
	132	* on some gk104 boards where the production vbios left this
	133	* setting enabled by default.
	134	*
	135	* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
	136	*/
70aa8670	137	for (i = 0; i < disp->base.head.nr; i++)
2a7909c0 BS	138	nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
	139
	140	return 0;
	141	}
	142
0ce41e3c BS	143	static const struct nv50_disp_root_func
0ce41e3c BS	144	gf119_disp_root = {
2a7909c0 BS	145	.init = gf119_disp_root_init,
2a7909c0 BS	146	.fini = gf119_disp_root_fini,
0ce41e3c BS	147	.dmac = {
	148	&gf119_disp_core_oclass,
	149	&gf119_disp_base_oclass,
	150	&gf119_disp_ovly_oclass,
	151	},
	152	.pioc = {
	153	&gf119_disp_oimm_oclass,
	154	&gf119_disp_curs_oclass,
	155	},
2a7909c0 BS	156	};
2a7909c0 BS	157
0ce41e3c BS	158	static int
	159	gf119_disp_root_new(struct nvkm_disp disp, const struct nvkm_oclass oclass,
	160	void data, u32 size, struct nvkm_object *pobject)
	161	{
	162	return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
	163	data, size, pobject);
	164	}
2a7909c0	165
0ce41e3c BS	166	const struct nvkm_disp_oclass
	167	gf119_disp_root_oclass = {
	168	.base.oclass = GF110_DISP,
	169	.base.minver = -1,
	170	.base.maxver = -1,
	171	.ctor = gf119_disp_root_new,
2a7909c0	172	};