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e3aaa946 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
a0fd4ec8 | 22 | #include <engine/falcon.h> |
5025407b | 23 | |
e3aaa946 BS |
24 | #include <subdev/timer.h> |
25 | ||
9b234db3 | 26 | void |
5025407b | 27 | nvkm_falcon_intr(struct nvkm_subdev *subdev) |
9b234db3 | 28 | { |
5025407b | 29 | struct nvkm_falcon *falcon = (void *)subdev; |
63902181 BS |
30 | struct nvkm_device *device = falcon->engine.subdev.device; |
31 | const u32 base = falcon->addr; | |
32 | u32 dispatch = nvkm_rd32(device, base + 0x01c); | |
33 | u32 intr = nvkm_rd32(device, base + 0x008) & dispatch & ~(dispatch >> 16); | |
9b234db3 ML |
34 | |
35 | if (intr & 0x00000010) { | |
64b5ce1f | 36 | nvkm_debug(subdev, "ucode halted\n"); |
63902181 | 37 | nvkm_wr32(device, base + 0x004, 0x00000010); |
9b234db3 ML |
38 | intr &= ~0x00000010; |
39 | } | |
40 | ||
41 | if (intr) { | |
64b5ce1f | 42 | nvkm_error(subdev, "intr %08x\n", intr); |
63902181 | 43 | nvkm_wr32(device, base + 0x004, intr); |
9b234db3 ML |
44 | } |
45 | } | |
46 | ||
90d6db16 IM |
47 | static void * |
48 | vmemdup(const void *src, size_t len) | |
49 | { | |
50 | void *p = vmalloc(len); | |
51 | ||
52 | if (p) | |
53 | memcpy(p, src, len); | |
54 | return p; | |
55 | } | |
56 | ||
e3aaa946 | 57 | int |
5025407b | 58 | _nvkm_falcon_init(struct nvkm_object *object) |
e3aaa946 | 59 | { |
5025407b | 60 | struct nvkm_falcon *falcon = (void *)object; |
64b5ce1f BS |
61 | struct nvkm_subdev *subdev = &falcon->engine.subdev; |
62 | struct nvkm_device *device = subdev->device; | |
e3aaa946 BS |
63 | const struct firmware *fw; |
64 | char name[32] = "internal"; | |
63902181 | 65 | const u32 base = falcon->addr; |
e3aaa946 BS |
66 | int ret, i; |
67 | u32 caps; | |
68 | ||
69 | /* enable engine, and determine its capabilities */ | |
b26ada6f | 70 | ret = nvkm_engine_init(&falcon->engine); |
e3aaa946 BS |
71 | if (ret) |
72 | return ret; | |
73 | ||
74 | if (device->chipset < 0xa3 || | |
75 | device->chipset == 0xaa || device->chipset == 0xac) { | |
76 | falcon->version = 0; | |
77 | falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; | |
78 | } else { | |
63902181 | 79 | caps = nvkm_rd32(device, base + 0x12c); |
e3aaa946 BS |
80 | falcon->version = (caps & 0x0000000f); |
81 | falcon->secret = (caps & 0x00000030) >> 4; | |
82 | } | |
83 | ||
63902181 | 84 | caps = nvkm_rd32(device, base + 0x108); |
e3aaa946 BS |
85 | falcon->code.limit = (caps & 0x000001ff) << 8; |
86 | falcon->data.limit = (caps & 0x0003fe00) >> 1; | |
87 | ||
64b5ce1f BS |
88 | nvkm_debug(subdev, "falcon version: %d\n", falcon->version); |
89 | nvkm_debug(subdev, "secret level: %d\n", falcon->secret); | |
90 | nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit); | |
91 | nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit); | |
e3aaa946 BS |
92 | |
93 | /* wait for 'uc halted' to be signalled before continuing */ | |
1e98380c | 94 | if (falcon->secret && falcon->version < 4) { |
6ed5c168 BS |
95 | if (!falcon->version) { |
96 | nvkm_msec(device, 2000, | |
63902181 | 97 | if (nvkm_rd32(device, base + 0x008) & 0x00000010) |
6ed5c168 BS |
98 | break; |
99 | ); | |
100 | } else { | |
101 | nvkm_msec(device, 2000, | |
63902181 | 102 | if (!(nvkm_rd32(device, base + 0x180) & 0x80000000)) |
6ed5c168 BS |
103 | break; |
104 | ); | |
105 | } | |
63902181 | 106 | nvkm_wr32(device, base + 0x004, 0x00000010); |
e3aaa946 BS |
107 | } |
108 | ||
109 | /* disable all interrupts */ | |
63902181 | 110 | nvkm_wr32(device, base + 0x014, 0xffffffff); |
e3aaa946 BS |
111 | |
112 | /* no default ucode provided by the engine implementation, try and | |
113 | * locate a "self-bootstrapping" firmware image for the engine | |
114 | */ | |
115 | if (!falcon->code.data) { | |
116 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", | |
117 | device->chipset, falcon->addr >> 12); | |
118 | ||
420b9469 | 119 | ret = request_firmware(&fw, name, nv_device_base(device)); |
e3aaa946 | 120 | if (ret == 0) { |
90d6db16 | 121 | falcon->code.data = vmemdup(fw->data, fw->size); |
e3aaa946 BS |
122 | falcon->code.size = fw->size; |
123 | falcon->data.data = NULL; | |
124 | falcon->data.size = 0; | |
125 | release_firmware(fw); | |
126 | } | |
127 | ||
128 | falcon->external = true; | |
129 | } | |
130 | ||
131 | /* next step is to try and load "static code/data segment" firmware | |
132 | * images for the engine | |
133 | */ | |
134 | if (!falcon->code.data) { | |
135 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", | |
136 | device->chipset, falcon->addr >> 12); | |
137 | ||
420b9469 | 138 | ret = request_firmware(&fw, name, nv_device_base(device)); |
e3aaa946 | 139 | if (ret) { |
64b5ce1f | 140 | nvkm_error(subdev, "unable to load firmware data\n"); |
e3aaa946 BS |
141 | return ret; |
142 | } | |
143 | ||
90d6db16 | 144 | falcon->data.data = vmemdup(fw->data, fw->size); |
e3aaa946 BS |
145 | falcon->data.size = fw->size; |
146 | release_firmware(fw); | |
147 | if (!falcon->data.data) | |
148 | return -ENOMEM; | |
149 | ||
150 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc", | |
151 | device->chipset, falcon->addr >> 12); | |
152 | ||
420b9469 | 153 | ret = request_firmware(&fw, name, nv_device_base(device)); |
e3aaa946 | 154 | if (ret) { |
64b5ce1f | 155 | nvkm_error(subdev, "unable to load firmware code\n"); |
e3aaa946 BS |
156 | return ret; |
157 | } | |
158 | ||
90d6db16 | 159 | falcon->code.data = vmemdup(fw->data, fw->size); |
e3aaa946 BS |
160 | falcon->code.size = fw->size; |
161 | release_firmware(fw); | |
162 | if (!falcon->code.data) | |
163 | return -ENOMEM; | |
164 | } | |
165 | ||
64b5ce1f BS |
166 | nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ? |
167 | "static code/data segments" : "self-bootstrapping"); | |
e3aaa946 BS |
168 | |
169 | /* ensure any "self-bootstrapping" firmware image is in vram */ | |
170 | if (!falcon->data.data && !falcon->core) { | |
5025407b BS |
171 | ret = nvkm_gpuobj_new(object->parent, NULL, falcon->code.size, |
172 | 256, 0, &falcon->core); | |
e3aaa946 | 173 | if (ret) { |
64b5ce1f | 174 | nvkm_error(subdev, "core allocation failed, %d\n", ret); |
e3aaa946 BS |
175 | return ret; |
176 | } | |
177 | ||
9cc264a3 | 178 | nvkm_kmap(falcon->core); |
e3aaa946 | 179 | for (i = 0; i < falcon->code.size; i += 4) |
9cc264a3 BS |
180 | nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]); |
181 | nvkm_done(falcon->core); | |
e3aaa946 BS |
182 | } |
183 | ||
184 | /* upload firmware bootloader (or the full code segments) */ | |
185 | if (falcon->core) { | |
186 | if (device->card_type < NV_C0) | |
63902181 | 187 | nvkm_wr32(device, base + 0x618, 0x04000000); |
e3aaa946 | 188 | else |
63902181 BS |
189 | nvkm_wr32(device, base + 0x618, 0x00000114); |
190 | nvkm_wr32(device, base + 0x11c, 0); | |
191 | nvkm_wr32(device, base + 0x110, falcon->core->addr >> 8); | |
192 | nvkm_wr32(device, base + 0x114, 0); | |
193 | nvkm_wr32(device, base + 0x118, 0x00006610); | |
e3aaa946 BS |
194 | } else { |
195 | if (falcon->code.size > falcon->code.limit || | |
196 | falcon->data.size > falcon->data.limit) { | |
64b5ce1f | 197 | nvkm_error(subdev, "ucode exceeds falcon limit(s)\n"); |
e3aaa946 BS |
198 | return -EINVAL; |
199 | } | |
200 | ||
201 | if (falcon->version < 3) { | |
63902181 | 202 | nvkm_wr32(device, base + 0xff8, 0x00100000); |
e3aaa946 | 203 | for (i = 0; i < falcon->code.size / 4; i++) |
63902181 | 204 | nvkm_wr32(device, base + 0xff4, falcon->code.data[i]); |
e3aaa946 | 205 | } else { |
63902181 | 206 | nvkm_wr32(device, base + 0x180, 0x01000000); |
e3aaa946 BS |
207 | for (i = 0; i < falcon->code.size / 4; i++) { |
208 | if ((i & 0x3f) == 0) | |
63902181 BS |
209 | nvkm_wr32(device, base + 0x188, i >> 6); |
210 | nvkm_wr32(device, base + 0x184, falcon->code.data[i]); | |
e3aaa946 BS |
211 | } |
212 | } | |
213 | } | |
214 | ||
215 | /* upload data segment (if necessary), zeroing the remainder */ | |
216 | if (falcon->version < 3) { | |
63902181 | 217 | nvkm_wr32(device, base + 0xff8, 0x00000000); |
e3aaa946 | 218 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) |
63902181 | 219 | nvkm_wr32(device, base + 0xff4, falcon->data.data[i]); |
e3aaa946 | 220 | for (; i < falcon->data.limit; i += 4) |
63902181 | 221 | nvkm_wr32(device, base + 0xff4, 0x00000000); |
e3aaa946 | 222 | } else { |
63902181 | 223 | nvkm_wr32(device, base + 0x1c0, 0x01000000); |
e3aaa946 | 224 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) |
63902181 | 225 | nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]); |
e3aaa946 | 226 | for (; i < falcon->data.limit / 4; i++) |
63902181 | 227 | nvkm_wr32(device, base + 0x1c4, 0x00000000); |
e3aaa946 BS |
228 | } |
229 | ||
230 | /* start it running */ | |
63902181 BS |
231 | nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ |
232 | nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ | |
233 | nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ | |
234 | nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ | |
e3aaa946 BS |
235 | return 0; |
236 | } | |
237 | ||
238 | int | |
5025407b | 239 | _nvkm_falcon_fini(struct nvkm_object *object, bool suspend) |
e3aaa946 | 240 | { |
5025407b | 241 | struct nvkm_falcon *falcon = (void *)object; |
63902181 BS |
242 | struct nvkm_device *device = falcon->engine.subdev.device; |
243 | const u32 base = falcon->addr; | |
e3aaa946 BS |
244 | |
245 | if (!suspend) { | |
5025407b | 246 | nvkm_gpuobj_ref(NULL, &falcon->core); |
e3aaa946 | 247 | if (falcon->external) { |
90d6db16 IM |
248 | vfree(falcon->data.data); |
249 | vfree(falcon->code.data); | |
e3aaa946 BS |
250 | falcon->code.data = NULL; |
251 | } | |
252 | } | |
253 | ||
63902181 BS |
254 | nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); |
255 | nvkm_wr32(device, base + 0x014, 0xffffffff); | |
e3aaa946 | 256 | |
b26ada6f | 257 | return nvkm_engine_fini(&falcon->engine, suspend); |
e3aaa946 BS |
258 | } |
259 | ||
260 | int | |
5025407b BS |
261 | nvkm_falcon_create_(struct nvkm_object *parent, struct nvkm_object *engine, |
262 | struct nvkm_oclass *oclass, u32 addr, bool enable, | |
263 | const char *iname, const char *fname, | |
264 | int length, void **pobject) | |
e3aaa946 | 265 | { |
5025407b | 266 | struct nvkm_falcon *falcon; |
e3aaa946 BS |
267 | int ret; |
268 | ||
5025407b BS |
269 | ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, |
270 | fname, length, pobject); | |
e3aaa946 BS |
271 | falcon = *pobject; |
272 | if (ret) | |
273 | return ret; | |
274 | ||
275 | falcon->addr = addr; | |
276 | return 0; | |
277 | } |