[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / ctxgf117.c

/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs <bskeggs@redhat.com>
 */
#include "ctxgf100.h"

#include <subdev/fb.h>
#include <subdev/mc.h>

/*******************************************************************************
 * PGRAPH context register lists
 ******************************************************************************/

static const struct gf100_gr_init
gf117_grctx_init_ds_0[] = {
	{ 0x405800,   1, 0x04, 0x0f8000bf },
	{ 0x405830,   1, 0x04, 0x02180324 },
	{ 0x405834,   1, 0x04, 0x08000000 },
	{ 0x405838,   1, 0x04, 0x00000000 },
	{ 0x405854,   1, 0x04, 0x00000000 },
	{ 0x405870,   4, 0x04, 0x00000001 },
	{ 0x405a00,   2, 0x04, 0x00000000 },
	{ 0x405a18,   1, 0x04, 0x00000000 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_pd_0[] = {
	{ 0x406020,   1, 0x04, 0x000103c1 },
	{ 0x406028,   4, 0x04, 0x00000001 },
	{ 0x4064a8,   1, 0x04, 0x00000000 },
	{ 0x4064ac,   1, 0x04, 0x00003fff },
	{ 0x4064b4,   3, 0x04, 0x00000000 },
	{ 0x4064c0,   1, 0x04, 0x801a0078 },
	{ 0x4064c4,   1, 0x04, 0x00c9ffff },
	{ 0x4064d0,   8, 0x04, 0x00000000 },
	{}
};

static const struct gf100_gr_pack
gf117_grctx_pack_hub[] = {
	{ gf100_grctx_init_main_0 },
	{ gf119_grctx_init_fe_0 },
	{ gf100_grctx_init_pri_0 },
	{ gf100_grctx_init_memfmt_0 },
	{ gf117_grctx_init_ds_0 },
	{ gf117_grctx_init_pd_0 },
	{ gf100_grctx_init_rstr2d_0 },
	{ gf100_grctx_init_scc_0 },
	{ gf119_grctx_init_be_0 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_setup_0[] = {
	{ 0x418800,   1, 0x04, 0x7006860a },
	{ 0x418808,   3, 0x04, 0x00000000 },
	{ 0x418828,   1, 0x04, 0x00008442 },
	{ 0x418830,   1, 0x04, 0x10000001 },
	{ 0x4188d8,   1, 0x04, 0x00000008 },
	{ 0x4188e0,   1, 0x04, 0x01000000 },
	{ 0x4188e8,   5, 0x04, 0x00000000 },
	{ 0x4188fc,   1, 0x04, 0x20100018 },
	{}
};

static const struct gf100_gr_pack
gf117_grctx_pack_gpc[] = {
	{ gf100_grctx_init_gpc_unk_0 },
	{ gf119_grctx_init_prop_0 },
	{ gf119_grctx_init_gpc_unk_1 },
	{ gf117_grctx_init_setup_0 },
	{ gf100_grctx_init_zcull_0 },
	{ gf119_grctx_init_crstr_0 },
	{ gf108_grctx_init_gpm_0 },
	{ gf100_grctx_init_gcc_0 },
	{}
};

const struct gf100_gr_init
gf117_grctx_init_pe_0[] = {
	{ 0x419848,   1, 0x04, 0x00000000 },
	{ 0x419864,   1, 0x04, 0x00000129 },
	{ 0x419888,   1, 0x04, 0x00000000 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_tex_0[] = {
	{ 0x419a00,   1, 0x04, 0x000001f0 },
	{ 0x419a04,   1, 0x04, 0x00000001 },
	{ 0x419a08,   1, 0x04, 0x00000023 },
	{ 0x419a0c,   1, 0x04, 0x00020000 },
	{ 0x419a10,   1, 0x04, 0x00000000 },
	{ 0x419a14,   1, 0x04, 0x00000200 },
	{ 0x419a1c,   1, 0x04, 0x00008000 },
	{ 0x419a20,   1, 0x04, 0x00000800 },
	{ 0x419ac4,   1, 0x04, 0x0017f440 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_mpc_0[] = {
	{ 0x419c00,   1, 0x04, 0x0000000a },
	{ 0x419c04,   1, 0x04, 0x00000006 },
	{ 0x419c08,   1, 0x04, 0x00000002 },
	{ 0x419c20,   1, 0x04, 0x00000000 },
	{ 0x419c24,   1, 0x04, 0x00084210 },
	{ 0x419c28,   1, 0x04, 0x3efbefbe },
	{}
};

static const struct gf100_gr_pack
gf117_grctx_pack_tpc[] = {
	{ gf117_grctx_init_pe_0 },
	{ gf117_grctx_init_tex_0 },
	{ gf117_grctx_init_mpc_0 },
	{ gf104_grctx_init_l1c_0 },
	{ gf119_grctx_init_sm_0 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_pes_0[] = {
	{ 0x41be24,   1, 0x04, 0x00000002 },
	{}
};

static const struct gf100_gr_init
gf117_grctx_init_cbm_0[] = {
	{ 0x41bec0,   1, 0x04, 0x12180000 },
	{ 0x41bec4,   1, 0x04, 0x00003fff },
	{ 0x41bee4,   1, 0x04, 0x03240218 },
	{}
};

const struct gf100_gr_init
gf117_grctx_init_wwdx_0[] = {
	{ 0x41bf00,   1, 0x04, 0x0a418820 },
	{ 0x41bf04,   1, 0x04, 0x062080e6 },
	{ 0x41bf08,   1, 0x04, 0x020398a4 },
	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
	{ 0x41bf10,   1, 0x04, 0x0a418820 },
	{ 0x41bf14,   1, 0x04, 0x000000e6 },
	{ 0x41bfd0,   1, 0x04, 0x00900103 },
	{ 0x41bfe0,   1, 0x04, 0x00400001 },
	{ 0x41bfe4,   1, 0x04, 0x00000000 },
	{}
};

static const struct gf100_gr_pack
gf117_grctx_pack_ppc[] = {
	{ gf117_grctx_init_pes_0 },
	{ gf117_grctx_init_cbm_0 },
	{ gf117_grctx_init_wwdx_0 },
	{}
};

/*******************************************************************************
 * PGRAPH context implementation
 ******************************************************************************/

void
gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
	struct gf100_gr *gr = info->gr;
	const struct gf100_grctx_func *grctx = gr->func->grctx;
	const u32  alpha = grctx->alpha_nr;
	const u32   beta = grctx->attrib_nr;
	const u32   size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
	const u32 access = NV_MEM_ACCESS_RW;
	const int s = 12;
	const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
	const int timeslice_mode = 1;
	const int max_batches = 0xffff;
	u32 bo = 0;
	u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
	int gpc, ppc;

	mmio_refn(info, 0x418810, 0x80000000, s, b);
	mmio_refn(info, 0x419848, 0x10000000, s, b);
	mmio_wr32(info, 0x405830, (beta << 16) | alpha);
	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
			const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
			const u32 b =  beta * gr->ppc_tpc_nr[gpc][ppc];
			const u32 t = timeslice_mode;
			const u32 o = PPC_UNIT(gpc, ppc, 0);
			if (!(gr->ppc_mask[gpc] & (1 << ppc)))
				continue;
			mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
			mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
			bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
			mmio_wr32(info, o + 0xe4, (a << 16) | ao);
			ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
		}
	}
}

void
gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	const struct gf100_grctx_func *grctx = gr->func->grctx;
	u32 idle_timeout;
	int i;

	nvkm_mc_unk260(device, 0);

	gf100_gr_mmio(gr, grctx->hub);
	gf100_gr_mmio(gr, grctx->gpc);
	gf100_gr_mmio(gr, grctx->zcull);
	gf100_gr_mmio(gr, grctx->tpc);
	gf100_gr_mmio(gr, grctx->ppc);

	idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);

	grctx->bundle(info);
	grctx->pagepool(info);
	grctx->attrib(info);
	grctx->unkn(gr);

	gf100_grctx_generate_tpcid(gr);
	gf100_grctx_generate_r406028(gr);
	gf100_grctx_generate_r4060a8(gr);
	gk104_grctx_generate_r418bb8(gr);
	gf100_grctx_generate_r406800(gr);

	for (i = 0; i < 8; i++)
		nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);

	gf100_gr_icmd(gr, grctx->icmd);
	nvkm_wr32(device, 0x404154, idle_timeout);
	gf100_gr_mthd(gr, grctx->mthd);
	nvkm_mc_unk260(device, 1);
}

const struct gf100_grctx_func
gf117_grctx = {
	.main  = gf117_grctx_generate_main,
	.unkn  = gk104_grctx_generate_unkn,
	.hub   = gf117_grctx_pack_hub,
	.gpc   = gf117_grctx_pack_gpc,
	.zcull = gf100_grctx_pack_zcull,
	.tpc   = gf117_grctx_pack_tpc,
	.ppc   = gf117_grctx_pack_ppc,
	.icmd  = gf119_grctx_pack_icmd,
	.mthd  = gf119_grctx_pack_mthd,
	.bundle = gf100_grctx_generate_bundle,
	.bundle_size = 0x1800,
	.pagepool = gf100_grctx_generate_pagepool,
	.pagepool_size = 0x8000,
	.attrib = gf117_grctx_generate_attrib,
	.attrib_nr_max = 0x324,
	.attrib_nr = 0x218,
	.alpha_nr_max = 0x7ff,
	.alpha_nr = 0x324,
};
Commit	Line	Data
26410c67 ML	1	/*
	2	* Copyright 2013 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs <bskeggs@redhat.com>
	23	*/
e3c71eb2	24	#include "ctxgf100.h"
26410c67	25
e3c71eb2 BS	26	#include <subdev/fb.h>
e3c71eb2 BS	27	#include <subdev/mc.h>
26410c67	28
c33b1e8c BS	29	/*******************************************************************************
	30	* PGRAPH context register lists
	31	******************************************************************************/
26410c67	32
e3c71eb2 BS	33	static const struct gf100_gr_init
e3c71eb2 BS	34	gf117_grctx_init_ds_0[] = {
26410c67 ML	35	{ 0x405800, 1, 0x04, 0x0f8000bf },
	36	{ 0x405830, 1, 0x04, 0x02180324 },
	37	{ 0x405834, 1, 0x04, 0x08000000 },
	38	{ 0x405838, 1, 0x04, 0x00000000 },
	39	{ 0x405854, 1, 0x04, 0x00000000 },
	40	{ 0x405870, 4, 0x04, 0x00000001 },
	41	{ 0x405a00, 2, 0x04, 0x00000000 },
	42	{ 0x405a18, 1, 0x04, 0x00000000 },
	43	{}
	44	};
	45
e3c71eb2 BS	46	static const struct gf100_gr_init
e3c71eb2 BS	47	gf117_grctx_init_pd_0[] = {
c33b1e8c BS	48	{ 0x406020, 1, 0x04, 0x000103c1 },
c33b1e8c BS	49	{ 0x406028, 4, 0x04, 0x00000001 },
26410c67 ML	50	{ 0x4064a8, 1, 0x04, 0x00000000 },
	51	{ 0x4064ac, 1, 0x04, 0x00003fff },
	52	{ 0x4064b4, 3, 0x04, 0x00000000 },
	53	{ 0x4064c0, 1, 0x04, 0x801a0078 },
	54	{ 0x4064c4, 1, 0x04, 0x00c9ffff },
	55	{ 0x4064d0, 8, 0x04, 0x00000000 },
	56	{}
	57	};
	58
e3c71eb2 BS	59	static const struct gf100_gr_pack
	60	gf117_grctx_pack_hub[] = {
	61	{ gf100_grctx_init_main_0 },
	62	{ gf119_grctx_init_fe_0 },
	63	{ gf100_grctx_init_pri_0 },
	64	{ gf100_grctx_init_memfmt_0 },
	65	{ gf117_grctx_init_ds_0 },
	66	{ gf117_grctx_init_pd_0 },
	67	{ gf100_grctx_init_rstr2d_0 },
	68	{ gf100_grctx_init_scc_0 },
	69	{ gf119_grctx_init_be_0 },
c33b1e8c BS	70	{}
	71	};
	72
e3c71eb2 BS	73	static const struct gf100_gr_init
e3c71eb2 BS	74	gf117_grctx_init_setup_0[] = {
26410c67 ML	75	{ 0x418800, 1, 0x04, 0x7006860a },
	76	{ 0x418808, 3, 0x04, 0x00000000 },
	77	{ 0x418828, 1, 0x04, 0x00008442 },
	78	{ 0x418830, 1, 0x04, 0x10000001 },
	79	{ 0x4188d8, 1, 0x04, 0x00000008 },
	80	{ 0x4188e0, 1, 0x04, 0x01000000 },
	81	{ 0x4188e8, 5, 0x04, 0x00000000 },
	82	{ 0x4188fc, 1, 0x04, 0x20100018 },
26410c67 ML	83	{}
	84	};
	85
e3c71eb2 BS	86	static const struct gf100_gr_pack
	87	gf117_grctx_pack_gpc[] = {
	88	{ gf100_grctx_init_gpc_unk_0 },
	89	{ gf119_grctx_init_prop_0 },
	90	{ gf119_grctx_init_gpc_unk_1 },
	91	{ gf117_grctx_init_setup_0 },
	92	{ gf100_grctx_init_zcull_0 },
	93	{ gf119_grctx_init_crstr_0 },
	94	{ gf108_grctx_init_gpm_0 },
	95	{ gf100_grctx_init_gcc_0 },
c33b1e8c BS	96	{}
	97	};
	98
e3c71eb2 BS	99	const struct gf100_gr_init
e3c71eb2 BS	100	gf117_grctx_init_pe_0[] = {
26410c67 ML	101	{ 0x419848, 1, 0x04, 0x00000000 },
	102	{ 0x419864, 1, 0x04, 0x00000129 },
	103	{ 0x419888, 1, 0x04, 0x00000000 },
7e194533 BS	104	{}
	105	};
	106
e3c71eb2 BS	107	static const struct gf100_gr_init
e3c71eb2 BS	108	gf117_grctx_init_tex_0[] = {
26410c67 ML	109	{ 0x419a00, 1, 0x04, 0x000001f0 },
	110	{ 0x419a04, 1, 0x04, 0x00000001 },
	111	{ 0x419a08, 1, 0x04, 0x00000023 },
	112	{ 0x419a0c, 1, 0x04, 0x00020000 },
	113	{ 0x419a10, 1, 0x04, 0x00000000 },
	114	{ 0x419a14, 1, 0x04, 0x00000200 },
	115	{ 0x419a1c, 1, 0x04, 0x00008000 },
	116	{ 0x419a20, 1, 0x04, 0x00000800 },
	117	{ 0x419ac4, 1, 0x04, 0x0017f440 },
7e194533 BS	118	{}
	119	};
	120
e3c71eb2 BS	121	static const struct gf100_gr_init
e3c71eb2 BS	122	gf117_grctx_init_mpc_0[] = {
26410c67 ML	123	{ 0x419c00, 1, 0x04, 0x0000000a },
	124	{ 0x419c04, 1, 0x04, 0x00000006 },
	125	{ 0x419c08, 1, 0x04, 0x00000002 },
	126	{ 0x419c20, 1, 0x04, 0x00000000 },
	127	{ 0x419c24, 1, 0x04, 0x00084210 },
	128	{ 0x419c28, 1, 0x04, 0x3efbefbe },
26410c67 ML	129	{}
	130	};
	131
e3c71eb2 BS	132	static const struct gf100_gr_pack
	133	gf117_grctx_pack_tpc[] = {
	134	{ gf117_grctx_init_pe_0 },
	135	{ gf117_grctx_init_tex_0 },
	136	{ gf117_grctx_init_mpc_0 },
	137	{ gf104_grctx_init_l1c_0 },
	138	{ gf119_grctx_init_sm_0 },
c33b1e8c BS	139	{}
	140	};
	141
e3c71eb2 BS	142	static const struct gf100_gr_init
e3c71eb2 BS	143	gf117_grctx_init_pes_0[] = {
26410c67	144	{ 0x41be24, 1, 0x04, 0x00000002 },
88e98d49 BS	145	{}
	146	};
	147
e3c71eb2 BS	148	static const struct gf100_gr_init
e3c71eb2 BS	149	gf117_grctx_init_cbm_0[] = {
26410c67 ML	150	{ 0x41bec0, 1, 0x04, 0x12180000 },
	151	{ 0x41bec4, 1, 0x04, 0x00003fff },
	152	{ 0x41bee4, 1, 0x04, 0x03240218 },
88e98d49 BS	153	{}
	154	};
	155
e3c71eb2 BS	156	const struct gf100_gr_init
e3c71eb2 BS	157	gf117_grctx_init_wwdx_0[] = {
26410c67 ML	158	{ 0x41bf00, 1, 0x04, 0x0a418820 },
	159	{ 0x41bf04, 1, 0x04, 0x062080e6 },
	160	{ 0x41bf08, 1, 0x04, 0x020398a4 },
	161	{ 0x41bf0c, 1, 0x04, 0x0e629062 },
	162	{ 0x41bf10, 1, 0x04, 0x0a418820 },
	163	{ 0x41bf14, 1, 0x04, 0x000000e6 },
	164	{ 0x41bfd0, 1, 0x04, 0x00900103 },
	165	{ 0x41bfe0, 1, 0x04, 0x00400001 },
	166	{ 0x41bfe4, 1, 0x04, 0x00000000 },
	167	{}
	168	};
	169
e3c71eb2 BS	170	static const struct gf100_gr_pack
	171	gf117_grctx_pack_ppc[] = {
	172	{ gf117_grctx_init_pes_0 },
	173	{ gf117_grctx_init_cbm_0 },
	174	{ gf117_grctx_init_wwdx_0 },
c33b1e8c BS	175	{}
	176	};
	177
	178	/*******************************************************************************
	179	* PGRAPH context implementation
	180	******************************************************************************/
	181
67cfbfdf	182	void
e3c71eb2	183	gf117_grctx_generate_attrib(struct gf100_grctx *info)
26410c67	184	{
bfee3f3d	185	struct gf100_gr *gr = info->gr;
27f3d6cf BS	186	const struct gf100_grctx_func *grctx = gr->func->grctx;
	187	const u32 alpha = grctx->alpha_nr;
	188	const u32 beta = grctx->attrib_nr;
	189	const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
67cfbfdf BS	190	const u32 access = NV_MEM_ACCESS_RW;
67cfbfdf BS	191	const int s = 12;
bfee3f3d	192	const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
67cfbfdf BS	193	const int timeslice_mode = 1;
	194	const int max_batches = 0xffff;
	195	u32 bo = 0;
27f3d6cf	196	u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
67cfbfdf	197	int gpc, ppc;
26410c67	198
67cfbfdf BS	199	mmio_refn(info, 0x418810, 0x80000000, s, b);
	200	mmio_refn(info, 0x419848, 0x10000000, s, b);
	201	mmio_wr32(info, 0x405830, (beta << 16) \| alpha);
	202	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) \| max_batches);
26410c67	203
bfee3f3d BS	204	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
	205	for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
	206	const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
	207	const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
67cfbfdf BS	208	const u32 t = timeslice_mode;
67cfbfdf BS	209	const u32 o = PPC_UNIT(gpc, ppc, 0);
2fb2b3c6 BS	210	if (!(gr->ppc_mask[gpc] & (1 << ppc)))
2fb2b3c6 BS	211	continue;
67cfbfdf BS	212	mmio_skip(info, o + 0xc0, (t << 28) \| (b << 16) \| ++bo);
67cfbfdf BS	213	mmio_wr32(info, o + 0xc0, (t << 28) \| (b << 16) \| --bo);
27f3d6cf	214	bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
67cfbfdf	215	mmio_wr32(info, o + 0xe4, (a << 16) \| ao);
27f3d6cf	216	ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
67cfbfdf	217	}
26410c67	218	}
67cfbfdf BS	219	}
67cfbfdf BS	220
26410c67	221	void
bfee3f3d	222	gf117_grctx_generate_main(struct gf100_gr gr, struct gf100_grctx info)
26410c67	223	{
276836d4	224	struct nvkm_device *device = gr->base.engine.subdev.device;
27f3d6cf	225	const struct gf100_grctx_func *grctx = gr->func->grctx;
933ad445	226	u32 idle_timeout;
26410c67 ML	227	int i;
26410c67 ML	228
d3981190	229	nvkm_mc_unk260(device, 0);
26410c67	230
27f3d6cf BS	231	gf100_gr_mmio(gr, grctx->hub);
	232	gf100_gr_mmio(gr, grctx->gpc);
	233	gf100_gr_mmio(gr, grctx->zcull);
	234	gf100_gr_mmio(gr, grctx->tpc);
	235	gf100_gr_mmio(gr, grctx->ppc);
26410c67	236
933ad445	237	idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
26410c67	238
27f3d6cf BS	239	grctx->bundle(info);
	240	grctx->pagepool(info);
	241	grctx->attrib(info);
	242	grctx->unkn(gr);
26410c67	243
bfee3f3d BS	244	gf100_grctx_generate_tpcid(gr);
	245	gf100_grctx_generate_r406028(gr);
	246	gf100_grctx_generate_r4060a8(gr);
	247	gk104_grctx_generate_r418bb8(gr);
	248	gf100_grctx_generate_r406800(gr);
26410c67 ML	249
26410c67 ML	250	for (i = 0; i < 8; i++)
276836d4	251	nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
26410c67	252
27f3d6cf	253	gf100_gr_icmd(gr, grctx->icmd);
933ad445	254	nvkm_wr32(device, 0x404154, idle_timeout);
27f3d6cf	255	gf100_gr_mthd(gr, grctx->mthd);
d3981190	256	nvkm_mc_unk260(device, 1);
26410c67 ML	257	}
26410c67 ML	258
27f3d6cf BS	259	const struct gf100_grctx_func
27f3d6cf BS	260	gf117_grctx = {
e3c71eb2 BS	261	.main = gf117_grctx_generate_main,
	262	.unkn = gk104_grctx_generate_unkn,
	263	.hub = gf117_grctx_pack_hub,
	264	.gpc = gf117_grctx_pack_gpc,
	265	.zcull = gf100_grctx_pack_zcull,
	266	.tpc = gf117_grctx_pack_tpc,
	267	.ppc = gf117_grctx_pack_ppc,
	268	.icmd = gf119_grctx_pack_icmd,
	269	.mthd = gf119_grctx_pack_mthd,
	270	.bundle = gf100_grctx_generate_bundle,
aa2d58c3	271	.bundle_size = 0x1800,
e3c71eb2	272	.pagepool = gf100_grctx_generate_pagepool,
f331a15f	273	.pagepool_size = 0x8000,
e3c71eb2	274	.attrib = gf117_grctx_generate_attrib,
67cfbfdf BS	275	.attrib_nr_max = 0x324,
	276	.attrib_nr = 0x218,
	277	.alpha_nr_max = 0x7ff,
	278	.alpha_nr = 0x324,
27f3d6cf	279	};