Commit | Line | Data |
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4b223eef | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
4b223eef BS |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
e3c71eb2 BS |
24 | #include "gf100.h" |
25 | #include "ctxgf100.h" | |
26 | #include "fuc/os.h" | |
27 | ||
28 | #include <core/client.h> | |
29 | #include <core/device.h> | |
30 | #include <core/handle.h> | |
31 | #include <core/option.h> | |
32 | #include <engine/fifo.h> | |
33 | #include <subdev/fb.h> | |
34 | #include <subdev/mc.h> | |
35 | #include <subdev/timer.h> | |
36 | ||
37 | #include <nvif/class.h> | |
38 | #include <nvif/unpack.h> | |
0411de85 | 39 | |
ac9738bb BS |
40 | /******************************************************************************* |
41 | * Zero Bandwidth Clear | |
42 | ******************************************************************************/ | |
43 | ||
44 | static void | |
e3c71eb2 | 45 | gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc) |
ac9738bb BS |
46 | { |
47 | if (priv->zbc_color[zbc].format) { | |
48 | nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); | |
49 | nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); | |
50 | nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); | |
51 | nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); | |
52 | } | |
53 | nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); | |
54 | nv_wr32(priv, 0x405820, zbc); | |
55 | nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ | |
56 | } | |
57 | ||
58 | static int | |
e3c71eb2 BS |
59 | gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, |
60 | const u32 ds[4], const u32 l2[4]) | |
ac9738bb | 61 | { |
e3c71eb2 | 62 | struct nvkm_ltc *ltc = nvkm_ltc(priv); |
ac9738bb BS |
63 | int zbc = -ENOSPC, i; |
64 | ||
65 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
66 | if (priv->zbc_color[i].format) { | |
67 | if (priv->zbc_color[i].format != format) | |
68 | continue; | |
69 | if (memcmp(priv->zbc_color[i].ds, ds, sizeof( | |
70 | priv->zbc_color[i].ds))) | |
71 | continue; | |
72 | if (memcmp(priv->zbc_color[i].l2, l2, sizeof( | |
73 | priv->zbc_color[i].l2))) { | |
74 | WARN_ON(1); | |
75 | return -EINVAL; | |
76 | } | |
77 | return i; | |
78 | } else { | |
79 | zbc = (zbc < 0) ? i : zbc; | |
80 | } | |
81 | } | |
82 | ||
da7c74ea BS |
83 | if (zbc < 0) |
84 | return zbc; | |
85 | ||
ac9738bb BS |
86 | memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); |
87 | memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); | |
88 | priv->zbc_color[zbc].format = format; | |
89 | ltc->zbc_color_get(ltc, zbc, l2); | |
e3c71eb2 | 90 | gf100_gr_zbc_clear_color(priv, zbc); |
ac9738bb BS |
91 | return zbc; |
92 | } | |
93 | ||
94 | static void | |
e3c71eb2 | 95 | gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc) |
ac9738bb BS |
96 | { |
97 | if (priv->zbc_depth[zbc].format) | |
98 | nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); | |
99 | nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); | |
100 | nv_wr32(priv, 0x405820, zbc); | |
101 | nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ | |
102 | } | |
103 | ||
104 | static int | |
e3c71eb2 BS |
105 | gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, |
106 | const u32 ds, const u32 l2) | |
ac9738bb | 107 | { |
e3c71eb2 | 108 | struct nvkm_ltc *ltc = nvkm_ltc(priv); |
ac9738bb BS |
109 | int zbc = -ENOSPC, i; |
110 | ||
111 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
112 | if (priv->zbc_depth[i].format) { | |
113 | if (priv->zbc_depth[i].format != format) | |
114 | continue; | |
115 | if (priv->zbc_depth[i].ds != ds) | |
116 | continue; | |
117 | if (priv->zbc_depth[i].l2 != l2) { | |
118 | WARN_ON(1); | |
119 | return -EINVAL; | |
120 | } | |
121 | return i; | |
122 | } else { | |
123 | zbc = (zbc < 0) ? i : zbc; | |
124 | } | |
125 | } | |
126 | ||
da7c74ea BS |
127 | if (zbc < 0) |
128 | return zbc; | |
129 | ||
ac9738bb BS |
130 | priv->zbc_depth[zbc].format = format; |
131 | priv->zbc_depth[zbc].ds = ds; | |
132 | priv->zbc_depth[zbc].l2 = l2; | |
133 | ltc->zbc_depth_get(ltc, zbc, l2); | |
e3c71eb2 | 134 | gf100_gr_zbc_clear_depth(priv, zbc); |
ac9738bb BS |
135 | return zbc; |
136 | } | |
137 | ||
ebb945a9 BS |
138 | /******************************************************************************* |
139 | * Graphics object classes | |
140 | ******************************************************************************/ | |
141 | ||
ac9738bb | 142 | static int |
e3c71eb2 | 143 | gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 144 | { |
e3c71eb2 | 145 | struct gf100_gr_priv *priv = (void *)object->engine; |
ac9738bb BS |
146 | union { |
147 | struct fermi_a_zbc_color_v0 v0; | |
148 | } *args = data; | |
149 | int ret; | |
150 | ||
151 | if (nvif_unpack(args->v0, 0, 0, false)) { | |
152 | switch (args->v0.format) { | |
153 | case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: | |
154 | case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: | |
155 | case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: | |
156 | case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: | |
157 | case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: | |
158 | case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: | |
159 | case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: | |
160 | case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: | |
161 | case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: | |
162 | case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: | |
163 | case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: | |
164 | case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: | |
165 | case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: | |
166 | case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: | |
167 | case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: | |
168 | case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: | |
169 | case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: | |
170 | case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: | |
171 | case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: | |
e3c71eb2 BS |
172 | ret = gf100_gr_zbc_color_get(priv, args->v0.format, |
173 | args->v0.ds, | |
174 | args->v0.l2); | |
ac9738bb BS |
175 | if (ret >= 0) { |
176 | args->v0.index = ret; | |
177 | return 0; | |
178 | } | |
179 | break; | |
180 | default: | |
181 | return -EINVAL; | |
182 | } | |
183 | } | |
184 | ||
185 | return ret; | |
186 | } | |
187 | ||
188 | static int | |
e3c71eb2 | 189 | gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 190 | { |
e3c71eb2 | 191 | struct gf100_gr_priv *priv = (void *)object->engine; |
ac9738bb BS |
192 | union { |
193 | struct fermi_a_zbc_depth_v0 v0; | |
194 | } *args = data; | |
195 | int ret; | |
196 | ||
197 | if (nvif_unpack(args->v0, 0, 0, false)) { | |
198 | switch (args->v0.format) { | |
199 | case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: | |
e3c71eb2 BS |
200 | ret = gf100_gr_zbc_depth_get(priv, args->v0.format, |
201 | args->v0.ds, | |
202 | args->v0.l2); | |
ac9738bb BS |
203 | return (ret >= 0) ? 0 : -ENOSPC; |
204 | default: | |
205 | return -EINVAL; | |
206 | } | |
207 | } | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
212 | static int | |
e3c71eb2 | 213 | gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) |
ac9738bb BS |
214 | { |
215 | switch (mthd) { | |
216 | case FERMI_A_ZBC_COLOR: | |
e3c71eb2 | 217 | return gf100_fermi_mthd_zbc_color(object, data, size); |
ac9738bb | 218 | case FERMI_A_ZBC_DEPTH: |
e3c71eb2 | 219 | return gf100_fermi_mthd_zbc_depth(object, data, size); |
ac9738bb BS |
220 | default: |
221 | break; | |
222 | } | |
223 | return -EINVAL; | |
224 | } | |
225 | ||
e3c71eb2 BS |
226 | struct nvkm_ofuncs |
227 | gf100_fermi_ofuncs = { | |
228 | .ctor = _nvkm_object_ctor, | |
229 | .dtor = nvkm_object_destroy, | |
230 | .init = nvkm_object_init, | |
231 | .fini = nvkm_object_fini, | |
232 | .mthd = gf100_fermi_mthd, | |
ac9738bb BS |
233 | }; |
234 | ||
d6bd3803 | 235 | static int |
e3c71eb2 BS |
236 | gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, |
237 | void *pdata, u32 size) | |
d6bd3803 | 238 | { |
3d951c38 | 239 | struct gf100_gr_priv *priv = (void *)object->engine; |
d6bd3803 BS |
240 | if (size >= sizeof(u32)) { |
241 | u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; | |
242 | nv_wr32(priv, 0x419e44, data); | |
243 | nv_wr32(priv, 0x419e4c, data); | |
244 | return 0; | |
245 | } | |
246 | return -EINVAL; | |
247 | } | |
248 | ||
e3c71eb2 BS |
249 | struct nvkm_omthds |
250 | gf100_gr_9097_omthds[] = { | |
251 | { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, | |
d6bd3803 BS |
252 | {} |
253 | }; | |
254 | ||
e3c71eb2 BS |
255 | struct nvkm_omthds |
256 | gf100_gr_90c0_omthds[] = { | |
257 | { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, | |
d6bd3803 BS |
258 | {} |
259 | }; | |
260 | ||
e3c71eb2 BS |
261 | struct nvkm_oclass |
262 | gf100_gr_sclass[] = { | |
3740c825 BS |
263 | { FERMI_TWOD_A, &nvkm_object_ofuncs }, |
264 | { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, | |
e3c71eb2 BS |
265 | { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, |
266 | { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, | |
ebb945a9 BS |
267 | {} |
268 | }; | |
269 | ||
ebb945a9 BS |
270 | /******************************************************************************* |
271 | * PGRAPH context | |
272 | ******************************************************************************/ | |
966a5b7d | 273 | |
ac1499d9 | 274 | int |
e3c71eb2 BS |
275 | gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
276 | struct nvkm_oclass *oclass, void *args, u32 size, | |
277 | struct nvkm_object **pobject) | |
966a5b7d | 278 | { |
e3c71eb2 BS |
279 | struct nvkm_vm *vm = nvkm_client(parent)->vm; |
280 | struct gf100_gr_priv *priv = (void *)engine; | |
281 | struct gf100_gr_data *data = priv->mmio_data; | |
282 | struct gf100_gr_mmio *mmio = priv->mmio_list; | |
283 | struct gf100_gr_chan *chan; | |
966a5b7d | 284 | int ret, i; |
966a5b7d | 285 | |
ebb945a9 | 286 | /* allocate memory for context, and fill with default values */ |
e3c71eb2 BS |
287 | ret = nvkm_gr_context_create(parent, engine, oclass, NULL, |
288 | priv->size, 0x100, | |
289 | NVOBJ_FLAG_ZERO_ALLOC, &chan); | |
ebb945a9 | 290 | *pobject = nv_object(chan); |
966a5b7d BS |
291 | if (ret) |
292 | return ret; | |
293 | ||
ac1499d9 BS |
294 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
295 | * fuc to modify some per-context register settings on first load | |
296 | * of the context. | |
297 | */ | |
e3c71eb2 BS |
298 | ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, |
299 | &chan->mmio); | |
73a60c0d BS |
300 | if (ret) |
301 | return ret; | |
302 | ||
e3c71eb2 BS |
303 | ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, |
304 | NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, | |
305 | &chan->mmio_vma); | |
73a60c0d BS |
306 | if (ret) |
307 | return ret; | |
308 | ||
ac1499d9 BS |
309 | /* allocate buffers referenced by mmio list */ |
310 | for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { | |
e3c71eb2 BS |
311 | ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, |
312 | data->align, 0, &chan->data[i].mem); | |
ac1499d9 BS |
313 | if (ret) |
314 | return ret; | |
73a60c0d | 315 | |
e3c71eb2 BS |
316 | ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, |
317 | &chan->data[i].vma); | |
ac1499d9 BS |
318 | if (ret) |
319 | return ret; | |
966a5b7d | 320 | |
ac1499d9 | 321 | data++; |
966a5b7d BS |
322 | } |
323 | ||
ac1499d9 BS |
324 | /* finally, fill in the mmio list and point the context at it */ |
325 | for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { | |
326 | u32 addr = mmio->addr; | |
327 | u32 data = mmio->data; | |
966a5b7d | 328 | |
694c6caf | 329 | if (mmio->buffer >= 0) { |
ebb945a9 | 330 | u64 info = chan->data[mmio->buffer].vma.offset; |
ac1499d9 BS |
331 | data |= info >> mmio->shift; |
332 | } | |
73a60c0d | 333 | |
ebb945a9 BS |
334 | nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); |
335 | nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); | |
ac1499d9 BS |
336 | mmio++; |
337 | } | |
73a60c0d | 338 | |
ac1499d9 | 339 | for (i = 0; i < priv->size; i += 4) |
ebb945a9 | 340 | nv_wo32(chan, i, priv->data[i / 4]); |
966a5b7d | 341 | |
ac1499d9 | 342 | if (!priv->firmware) { |
ebb945a9 BS |
343 | nv_wo32(chan, 0x00, chan->mmio_nr / 2); |
344 | nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); | |
0411de85 | 345 | } else { |
ebb945a9 BS |
346 | nv_wo32(chan, 0xf4, 0); |
347 | nv_wo32(chan, 0xf8, 0); | |
348 | nv_wo32(chan, 0x10, chan->mmio_nr / 2); | |
349 | nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); | |
350 | nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); | |
351 | nv_wo32(chan, 0x1c, 1); | |
352 | nv_wo32(chan, 0x20, 0); | |
353 | nv_wo32(chan, 0x28, 0); | |
354 | nv_wo32(chan, 0x2c, 0); | |
0411de85 | 355 | } |
966a5b7d | 356 | |
ebb945a9 | 357 | return 0; |
4b223eef BS |
358 | } |
359 | ||
ac1499d9 | 360 | void |
e3c71eb2 | 361 | gf100_gr_context_dtor(struct nvkm_object *object) |
4b223eef | 362 | { |
e3c71eb2 | 363 | struct gf100_gr_chan *chan = (void *)object; |
ac1499d9 BS |
364 | int i; |
365 | ||
ebb945a9 | 366 | for (i = 0; i < ARRAY_SIZE(chan->data); i++) { |
e3c71eb2 BS |
367 | nvkm_gpuobj_unmap(&chan->data[i].vma); |
368 | nvkm_gpuobj_ref(NULL, &chan->data[i].mem); | |
ac1499d9 | 369 | } |
966a5b7d | 370 | |
e3c71eb2 BS |
371 | nvkm_gpuobj_unmap(&chan->mmio_vma); |
372 | nvkm_gpuobj_ref(NULL, &chan->mmio); | |
ac1499d9 | 373 | |
e3c71eb2 | 374 | nvkm_gr_context_destroy(&chan->base); |
4b223eef BS |
375 | } |
376 | ||
ebb945a9 | 377 | /******************************************************************************* |
c33b1e8c | 378 | * PGRAPH register lists |
ebb945a9 BS |
379 | ******************************************************************************/ |
380 | ||
e3c71eb2 BS |
381 | const struct gf100_gr_init |
382 | gf100_gr_init_main_0[] = { | |
30f4e087 BS |
383 | { 0x400080, 1, 0x04, 0x003083c2 }, |
384 | { 0x400088, 1, 0x04, 0x00006fe7 }, | |
385 | { 0x40008c, 1, 0x04, 0x00000000 }, | |
386 | { 0x400090, 1, 0x04, 0x00000030 }, | |
387 | { 0x40013c, 1, 0x04, 0x013901f7 }, | |
388 | { 0x400140, 1, 0x04, 0x00000100 }, | |
389 | { 0x400144, 1, 0x04, 0x00000000 }, | |
390 | { 0x400148, 1, 0x04, 0x00000110 }, | |
391 | { 0x400138, 1, 0x04, 0x00000000 }, | |
392 | { 0x400130, 2, 0x04, 0x00000000 }, | |
393 | { 0x400124, 1, 0x04, 0x00000002 }, | |
394 | {} | |
395 | }; | |
396 | ||
e3c71eb2 BS |
397 | const struct gf100_gr_init |
398 | gf100_gr_init_fe_0[] = { | |
30f4e087 BS |
399 | { 0x40415c, 1, 0x04, 0x00000000 }, |
400 | { 0x404170, 1, 0x04, 0x00000000 }, | |
401 | {} | |
402 | }; | |
403 | ||
e3c71eb2 BS |
404 | const struct gf100_gr_init |
405 | gf100_gr_init_pri_0[] = { | |
30f4e087 BS |
406 | { 0x404488, 2, 0x04, 0x00000000 }, |
407 | {} | |
408 | }; | |
409 | ||
e3c71eb2 BS |
410 | const struct gf100_gr_init |
411 | gf100_gr_init_rstr2d_0[] = { | |
30f4e087 BS |
412 | { 0x407808, 1, 0x04, 0x00000000 }, |
413 | {} | |
414 | }; | |
415 | ||
e3c71eb2 BS |
416 | const struct gf100_gr_init |
417 | gf100_gr_init_pd_0[] = { | |
30f4e087 BS |
418 | { 0x406024, 1, 0x04, 0x00000000 }, |
419 | {} | |
420 | }; | |
421 | ||
e3c71eb2 BS |
422 | const struct gf100_gr_init |
423 | gf100_gr_init_ds_0[] = { | |
30f4e087 BS |
424 | { 0x405844, 1, 0x04, 0x00ffffff }, |
425 | { 0x405850, 1, 0x04, 0x00000000 }, | |
426 | { 0x405908, 1, 0x04, 0x00000000 }, | |
427 | {} | |
428 | }; | |
429 | ||
e3c71eb2 BS |
430 | const struct gf100_gr_init |
431 | gf100_gr_init_scc_0[] = { | |
30f4e087 BS |
432 | { 0x40803c, 1, 0x04, 0x00000000 }, |
433 | {} | |
434 | }; | |
435 | ||
e3c71eb2 BS |
436 | const struct gf100_gr_init |
437 | gf100_gr_init_prop_0[] = { | |
30f4e087 | 438 | { 0x4184a0, 1, 0x04, 0x00000000 }, |
97af71fa BS |
439 | {} |
440 | }; | |
441 | ||
e3c71eb2 BS |
442 | const struct gf100_gr_init |
443 | gf100_gr_init_gpc_unk_0[] = { | |
30f4e087 BS |
444 | { 0x418604, 1, 0x04, 0x00000000 }, |
445 | { 0x418680, 1, 0x04, 0x00000000 }, | |
446 | { 0x418714, 1, 0x04, 0x80000000 }, | |
447 | { 0x418384, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
448 | {} |
449 | }; | |
450 | ||
e3c71eb2 BS |
451 | const struct gf100_gr_init |
452 | gf100_gr_init_setup_0[] = { | |
30f4e087 | 453 | { 0x418814, 3, 0x04, 0x00000000 }, |
97af71fa BS |
454 | {} |
455 | }; | |
456 | ||
e3c71eb2 BS |
457 | const struct gf100_gr_init |
458 | gf100_gr_init_crstr_0[] = { | |
30f4e087 | 459 | { 0x418b04, 1, 0x04, 0x00000000 }, |
97af71fa BS |
460 | {} |
461 | }; | |
462 | ||
e3c71eb2 BS |
463 | const struct gf100_gr_init |
464 | gf100_gr_init_setup_1[] = { | |
30f4e087 BS |
465 | { 0x4188c8, 1, 0x04, 0x80000000 }, |
466 | { 0x4188cc, 1, 0x04, 0x00000000 }, | |
467 | { 0x4188d0, 1, 0x04, 0x00010000 }, | |
468 | { 0x4188d4, 1, 0x04, 0x00000001 }, | |
97af71fa BS |
469 | {} |
470 | }; | |
471 | ||
e3c71eb2 BS |
472 | const struct gf100_gr_init |
473 | gf100_gr_init_zcull_0[] = { | |
30f4e087 BS |
474 | { 0x418910, 1, 0x04, 0x00010001 }, |
475 | { 0x418914, 1, 0x04, 0x00000301 }, | |
476 | { 0x418918, 1, 0x04, 0x00800000 }, | |
477 | { 0x418980, 1, 0x04, 0x77777770 }, | |
478 | { 0x418984, 3, 0x04, 0x77777777 }, | |
97af71fa BS |
479 | {} |
480 | }; | |
481 | ||
e3c71eb2 BS |
482 | const struct gf100_gr_init |
483 | gf100_gr_init_gpm_0[] = { | |
30f4e087 BS |
484 | { 0x418c04, 1, 0x04, 0x00000000 }, |
485 | { 0x418c88, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
486 | {} |
487 | }; | |
488 | ||
e3c71eb2 BS |
489 | const struct gf100_gr_init |
490 | gf100_gr_init_gpc_unk_1[] = { | |
30f4e087 BS |
491 | { 0x418d00, 1, 0x04, 0x00000000 }, |
492 | { 0x418f08, 1, 0x04, 0x00000000 }, | |
493 | { 0x418e00, 1, 0x04, 0x00000050 }, | |
494 | { 0x418e08, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
495 | {} |
496 | }; | |
497 | ||
e3c71eb2 BS |
498 | const struct gf100_gr_init |
499 | gf100_gr_init_gcc_0[] = { | |
30f4e087 BS |
500 | { 0x41900c, 1, 0x04, 0x00000000 }, |
501 | { 0x419018, 1, 0x04, 0x00000000 }, | |
502 | {} | |
503 | }; | |
504 | ||
e3c71eb2 BS |
505 | const struct gf100_gr_init |
506 | gf100_gr_init_tpccs_0[] = { | |
30f4e087 BS |
507 | { 0x419d08, 2, 0x04, 0x00000000 }, |
508 | { 0x419d10, 1, 0x04, 0x00000014 }, | |
7e194533 BS |
509 | {} |
510 | }; | |
511 | ||
e3c71eb2 BS |
512 | const struct gf100_gr_init |
513 | gf100_gr_init_tex_0[] = { | |
30f4e087 BS |
514 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
515 | { 0x419ab8, 1, 0x04, 0x000000e7 }, | |
516 | { 0x419abc, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
517 | {} |
518 | }; | |
519 | ||
e3c71eb2 BS |
520 | const struct gf100_gr_init |
521 | gf100_gr_init_pe_0[] = { | |
30f4e087 BS |
522 | { 0x41980c, 3, 0x04, 0x00000000 }, |
523 | { 0x419844, 1, 0x04, 0x00000000 }, | |
524 | { 0x41984c, 1, 0x04, 0x00005bc5 }, | |
525 | { 0x419850, 4, 0x04, 0x00000000 }, | |
7e194533 BS |
526 | {} |
527 | }; | |
528 | ||
e3c71eb2 BS |
529 | const struct gf100_gr_init |
530 | gf100_gr_init_l1c_0[] = { | |
30f4e087 BS |
531 | { 0x419c98, 1, 0x04, 0x00000000 }, |
532 | { 0x419ca8, 1, 0x04, 0x80000000 }, | |
533 | { 0x419cb4, 1, 0x04, 0x00000000 }, | |
534 | { 0x419cb8, 1, 0x04, 0x00008bf4 }, | |
535 | { 0x419cbc, 1, 0x04, 0x28137606 }, | |
536 | { 0x419cc0, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
537 | {} |
538 | }; | |
539 | ||
e3c71eb2 BS |
540 | const struct gf100_gr_init |
541 | gf100_gr_init_wwdx_0[] = { | |
30f4e087 BS |
542 | { 0x419bd4, 1, 0x04, 0x00800000 }, |
543 | { 0x419bdc, 1, 0x04, 0x00000000 }, | |
7e194533 BS |
544 | {} |
545 | }; | |
546 | ||
e3c71eb2 BS |
547 | const struct gf100_gr_init |
548 | gf100_gr_init_tpccs_1[] = { | |
30f4e087 | 549 | { 0x419d2c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
550 | {} |
551 | }; | |
552 | ||
e3c71eb2 BS |
553 | const struct gf100_gr_init |
554 | gf100_gr_init_mpc_0[] = { | |
30f4e087 | 555 | { 0x419c0c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
556 | {} |
557 | }; | |
558 | ||
e3c71eb2 BS |
559 | static const struct gf100_gr_init |
560 | gf100_gr_init_sm_0[] = { | |
30f4e087 BS |
561 | { 0x419e00, 1, 0x04, 0x00000000 }, |
562 | { 0x419ea0, 1, 0x04, 0x00000000 }, | |
563 | { 0x419ea4, 1, 0x04, 0x00000100 }, | |
564 | { 0x419ea8, 1, 0x04, 0x00001100 }, | |
565 | { 0x419eac, 1, 0x04, 0x11100702 }, | |
566 | { 0x419eb0, 1, 0x04, 0x00000003 }, | |
567 | { 0x419eb4, 4, 0x04, 0x00000000 }, | |
568 | { 0x419ec8, 1, 0x04, 0x06060618 }, | |
569 | { 0x419ed0, 1, 0x04, 0x0eff0e38 }, | |
570 | { 0x419ed4, 1, 0x04, 0x011104f1 }, | |
571 | { 0x419edc, 1, 0x04, 0x00000000 }, | |
572 | { 0x419f00, 1, 0x04, 0x00000000 }, | |
573 | { 0x419f2c, 1, 0x04, 0x00000000 }, | |
574 | {} | |
575 | }; | |
576 | ||
e3c71eb2 BS |
577 | const struct gf100_gr_init |
578 | gf100_gr_init_be_0[] = { | |
30f4e087 BS |
579 | { 0x40880c, 1, 0x04, 0x00000000 }, |
580 | { 0x408910, 9, 0x04, 0x00000000 }, | |
581 | { 0x408950, 1, 0x04, 0x00000000 }, | |
582 | { 0x408954, 1, 0x04, 0x0000ffff }, | |
583 | { 0x408984, 1, 0x04, 0x00000000 }, | |
584 | { 0x408988, 1, 0x04, 0x08040201 }, | |
585 | { 0x40898c, 1, 0x04, 0x80402010 }, | |
586 | {} | |
587 | }; | |
588 | ||
e3c71eb2 BS |
589 | const struct gf100_gr_init |
590 | gf100_gr_init_fe_1[] = { | |
c33b1e8c BS |
591 | { 0x4040f0, 1, 0x04, 0x00000000 }, |
592 | {} | |
593 | }; | |
594 | ||
e3c71eb2 BS |
595 | const struct gf100_gr_init |
596 | gf100_gr_init_pe_1[] = { | |
c33b1e8c BS |
597 | { 0x419880, 1, 0x04, 0x00000002 }, |
598 | {} | |
599 | }; | |
600 | ||
e3c71eb2 BS |
601 | static const struct gf100_gr_pack |
602 | gf100_gr_pack_mmio[] = { | |
603 | { gf100_gr_init_main_0 }, | |
604 | { gf100_gr_init_fe_0 }, | |
605 | { gf100_gr_init_pri_0 }, | |
606 | { gf100_gr_init_rstr2d_0 }, | |
607 | { gf100_gr_init_pd_0 }, | |
608 | { gf100_gr_init_ds_0 }, | |
609 | { gf100_gr_init_scc_0 }, | |
610 | { gf100_gr_init_prop_0 }, | |
611 | { gf100_gr_init_gpc_unk_0 }, | |
612 | { gf100_gr_init_setup_0 }, | |
613 | { gf100_gr_init_crstr_0 }, | |
614 | { gf100_gr_init_setup_1 }, | |
615 | { gf100_gr_init_zcull_0 }, | |
616 | { gf100_gr_init_gpm_0 }, | |
617 | { gf100_gr_init_gpc_unk_1 }, | |
618 | { gf100_gr_init_gcc_0 }, | |
619 | { gf100_gr_init_tpccs_0 }, | |
620 | { gf100_gr_init_tex_0 }, | |
621 | { gf100_gr_init_pe_0 }, | |
622 | { gf100_gr_init_l1c_0 }, | |
623 | { gf100_gr_init_wwdx_0 }, | |
624 | { gf100_gr_init_tpccs_1 }, | |
625 | { gf100_gr_init_mpc_0 }, | |
626 | { gf100_gr_init_sm_0 }, | |
627 | { gf100_gr_init_be_0 }, | |
628 | { gf100_gr_init_fe_1 }, | |
629 | { gf100_gr_init_pe_1 }, | |
26410c67 ML |
630 | {} |
631 | }; | |
632 | ||
c33b1e8c BS |
633 | /******************************************************************************* |
634 | * PGRAPH engine/subdev functions | |
635 | ******************************************************************************/ | |
636 | ||
ac9738bb | 637 | void |
e3c71eb2 | 638 | gf100_gr_zbc_init(struct gf100_gr_priv *priv) |
ac9738bb BS |
639 | { |
640 | const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
641 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
642 | const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
643 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; | |
644 | const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
645 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
646 | const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
647 | 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; | |
e3c71eb2 | 648 | struct nvkm_ltc *ltc = nvkm_ltc(priv); |
ac9738bb BS |
649 | int index; |
650 | ||
651 | if (!priv->zbc_color[0].format) { | |
e3c71eb2 BS |
652 | gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); |
653 | gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]); | |
654 | gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); | |
655 | gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); | |
656 | gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); | |
657 | gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); | |
ac9738bb BS |
658 | } |
659 | ||
660 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) | |
e3c71eb2 | 661 | gf100_gr_zbc_clear_color(priv, index); |
ac9738bb | 662 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
e3c71eb2 | 663 | gf100_gr_zbc_clear_depth(priv, index); |
ac9738bb BS |
664 | } |
665 | ||
4a8cf451 AC |
666 | /** |
667 | * Wait until GR goes idle. GR is considered idle if it is disabled by the | |
668 | * MC (0x200) register, or GR is not busy and a context switch is not in | |
669 | * progress. | |
670 | */ | |
671 | int | |
672 | gf100_gr_wait_idle(struct gf100_gr_priv *priv) | |
673 | { | |
674 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); | |
675 | bool gr_enabled, ctxsw_active, gr_busy; | |
676 | ||
677 | do { | |
678 | /* | |
679 | * required to make sure FIFO_ENGINE_STATUS (0x2640) is | |
680 | * up-to-date | |
681 | */ | |
682 | nv_rd32(priv, 0x400700); | |
683 | ||
684 | gr_enabled = nv_rd32(priv, 0x200) & 0x1000; | |
685 | ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000; | |
686 | gr_busy = nv_rd32(priv, 0x40060c) & 0x1; | |
687 | ||
688 | if (!gr_enabled || (!gr_busy && !ctxsw_active)) | |
689 | return 0; | |
690 | } while (time_before(jiffies, end_jiffies)); | |
691 | ||
692 | nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", | |
693 | gr_enabled, ctxsw_active, gr_busy); | |
694 | return -EAGAIN; | |
695 | } | |
696 | ||
30f4e087 | 697 | void |
e3c71eb2 | 698 | gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) |
4b223eef | 699 | { |
e3c71eb2 BS |
700 | const struct gf100_gr_pack *pack; |
701 | const struct gf100_gr_init *init; | |
c33b1e8c BS |
702 | |
703 | pack_for_each_init(init, pack, p) { | |
704 | u32 next = init->addr + init->count * init->pitch; | |
705 | u32 addr = init->addr; | |
706 | while (addr < next) { | |
30f4e087 BS |
707 | nv_wr32(priv, addr, init->data); |
708 | addr += init->pitch; | |
709 | } | |
710 | } | |
ebb945a9 BS |
711 | } |
712 | ||
713 | void | |
e3c71eb2 | 714 | gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) |
ebb945a9 | 715 | { |
e3c71eb2 BS |
716 | const struct gf100_gr_pack *pack; |
717 | const struct gf100_gr_init *init; | |
c33b1e8c | 718 | u32 data = 0; |
30f4e087 BS |
719 | |
720 | nv_wr32(priv, 0x400208, 0x80000000); | |
c33b1e8c BS |
721 | |
722 | pack_for_each_init(init, pack, p) { | |
723 | u32 next = init->addr + init->count * init->pitch; | |
724 | u32 addr = init->addr; | |
725 | ||
726 | if ((pack == p && init == p->init) || data != init->data) { | |
30f4e087 BS |
727 | nv_wr32(priv, 0x400204, init->data); |
728 | data = init->data; | |
729 | } | |
ebb945a9 | 730 | |
c33b1e8c | 731 | while (addr < next) { |
30f4e087 | 732 | nv_wr32(priv, 0x400200, addr); |
4a8cf451 AC |
733 | /** |
734 | * Wait for GR to go idle after submitting a | |
735 | * GO_IDLE bundle | |
736 | */ | |
737 | if ((addr & 0xffff) == 0xe100) | |
738 | gf100_gr_wait_idle(priv); | |
19bf09ce | 739 | nv_wait(priv, 0x400700, 0x00000004, 0x00000000); |
30f4e087 | 740 | addr += init->pitch; |
30f4e087 BS |
741 | } |
742 | } | |
c33b1e8c | 743 | |
30f4e087 BS |
744 | nv_wr32(priv, 0x400208, 0x00000000); |
745 | } | |
746 | ||
747 | void | |
e3c71eb2 | 748 | gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) |
30f4e087 | 749 | { |
e3c71eb2 BS |
750 | const struct gf100_gr_pack *pack; |
751 | const struct gf100_gr_init *init; | |
c33b1e8c | 752 | u32 data = 0; |
30f4e087 | 753 | |
c33b1e8c BS |
754 | pack_for_each_init(init, pack, p) { |
755 | u32 ctrl = 0x80000000 | pack->type; | |
756 | u32 next = init->addr + init->count * init->pitch; | |
757 | u32 addr = init->addr; | |
758 | ||
759 | if ((pack == p && init == p->init) || data != init->data) { | |
760 | nv_wr32(priv, 0x40448c, init->data); | |
761 | data = init->data; | |
762 | } | |
763 | ||
764 | while (addr < next) { | |
765 | nv_wr32(priv, 0x404488, ctrl | (addr << 14)); | |
766 | addr += init->pitch; | |
30f4e087 BS |
767 | } |
768 | } | |
769 | } | |
770 | ||
771 | u64 | |
e3c71eb2 | 772 | gf100_gr_units(struct nvkm_gr *gr) |
30f4e087 | 773 | { |
e3c71eb2 | 774 | struct gf100_gr_priv *priv = (void *)gr; |
30f4e087 BS |
775 | u64 cfg; |
776 | ||
777 | cfg = (u32)priv->gpc_nr; | |
778 | cfg |= (u32)priv->tpc_total << 8; | |
779 | cfg |= (u64)priv->rop_nr << 32; | |
780 | ||
781 | return cfg; | |
ebb945a9 BS |
782 | } |
783 | ||
e3c71eb2 | 784 | static const struct nvkm_enum gk104_sked_error[] = { |
30f4e087 BS |
785 | { 7, "CONSTANT_BUFFER_SIZE" }, |
786 | { 9, "LOCAL_MEMORY_SIZE_POS" }, | |
787 | { 10, "LOCAL_MEMORY_SIZE_NEG" }, | |
788 | { 11, "WARP_CSTACK_SIZE" }, | |
789 | { 12, "TOTAL_TEMP_SIZE" }, | |
790 | { 13, "REGISTER_COUNT" }, | |
791 | { 18, "TOTAL_THREADS" }, | |
792 | { 20, "PROGRAM_OFFSET" }, | |
793 | { 21, "SHARED_MEMORY_SIZE" }, | |
794 | { 25, "SHARED_CONFIG_TOO_SMALL" }, | |
795 | { 26, "TOTAL_REGISTER_COUNT" }, | |
796 | {} | |
797 | }; | |
798 | ||
e3c71eb2 | 799 | static const struct nvkm_enum gf100_gpc_rop_error[] = { |
30f4e087 BS |
800 | { 1, "RT_PITCH_OVERRUN" }, |
801 | { 4, "RT_WIDTH_OVERRUN" }, | |
802 | { 5, "RT_HEIGHT_OVERRUN" }, | |
803 | { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, | |
804 | { 8, "RT_STORAGE_TYPE_MISMATCH" }, | |
805 | { 10, "RT_LINEAR_MISMATCH" }, | |
806 | {} | |
807 | }; | |
808 | ||
ebb945a9 | 809 | static void |
e3c71eb2 | 810 | gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) |
ebb945a9 | 811 | { |
30f4e087 BS |
812 | u32 trap[4]; |
813 | int i; | |
ebb945a9 | 814 | |
30f4e087 BS |
815 | trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); |
816 | trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); | |
817 | trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); | |
818 | trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); | |
ebb945a9 | 819 | |
30f4e087 BS |
820 | nv_error(priv, "GPC%d/PROP trap:", gpc); |
821 | for (i = 0; i <= 29; ++i) { | |
822 | if (!(trap[0] & (1 << i))) | |
823 | continue; | |
824 | pr_cont(" "); | |
e3c71eb2 | 825 | nvkm_enum_print(gf100_gpc_rop_error, i); |
30f4e087 BS |
826 | } |
827 | pr_cont("\n"); | |
828 | ||
829 | nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", | |
830 | trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, | |
831 | trap[3] & 0xff); | |
832 | nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); | |
ebb945a9 BS |
833 | } |
834 | ||
e3c71eb2 | 835 | static const struct nvkm_enum gf100_mp_warp_error[] = { |
fec43a72 BS |
836 | { 0x00, "NO_ERROR" }, |
837 | { 0x01, "STACK_MISMATCH" }, | |
838 | { 0x05, "MISALIGNED_PC" }, | |
839 | { 0x08, "MISALIGNED_GPR" }, | |
840 | { 0x09, "INVALID_OPCODE" }, | |
841 | { 0x0d, "GPR_OUT_OF_BOUNDS" }, | |
842 | { 0x0e, "MEM_OUT_OF_BOUNDS" }, | |
843 | { 0x0f, "UNALIGNED_MEM_ACCESS" }, | |
844 | { 0x11, "INVALID_PARAM" }, | |
845 | {} | |
846 | }; | |
847 | ||
e3c71eb2 | 848 | static const struct nvkm_bitfield gf100_mp_global_error[] = { |
fec43a72 BS |
849 | { 0x00000004, "MULTIPLE_WARP_ERRORS" }, |
850 | { 0x00000008, "OUT_OF_STACK_SPACE" }, | |
851 | {} | |
852 | }; | |
853 | ||
854 | static void | |
e3c71eb2 | 855 | gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) |
fec43a72 BS |
856 | { |
857 | u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); | |
858 | u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); | |
859 | ||
860 | nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); | |
e3c71eb2 | 861 | nvkm_bitfield_print(gf100_mp_global_error, gerr); |
fec43a72 BS |
862 | if (werr) { |
863 | pr_cont(" "); | |
e3c71eb2 | 864 | nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); |
fec43a72 BS |
865 | } |
866 | pr_cont("\n"); | |
867 | ||
868 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); | |
869 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); | |
870 | } | |
871 | ||
f73221e4 | 872 | static void |
e3c71eb2 | 873 | gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc) |
f73221e4 BS |
874 | { |
875 | u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); | |
876 | ||
877 | if (stat & 0x00000001) { | |
878 | u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); | |
879 | nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); | |
880 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); | |
f73221e4 BS |
881 | stat &= ~0x00000001; |
882 | } | |
883 | ||
884 | if (stat & 0x00000002) { | |
e3c71eb2 | 885 | gf100_gr_trap_mp(priv, gpc, tpc); |
f73221e4 BS |
886 | stat &= ~0x00000002; |
887 | } | |
888 | ||
889 | if (stat & 0x00000004) { | |
890 | u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); | |
891 | nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); | |
892 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); | |
f73221e4 BS |
893 | stat &= ~0x00000004; |
894 | } | |
895 | ||
896 | if (stat & 0x00000008) { | |
897 | u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); | |
898 | nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); | |
899 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); | |
f73221e4 BS |
900 | stat &= ~0x00000008; |
901 | } | |
902 | ||
903 | if (stat) { | |
904 | nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); | |
f73221e4 BS |
905 | } |
906 | } | |
907 | ||
908 | static void | |
e3c71eb2 | 909 | gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc) |
f73221e4 BS |
910 | { |
911 | u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); | |
912 | int tpc; | |
913 | ||
914 | if (stat & 0x00000001) { | |
e3c71eb2 | 915 | gf100_gr_trap_gpc_rop(priv, gpc); |
f73221e4 BS |
916 | stat &= ~0x00000001; |
917 | } | |
918 | ||
919 | if (stat & 0x00000002) { | |
920 | u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); | |
921 | nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); | |
922 | nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
f73221e4 BS |
923 | stat &= ~0x00000002; |
924 | } | |
925 | ||
926 | if (stat & 0x00000004) { | |
927 | u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); | |
928 | nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); | |
929 | nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
f73221e4 BS |
930 | stat &= ~0x00000004; |
931 | } | |
932 | ||
933 | if (stat & 0x00000008) { | |
934 | u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); | |
935 | nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); | |
936 | nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
f73221e4 BS |
937 | stat &= ~0x00000009; |
938 | } | |
939 | ||
940 | for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { | |
941 | u32 mask = 0x00010000 << tpc; | |
942 | if (stat & mask) { | |
e3c71eb2 | 943 | gf100_gr_trap_tpc(priv, gpc, tpc); |
f73221e4 BS |
944 | nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); |
945 | stat &= ~mask; | |
946 | } | |
947 | } | |
948 | ||
949 | if (stat) { | |
950 | nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); | |
f73221e4 BS |
951 | } |
952 | } | |
953 | ||
954 | static void | |
e3c71eb2 | 955 | gf100_gr_trap_intr(struct gf100_gr_priv *priv) |
f73221e4 BS |
956 | { |
957 | u32 trap = nv_rd32(priv, 0x400108); | |
30f4e087 | 958 | int rop, gpc, i; |
f73221e4 BS |
959 | |
960 | if (trap & 0x00000001) { | |
961 | u32 stat = nv_rd32(priv, 0x404000); | |
962 | nv_error(priv, "DISPATCH 0x%08x\n", stat); | |
963 | nv_wr32(priv, 0x404000, 0xc0000000); | |
964 | nv_wr32(priv, 0x400108, 0x00000001); | |
965 | trap &= ~0x00000001; | |
966 | } | |
967 | ||
968 | if (trap & 0x00000002) { | |
969 | u32 stat = nv_rd32(priv, 0x404600); | |
970 | nv_error(priv, "M2MF 0x%08x\n", stat); | |
971 | nv_wr32(priv, 0x404600, 0xc0000000); | |
972 | nv_wr32(priv, 0x400108, 0x00000002); | |
973 | trap &= ~0x00000002; | |
974 | } | |
975 | ||
976 | if (trap & 0x00000008) { | |
977 | u32 stat = nv_rd32(priv, 0x408030); | |
978 | nv_error(priv, "CCACHE 0x%08x\n", stat); | |
979 | nv_wr32(priv, 0x408030, 0xc0000000); | |
980 | nv_wr32(priv, 0x400108, 0x00000008); | |
981 | trap &= ~0x00000008; | |
982 | } | |
983 | ||
984 | if (trap & 0x00000010) { | |
985 | u32 stat = nv_rd32(priv, 0x405840); | |
986 | nv_error(priv, "SHADER 0x%08x\n", stat); | |
987 | nv_wr32(priv, 0x405840, 0xc0000000); | |
988 | nv_wr32(priv, 0x400108, 0x00000010); | |
989 | trap &= ~0x00000010; | |
990 | } | |
991 | ||
992 | if (trap & 0x00000040) { | |
993 | u32 stat = nv_rd32(priv, 0x40601c); | |
994 | nv_error(priv, "UNK6 0x%08x\n", stat); | |
995 | nv_wr32(priv, 0x40601c, 0xc0000000); | |
996 | nv_wr32(priv, 0x400108, 0x00000040); | |
997 | trap &= ~0x00000040; | |
998 | } | |
999 | ||
1000 | if (trap & 0x00000080) { | |
1001 | u32 stat = nv_rd32(priv, 0x404490); | |
1002 | nv_error(priv, "MACRO 0x%08x\n", stat); | |
1003 | nv_wr32(priv, 0x404490, 0xc0000000); | |
1004 | nv_wr32(priv, 0x400108, 0x00000080); | |
1005 | trap &= ~0x00000080; | |
1006 | } | |
1007 | ||
30f4e087 BS |
1008 | if (trap & 0x00000100) { |
1009 | u32 stat = nv_rd32(priv, 0x407020); | |
1010 | ||
1011 | nv_error(priv, "SKED:"); | |
1012 | for (i = 0; i <= 29; ++i) { | |
1013 | if (!(stat & (1 << i))) | |
1014 | continue; | |
1015 | pr_cont(" "); | |
e3c71eb2 | 1016 | nvkm_enum_print(gk104_sked_error, i); |
30f4e087 BS |
1017 | } |
1018 | pr_cont("\n"); | |
1019 | ||
1020 | if (stat & 0x3fffffff) | |
1021 | nv_wr32(priv, 0x407020, 0x40000000); | |
1022 | nv_wr32(priv, 0x400108, 0x00000100); | |
1023 | trap &= ~0x00000100; | |
1024 | } | |
1025 | ||
f73221e4 BS |
1026 | if (trap & 0x01000000) { |
1027 | u32 stat = nv_rd32(priv, 0x400118); | |
1028 | for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { | |
1029 | u32 mask = 0x00000001 << gpc; | |
1030 | if (stat & mask) { | |
e3c71eb2 | 1031 | gf100_gr_trap_gpc(priv, gpc); |
f73221e4 BS |
1032 | nv_wr32(priv, 0x400118, mask); |
1033 | stat &= ~mask; | |
1034 | } | |
1035 | } | |
1036 | nv_wr32(priv, 0x400108, 0x01000000); | |
1037 | trap &= ~0x01000000; | |
1038 | } | |
1039 | ||
1040 | if (trap & 0x02000000) { | |
1041 | for (rop = 0; rop < priv->rop_nr; rop++) { | |
1042 | u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); | |
1043 | u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); | |
1044 | nv_error(priv, "ROP%d 0x%08x 0x%08x\n", | |
1045 | rop, statz, statc); | |
1046 | nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); | |
1047 | nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); | |
1048 | } | |
1049 | nv_wr32(priv, 0x400108, 0x02000000); | |
1050 | trap &= ~0x02000000; | |
1051 | } | |
1052 | ||
1053 | if (trap) { | |
1054 | nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); | |
1055 | nv_wr32(priv, 0x400108, trap); | |
1056 | } | |
1057 | } | |
1058 | ||
30f4e087 | 1059 | static void |
e3c71eb2 | 1060 | gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base) |
30f4e087 BS |
1061 | { |
1062 | nv_error(priv, "%06x - done 0x%08x\n", base, | |
1063 | nv_rd32(priv, base + 0x400)); | |
1064 | nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
1065 | nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), | |
1066 | nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); | |
1067 | nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, | |
1068 | nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), | |
1069 | nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); | |
1070 | } | |
1071 | ||
1072 | void | |
e3c71eb2 | 1073 | gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv) |
30f4e087 BS |
1074 | { |
1075 | u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; | |
1076 | u32 gpc; | |
1077 | ||
e3c71eb2 | 1078 | gf100_gr_ctxctl_debug_unit(priv, 0x409000); |
30f4e087 | 1079 | for (gpc = 0; gpc < gpcnr; gpc++) |
e3c71eb2 | 1080 | gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); |
30f4e087 BS |
1081 | } |
1082 | ||
1083 | static void | |
e3c71eb2 | 1084 | gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) |
30f4e087 | 1085 | { |
23f67841 | 1086 | u32 stat = nv_rd32(priv, 0x409c18); |
30f4e087 | 1087 | |
23f67841 BS |
1088 | if (stat & 0x00000001) { |
1089 | u32 code = nv_rd32(priv, 0x409814); | |
1090 | if (code == E_BAD_FWMTHD) { | |
1091 | u32 class = nv_rd32(priv, 0x409808); | |
1092 | u32 addr = nv_rd32(priv, 0x40980c); | |
1093 | u32 subc = (addr & 0x00070000) >> 16; | |
1094 | u32 mthd = (addr & 0x00003ffc); | |
1095 | u32 data = nv_rd32(priv, 0x409810); | |
1096 | ||
1097 | nv_error(priv, "FECS MTHD subc %d class 0x%04x " | |
1098 | "mthd 0x%04x data 0x%08x\n", | |
1099 | subc, class, mthd, data); | |
1100 | ||
1101 | nv_wr32(priv, 0x409c20, 0x00000001); | |
1102 | stat &= ~0x00000001; | |
1103 | } else { | |
1104 | nv_error(priv, "FECS ucode error %d\n", code); | |
1105 | } | |
1106 | } | |
30f4e087 | 1107 | |
23f67841 BS |
1108 | if (stat & 0x00080000) { |
1109 | nv_error(priv, "FECS watchdog timeout\n"); | |
e3c71eb2 | 1110 | gf100_gr_ctxctl_debug(priv); |
23f67841 BS |
1111 | nv_wr32(priv, 0x409c20, 0x00080000); |
1112 | stat &= ~0x00080000; | |
1113 | } | |
1114 | ||
1115 | if (stat) { | |
1116 | nv_error(priv, "FECS 0x%08x\n", stat); | |
e3c71eb2 | 1117 | gf100_gr_ctxctl_debug(priv); |
23f67841 BS |
1118 | nv_wr32(priv, 0x409c20, stat); |
1119 | } | |
30f4e087 BS |
1120 | } |
1121 | ||
ebb945a9 | 1122 | static void |
e3c71eb2 | 1123 | gf100_gr_intr(struct nvkm_subdev *subdev) |
ebb945a9 | 1124 | { |
e3c71eb2 BS |
1125 | struct nvkm_fifo *pfifo = nvkm_fifo(subdev); |
1126 | struct nvkm_engine *engine = nv_engine(subdev); | |
1127 | struct nvkm_object *engctx; | |
1128 | struct nvkm_handle *handle; | |
1129 | struct gf100_gr_priv *priv = (void *)subdev; | |
72a14827 | 1130 | u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; |
ebb945a9 BS |
1131 | u32 stat = nv_rd32(priv, 0x400100); |
1132 | u32 addr = nv_rd32(priv, 0x400704); | |
1133 | u32 mthd = (addr & 0x00003ffc); | |
1134 | u32 subc = (addr & 0x00070000) >> 16; | |
1135 | u32 data = nv_rd32(priv, 0x400708); | |
1136 | u32 code = nv_rd32(priv, 0x400110); | |
91c772ec | 1137 | u32 class; |
72a14827 BS |
1138 | int chid; |
1139 | ||
91c772ec BS |
1140 | if (nv_device(priv)->card_type < NV_E0 || subc < 4) |
1141 | class = nv_rd32(priv, 0x404200 + (subc * 4)); | |
1142 | else | |
1143 | class = 0x0000; | |
1144 | ||
e3c71eb2 | 1145 | engctx = nvkm_engctx_get(engine, inst); |
72a14827 | 1146 | chid = pfifo->chid(pfifo, engctx); |
ebb945a9 | 1147 | |
c6a7b026 LP |
1148 | if (stat & 0x00000001) { |
1149 | /* | |
1150 | * notifier interrupt, only needed for cyclestats | |
1151 | * can be safely ignored | |
1152 | */ | |
1153 | nv_wr32(priv, 0x400100, 0x00000001); | |
1154 | stat &= ~0x00000001; | |
1155 | } | |
1156 | ||
ebb945a9 | 1157 | if (stat & 0x00000010) { |
e3c71eb2 | 1158 | handle = nvkm_handle_get_class(engctx, class); |
ebb945a9 | 1159 | if (!handle || nv_call(handle->object, mthd, data)) { |
93260d3c MS |
1160 | nv_error(priv, |
1161 | "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", | |
e3c71eb2 | 1162 | chid, inst << 12, nvkm_client_name(engctx), |
93260d3c | 1163 | subc, class, mthd, data); |
ebb945a9 | 1164 | } |
e3c71eb2 | 1165 | nvkm_handle_put(handle); |
ebb945a9 BS |
1166 | nv_wr32(priv, 0x400100, 0x00000010); |
1167 | stat &= ~0x00000010; | |
1168 | } | |
1169 | ||
1170 | if (stat & 0x00000020) { | |
93260d3c MS |
1171 | nv_error(priv, |
1172 | "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", | |
e3c71eb2 | 1173 | chid, inst << 12, nvkm_client_name(engctx), subc, |
93260d3c | 1174 | class, mthd, data); |
ebb945a9 BS |
1175 | nv_wr32(priv, 0x400100, 0x00000020); |
1176 | stat &= ~0x00000020; | |
1177 | } | |
1178 | ||
1179 | if (stat & 0x00100000) { | |
1180 | nv_error(priv, "DATA_ERROR ["); | |
e3c71eb2 | 1181 | nvkm_enum_print(nv50_data_error_names, code); |
93260d3c | 1182 | pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", |
e3c71eb2 | 1183 | chid, inst << 12, nvkm_client_name(engctx), subc, |
93260d3c | 1184 | class, mthd, data); |
ebb945a9 BS |
1185 | nv_wr32(priv, 0x400100, 0x00100000); |
1186 | stat &= ~0x00100000; | |
1187 | } | |
1188 | ||
1189 | if (stat & 0x00200000) { | |
93260d3c | 1190 | nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, |
e3c71eb2 BS |
1191 | nvkm_client_name(engctx)); |
1192 | gf100_gr_trap_intr(priv); | |
ebb945a9 BS |
1193 | nv_wr32(priv, 0x400100, 0x00200000); |
1194 | stat &= ~0x00200000; | |
1195 | } | |
1196 | ||
1197 | if (stat & 0x00080000) { | |
e3c71eb2 | 1198 | gf100_gr_ctxctl_isr(priv); |
ebb945a9 BS |
1199 | nv_wr32(priv, 0x400100, 0x00080000); |
1200 | stat &= ~0x00080000; | |
1201 | } | |
1202 | ||
1203 | if (stat) { | |
1204 | nv_error(priv, "unknown stat 0x%08x\n", stat); | |
1205 | nv_wr32(priv, 0x400100, stat); | |
1206 | } | |
1207 | ||
1208 | nv_wr32(priv, 0x400500, 0x00010001); | |
e3c71eb2 | 1209 | nvkm_engctx_put(engctx); |
ebb945a9 BS |
1210 | } |
1211 | ||
30f4e087 | 1212 | void |
e3c71eb2 BS |
1213 | gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base, |
1214 | struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) | |
ebb945a9 | 1215 | { |
30f4e087 | 1216 | int i; |
ebb945a9 | 1217 | |
30f4e087 BS |
1218 | nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); |
1219 | for (i = 0; i < data->size / 4; i++) | |
1220 | nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); | |
ebb945a9 | 1221 | |
30f4e087 BS |
1222 | nv_wr32(priv, fuc_base + 0x0180, 0x01000000); |
1223 | for (i = 0; i < code->size / 4; i++) { | |
1224 | if ((i & 0x3f) == 0) | |
1225 | nv_wr32(priv, fuc_base + 0x0188, i >> 6); | |
1226 | nv_wr32(priv, fuc_base + 0x0184, code->data[i]); | |
1227 | } | |
370eec76 AC |
1228 | |
1229 | /* code must be padded to 0x40 words */ | |
1230 | for (; i & 0x3f; i++) | |
1231 | nv_wr32(priv, fuc_base + 0x0184, 0); | |
966a5b7d BS |
1232 | } |
1233 | ||
a32b2ffb | 1234 | static void |
e3c71eb2 BS |
1235 | gf100_gr_init_csdata(struct gf100_gr_priv *priv, |
1236 | const struct gf100_gr_pack *pack, | |
1237 | u32 falcon, u32 starstar, u32 base) | |
a32b2ffb | 1238 | { |
e3c71eb2 BS |
1239 | const struct gf100_gr_pack *iter; |
1240 | const struct gf100_gr_init *init; | |
c33b1e8c | 1241 | u32 addr = ~0, prev = ~0, xfer = 0; |
a32b2ffb BS |
1242 | u32 star, temp; |
1243 | ||
1244 | nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); | |
1245 | star = nv_rd32(priv, falcon + 0x01c4); | |
1246 | temp = nv_rd32(priv, falcon + 0x01c4); | |
1247 | if (temp > star) | |
1248 | star = temp; | |
1249 | nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); | |
1250 | ||
c33b1e8c BS |
1251 | pack_for_each_init(init, iter, pack) { |
1252 | u32 head = init->addr - base; | |
1253 | u32 tail = head + init->count * init->pitch; | |
1254 | while (head < tail) { | |
1255 | if (head != prev + 4 || xfer >= 32) { | |
1256 | if (xfer) { | |
1257 | u32 data = ((--xfer << 26) | addr); | |
1258 | nv_wr32(priv, falcon + 0x01c4, data); | |
1259 | star += 4; | |
1260 | } | |
1261 | addr = head; | |
1262 | xfer = 0; | |
a32b2ffb | 1263 | } |
c33b1e8c BS |
1264 | prev = head; |
1265 | xfer = xfer + 1; | |
1266 | head = head + init->pitch; | |
a32b2ffb | 1267 | } |
c33b1e8c | 1268 | } |
a32b2ffb | 1269 | |
c33b1e8c | 1270 | nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); |
a32b2ffb | 1271 | nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); |
c33b1e8c | 1272 | nv_wr32(priv, falcon + 0x01c4, star + 4); |
a32b2ffb BS |
1273 | } |
1274 | ||
30f4e087 | 1275 | int |
e3c71eb2 | 1276 | gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) |
966a5b7d | 1277 | { |
e3c71eb2 BS |
1278 | struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; |
1279 | struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; | |
30f4e087 | 1280 | int i; |
ebb945a9 | 1281 | |
30f4e087 BS |
1282 | if (priv->firmware) { |
1283 | /* load fuc microcode */ | |
e3c71eb2 BS |
1284 | nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); |
1285 | gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c, | |
1286 | &priv->fuc409d); | |
1287 | gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, | |
1288 | &priv->fuc41ad); | |
1289 | nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); | |
ebb945a9 | 1290 | |
30f4e087 BS |
1291 | /* start both of them running */ |
1292 | nv_wr32(priv, 0x409840, 0xffffffff); | |
1293 | nv_wr32(priv, 0x41a10c, 0x00000000); | |
1294 | nv_wr32(priv, 0x40910c, 0x00000000); | |
1295 | nv_wr32(priv, 0x41a100, 0x00000002); | |
1296 | nv_wr32(priv, 0x409100, 0x00000002); | |
1297 | if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) | |
1298 | nv_warn(priv, "0x409800 wait failed\n"); | |
ebb945a9 | 1299 | |
30f4e087 BS |
1300 | nv_wr32(priv, 0x409840, 0xffffffff); |
1301 | nv_wr32(priv, 0x409500, 0x7fffffff); | |
1302 | nv_wr32(priv, 0x409504, 0x00000021); | |
7e22e71e | 1303 | |
30f4e087 BS |
1304 | nv_wr32(priv, 0x409840, 0xffffffff); |
1305 | nv_wr32(priv, 0x409500, 0x00000000); | |
1306 | nv_wr32(priv, 0x409504, 0x00000010); | |
1307 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1308 | nv_error(priv, "fuc09 req 0x10 timeout\n"); | |
1309 | return -EBUSY; | |
1310 | } | |
1311 | priv->size = nv_rd32(priv, 0x409800); | |
0411de85 | 1312 | |
ebb945a9 BS |
1313 | nv_wr32(priv, 0x409840, 0xffffffff); |
1314 | nv_wr32(priv, 0x409500, 0x00000000); | |
1315 | nv_wr32(priv, 0x409504, 0x00000016); | |
1316 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1317 | nv_error(priv, "fuc09 req 0x16 timeout\n"); | |
ac1499d9 BS |
1318 | return -EBUSY; |
1319 | } | |
1320 | ||
ebb945a9 BS |
1321 | nv_wr32(priv, 0x409840, 0xffffffff); |
1322 | nv_wr32(priv, 0x409500, 0x00000000); | |
1323 | nv_wr32(priv, 0x409504, 0x00000025); | |
1324 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1325 | nv_error(priv, "fuc09 req 0x25 timeout\n"); | |
ac1499d9 BS |
1326 | return -EBUSY; |
1327 | } | |
1328 | ||
30f4e087 BS |
1329 | if (nv_device(priv)->chipset >= 0xe0) { |
1330 | nv_wr32(priv, 0x409800, 0x00000000); | |
1331 | nv_wr32(priv, 0x409500, 0x00000001); | |
1332 | nv_wr32(priv, 0x409504, 0x00000030); | |
1333 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1334 | nv_error(priv, "fuc09 req 0x30 timeout\n"); | |
1335 | return -EBUSY; | |
1336 | } | |
1337 | ||
1338 | nv_wr32(priv, 0x409810, 0xb00095c8); | |
1339 | nv_wr32(priv, 0x409800, 0x00000000); | |
1340 | nv_wr32(priv, 0x409500, 0x00000001); | |
1341 | nv_wr32(priv, 0x409504, 0x00000031); | |
1342 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1343 | nv_error(priv, "fuc09 req 0x31 timeout\n"); | |
1344 | return -EBUSY; | |
1345 | } | |
1346 | ||
1347 | nv_wr32(priv, 0x409810, 0x00080420); | |
1348 | nv_wr32(priv, 0x409800, 0x00000000); | |
1349 | nv_wr32(priv, 0x409500, 0x00000001); | |
1350 | nv_wr32(priv, 0x409504, 0x00000032); | |
1351 | if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { | |
1352 | nv_error(priv, "fuc09 req 0x32 timeout\n"); | |
1353 | return -EBUSY; | |
1354 | } | |
1355 | ||
1356 | nv_wr32(priv, 0x409614, 0x00000070); | |
1357 | nv_wr32(priv, 0x409614, 0x00000770); | |
1358 | nv_wr32(priv, 0x40802c, 0x00000001); | |
1359 | } | |
1360 | ||
ebb945a9 | 1361 | if (priv->data == NULL) { |
e3c71eb2 | 1362 | int ret = gf100_grctx_generate(priv); |
ebb945a9 BS |
1363 | if (ret) { |
1364 | nv_error(priv, "failed to construct context\n"); | |
1365 | return ret; | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | return 0; | |
96616b4c BS |
1370 | } else |
1371 | if (!oclass->fecs.ucode) { | |
1372 | return -ENOSYS; | |
0411de85 | 1373 | } |
966a5b7d | 1374 | |
ac1499d9 | 1375 | /* load HUB microcode */ |
e3c71eb2 | 1376 | nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); |
ebb945a9 | 1377 | nv_wr32(priv, 0x4091c0, 0x01000000); |
30f4e087 BS |
1378 | for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) |
1379 | nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); | |
ac1499d9 | 1380 | |
ebb945a9 | 1381 | nv_wr32(priv, 0x409180, 0x01000000); |
30f4e087 | 1382 | for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { |
ac1499d9 | 1383 | if ((i & 0x3f) == 0) |
ebb945a9 | 1384 | nv_wr32(priv, 0x409188, i >> 6); |
30f4e087 | 1385 | nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); |
ac1499d9 BS |
1386 | } |
1387 | ||
1388 | /* load GPC microcode */ | |
ebb945a9 | 1389 | nv_wr32(priv, 0x41a1c0, 0x01000000); |
30f4e087 BS |
1390 | for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) |
1391 | nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); | |
ac1499d9 | 1392 | |
ebb945a9 | 1393 | nv_wr32(priv, 0x41a180, 0x01000000); |
30f4e087 | 1394 | for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { |
ac1499d9 | 1395 | if ((i & 0x3f) == 0) |
ebb945a9 | 1396 | nv_wr32(priv, 0x41a188, i >> 6); |
30f4e087 | 1397 | nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); |
ac1499d9 | 1398 | } |
e3c71eb2 | 1399 | nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); |
966a5b7d | 1400 | |
c33b1e8c | 1401 | /* load register lists */ |
e3c71eb2 BS |
1402 | gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); |
1403 | gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); | |
1404 | gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); | |
1405 | gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); | |
a32b2ffb | 1406 | |
ac1499d9 | 1407 | /* start HUB ucode running, it'll init the GPCs */ |
ebb945a9 BS |
1408 | nv_wr32(priv, 0x40910c, 0x00000000); |
1409 | nv_wr32(priv, 0x409100, 0x00000002); | |
1410 | if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { | |
1411 | nv_error(priv, "HUB_INIT timed out\n"); | |
e3c71eb2 | 1412 | gf100_gr_ctxctl_debug(priv); |
966a5b7d BS |
1413 | return -EBUSY; |
1414 | } | |
966a5b7d | 1415 | |
ebb945a9 | 1416 | priv->size = nv_rd32(priv, 0x409804); |
ac1499d9 | 1417 | if (priv->data == NULL) { |
e3c71eb2 | 1418 | int ret = gf100_grctx_generate(priv); |
ac1499d9 | 1419 | if (ret) { |
ebb945a9 | 1420 | nv_error(priv, "failed to construct context\n"); |
ac1499d9 BS |
1421 | return ret; |
1422 | } | |
966a5b7d BS |
1423 | } |
1424 | ||
1425 | return 0; | |
4b223eef BS |
1426 | } |
1427 | ||
30f4e087 | 1428 | int |
e3c71eb2 | 1429 | gf100_gr_init(struct nvkm_object *object) |
4b223eef | 1430 | { |
e3c71eb2 BS |
1431 | struct gf100_gr_oclass *oclass = (void *)object->oclass; |
1432 | struct gf100_gr_priv *priv = (void *)object; | |
30f4e087 BS |
1433 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); |
1434 | u32 data[TPC_MAX / 8] = {}; | |
1435 | u8 tpcnr[GPC_MAX]; | |
1436 | int gpc, tpc, rop; | |
1437 | int ret, i; | |
966a5b7d | 1438 | |
e3c71eb2 | 1439 | ret = nvkm_gr_init(&priv->base); |
ebb945a9 BS |
1440 | if (ret) |
1441 | return ret; | |
1442 | ||
30f4e087 BS |
1443 | nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); |
1444 | nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); | |
1445 | nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); | |
1446 | nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); | |
1447 | nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); | |
1448 | nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); | |
1449 | nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); | |
1450 | nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); | |
1451 | ||
e3c71eb2 | 1452 | gf100_gr_mmio(priv, oclass->mmio); |
30f4e087 | 1453 | |
30f4e087 BS |
1454 | memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); |
1455 | for (i = 0, gpc = -1; i < priv->tpc_total; i++) { | |
1456 | do { | |
1457 | gpc = (gpc + 1) % priv->gpc_nr; | |
1458 | } while (!tpcnr[gpc]); | |
1459 | tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; | |
1460 | ||
1461 | data[i / 8] |= tpc << ((i % 8) * 4); | |
1462 | } | |
1463 | ||
1464 | nv_wr32(priv, GPC_BCAST(0x0980), data[0]); | |
1465 | nv_wr32(priv, GPC_BCAST(0x0984), data[1]); | |
1466 | nv_wr32(priv, GPC_BCAST(0x0988), data[2]); | |
1467 | nv_wr32(priv, GPC_BCAST(0x098c), data[3]); | |
1468 | ||
1469 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
1470 | nv_wr32(priv, GPC_UNIT(gpc, 0x0914), | |
1471 | priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); | |
1472 | nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | | |
1473 | priv->tpc_total); | |
1474 | nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); | |
1475 | } | |
1476 | ||
26410c67 ML |
1477 | if (nv_device(priv)->chipset != 0xd7) |
1478 | nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); | |
1479 | else | |
1480 | nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); | |
1481 | ||
30f4e087 | 1482 | nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); |
ebb945a9 BS |
1483 | |
1484 | nv_wr32(priv, 0x400500, 0x00010001); | |
30f4e087 | 1485 | |
ebb945a9 BS |
1486 | nv_wr32(priv, 0x400100, 0xffffffff); |
1487 | nv_wr32(priv, 0x40013c, 0xffffffff); | |
1488 | ||
30f4e087 BS |
1489 | nv_wr32(priv, 0x409c24, 0x000f0000); |
1490 | nv_wr32(priv, 0x404000, 0xc0000000); | |
1491 | nv_wr32(priv, 0x404600, 0xc0000000); | |
1492 | nv_wr32(priv, 0x408030, 0xc0000000); | |
1493 | nv_wr32(priv, 0x40601c, 0xc0000000); | |
1494 | nv_wr32(priv, 0x404490, 0xc0000000); | |
1495 | nv_wr32(priv, 0x406018, 0xc0000000); | |
1496 | nv_wr32(priv, 0x405840, 0xc0000000); | |
1497 | nv_wr32(priv, 0x405844, 0x00ffffff); | |
1498 | nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); | |
1499 | nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); | |
1500 | ||
1501 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
1502 | nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); | |
1503 | nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
1504 | nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
1505 | nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
1506 | for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { | |
1507 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); | |
1508 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); | |
1509 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); | |
1510 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); | |
1511 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); | |
1512 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); | |
1513 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); | |
1514 | } | |
1515 | nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); | |
1516 | nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
1517 | } | |
1518 | ||
1519 | for (rop = 0; rop < priv->rop_nr; rop++) { | |
1520 | nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); | |
1521 | nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); | |
1522 | nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); | |
1523 | nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); | |
1524 | } | |
ebb945a9 BS |
1525 | |
1526 | nv_wr32(priv, 0x400108, 0xffffffff); | |
1527 | nv_wr32(priv, 0x400138, 0xffffffff); | |
1528 | nv_wr32(priv, 0x400118, 0xffffffff); | |
1529 | nv_wr32(priv, 0x400130, 0xffffffff); | |
1530 | nv_wr32(priv, 0x40011c, 0xffffffff); | |
1531 | nv_wr32(priv, 0x400134, 0xffffffff); | |
30f4e087 | 1532 | |
ebb945a9 | 1533 | nv_wr32(priv, 0x400054, 0x34ce3464); |
ac9738bb | 1534 | |
e3c71eb2 | 1535 | gf100_gr_zbc_init(priv); |
ac9738bb | 1536 | |
e3c71eb2 | 1537 | return gf100_gr_init_ctxctl(priv); |
30f4e087 BS |
1538 | } |
1539 | ||
c4d0f8f6 | 1540 | void |
e3c71eb2 | 1541 | gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) |
30f4e087 BS |
1542 | { |
1543 | kfree(fuc->data); | |
1544 | fuc->data = NULL; | |
1545 | } | |
1546 | ||
1547 | int | |
e3c71eb2 BS |
1548 | gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, |
1549 | struct gf100_gr_fuc *fuc) | |
30f4e087 | 1550 | { |
e3c71eb2 | 1551 | struct nvkm_device *device = nv_device(priv); |
30f4e087 | 1552 | const struct firmware *fw; |
8539b37a AC |
1553 | char f[64]; |
1554 | char cname[16]; | |
30f4e087 | 1555 | int ret; |
8539b37a AC |
1556 | int i; |
1557 | ||
1558 | /* Convert device name to lowercase */ | |
1559 | strncpy(cname, device->cname, sizeof(cname)); | |
1560 | cname[sizeof(cname) - 1] = '\0'; | |
1561 | i = strlen(cname); | |
1562 | while (i) { | |
1563 | --i; | |
1564 | cname[i] = tolower(cname[i]); | |
1565 | } | |
30f4e087 | 1566 | |
8539b37a | 1567 | snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); |
420b9469 | 1568 | ret = request_firmware(&fw, f, nv_device_base(device)); |
30f4e087 | 1569 | if (ret) { |
8539b37a AC |
1570 | nv_error(priv, "failed to load %s\n", fwname); |
1571 | return ret; | |
30f4e087 BS |
1572 | } |
1573 | ||
1574 | fuc->size = fw->size; | |
1575 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); | |
1576 | release_firmware(fw); | |
1577 | return (fuc->data != NULL) ? 0 : -ENOMEM; | |
1578 | } | |
1579 | ||
1580 | void | |
e3c71eb2 | 1581 | gf100_gr_dtor(struct nvkm_object *object) |
30f4e087 | 1582 | { |
e3c71eb2 | 1583 | struct gf100_gr_priv *priv = (void *)object; |
30f4e087 BS |
1584 | |
1585 | kfree(priv->data); | |
1586 | ||
e3c71eb2 BS |
1587 | gf100_gr_dtor_fw(&priv->fuc409c); |
1588 | gf100_gr_dtor_fw(&priv->fuc409d); | |
1589 | gf100_gr_dtor_fw(&priv->fuc41ac); | |
1590 | gf100_gr_dtor_fw(&priv->fuc41ad); | |
30f4e087 | 1591 | |
e3c71eb2 BS |
1592 | nvkm_gpuobj_ref(NULL, &priv->unk4188b8); |
1593 | nvkm_gpuobj_ref(NULL, &priv->unk4188b4); | |
30f4e087 | 1594 | |
e3c71eb2 | 1595 | nvkm_gr_destroy(&priv->base); |
30f4e087 BS |
1596 | } |
1597 | ||
1598 | int | |
e3c71eb2 BS |
1599 | gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
1600 | struct nvkm_oclass *bclass, void *data, u32 size, | |
1601 | struct nvkm_object **pobject) | |
30f4e087 | 1602 | { |
e3c71eb2 BS |
1603 | struct gf100_gr_oclass *oclass = (void *)bclass; |
1604 | struct nvkm_device *device = nv_device(parent); | |
1605 | struct gf100_gr_priv *priv; | |
b7c852a6 | 1606 | bool use_ext_fw, enable; |
b81146b0 | 1607 | int ret, i, j; |
30f4e087 | 1608 | |
e3c71eb2 BS |
1609 | use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", |
1610 | oclass->fecs.ucode == NULL); | |
b7c852a6 AC |
1611 | enable = use_ext_fw || oclass->fecs.ucode != NULL; |
1612 | ||
e3c71eb2 | 1613 | ret = nvkm_gr_create(parent, engine, bclass, enable, &priv); |
30f4e087 BS |
1614 | *pobject = nv_object(priv); |
1615 | if (ret) | |
1616 | return ret; | |
1617 | ||
aa4d7a4d | 1618 | nv_subdev(priv)->unit = 0x08001000; |
e3c71eb2 | 1619 | nv_subdev(priv)->intr = gf100_gr_intr; |
30f4e087 | 1620 | |
e3c71eb2 | 1621 | priv->base.units = gf100_gr_units; |
30f4e087 | 1622 | |
b7c852a6 | 1623 | if (use_ext_fw) { |
30f4e087 | 1624 | nv_info(priv, "using external firmware\n"); |
8539b37a AC |
1625 | if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) || |
1626 | gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) || | |
1627 | gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) || | |
1628 | gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad)) | |
c6f37e0c | 1629 | return -ENODEV; |
30f4e087 BS |
1630 | priv->firmware = true; |
1631 | } | |
1632 | ||
e3c71eb2 BS |
1633 | ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, |
1634 | &priv->unk4188b4); | |
30f4e087 BS |
1635 | if (ret) |
1636 | return ret; | |
ebb945a9 | 1637 | |
e3c71eb2 BS |
1638 | ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, |
1639 | &priv->unk4188b8); | |
b10f20d5 | 1640 | if (ret) |
a82dd49f BS |
1641 | return ret; |
1642 | ||
30f4e087 BS |
1643 | for (i = 0; i < 0x1000; i += 4) { |
1644 | nv_wo32(priv->unk4188b4, i, 0x00000010); | |
1645 | nv_wo32(priv->unk4188b8, i, 0x00000010); | |
1646 | } | |
1647 | ||
1648 | priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; | |
1649 | priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; | |
1650 | for (i = 0; i < priv->gpc_nr; i++) { | |
1651 | priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); | |
1652 | priv->tpc_total += priv->tpc_nr[i]; | |
b81146b0 BS |
1653 | priv->ppc_nr[i] = oclass->ppc_nr; |
1654 | for (j = 0; j < priv->ppc_nr[i]; j++) { | |
1655 | u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); | |
1656 | priv->ppc_tpc_nr[i][j] = hweight8(mask); | |
1657 | } | |
30f4e087 BS |
1658 | } |
1659 | ||
1660 | /*XXX: these need figuring out... though it might not even matter */ | |
1661 | switch (nv_device(priv)->chipset) { | |
1662 | case 0xc0: | |
1663 | if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ | |
1664 | priv->magic_not_rop_nr = 0x07; | |
1665 | } else | |
1666 | if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ | |
1667 | priv->magic_not_rop_nr = 0x05; | |
1668 | } else | |
1669 | if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ | |
1670 | priv->magic_not_rop_nr = 0x06; | |
1671 | } | |
1672 | break; | |
1673 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
1674 | priv->magic_not_rop_nr = 0x03; | |
1675 | break; | |
1676 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
1677 | priv->magic_not_rop_nr = 0x01; | |
1678 | break; | |
1679 | case 0xc1: /* 2/0/0/0, 1 */ | |
1680 | priv->magic_not_rop_nr = 0x01; | |
1681 | break; | |
1682 | case 0xc8: /* 4/4/3/4, 5 */ | |
1683 | priv->magic_not_rop_nr = 0x06; | |
1684 | break; | |
1685 | case 0xce: /* 4/4/0/0, 4 */ | |
1686 | priv->magic_not_rop_nr = 0x03; | |
1687 | break; | |
1688 | case 0xcf: /* 4/0/0/0, 3 */ | |
1689 | priv->magic_not_rop_nr = 0x03; | |
1690 | break; | |
26410c67 | 1691 | case 0xd7: |
30f4e087 | 1692 | case 0xd9: /* 1/0/0/0, 1 */ |
c4d0f8f6 | 1693 | case 0xea: /* gk20a */ |
a032fb9d | 1694 | case 0x12b: /* gm20b */ |
30f4e087 BS |
1695 | priv->magic_not_rop_nr = 0x01; |
1696 | break; | |
1697 | } | |
1698 | ||
1699 | nv_engine(priv)->cclass = *oclass->cclass; | |
1700 | nv_engine(priv)->sclass = oclass->sclass; | |
4b223eef BS |
1701 | return 0; |
1702 | } | |
1703 | ||
e3c71eb2 | 1704 | #include "fuc/hubgf100.fuc3.h" |
30f4e087 | 1705 | |
e3c71eb2 BS |
1706 | struct gf100_gr_ucode |
1707 | gf100_gr_fecs_ucode = { | |
1708 | .code.data = gf100_grhub_code, | |
1709 | .code.size = sizeof(gf100_grhub_code), | |
1710 | .data.data = gf100_grhub_data, | |
1711 | .data.size = sizeof(gf100_grhub_data), | |
30f4e087 BS |
1712 | }; |
1713 | ||
e3c71eb2 | 1714 | #include "fuc/gpcgf100.fuc3.h" |
30f4e087 | 1715 | |
e3c71eb2 BS |
1716 | struct gf100_gr_ucode |
1717 | gf100_gr_gpccs_ucode = { | |
1718 | .code.data = gf100_grgpc_code, | |
1719 | .code.size = sizeof(gf100_grgpc_code), | |
1720 | .data.data = gf100_grgpc_data, | |
1721 | .data.size = sizeof(gf100_grgpc_data), | |
30f4e087 BS |
1722 | }; |
1723 | ||
e3c71eb2 BS |
1724 | struct nvkm_oclass * |
1725 | gf100_gr_oclass = &(struct gf100_gr_oclass) { | |
30f4e087 | 1726 | .base.handle = NV_ENGINE(GR, 0xc0), |
e3c71eb2 BS |
1727 | .base.ofuncs = &(struct nvkm_ofuncs) { |
1728 | .ctor = gf100_gr_ctor, | |
1729 | .dtor = gf100_gr_dtor, | |
1730 | .init = gf100_gr_init, | |
1731 | .fini = _nvkm_gr_fini, | |
ebb945a9 | 1732 | }, |
e3c71eb2 BS |
1733 | .cclass = &gf100_grctx_oclass, |
1734 | .sclass = gf100_gr_sclass, | |
1735 | .mmio = gf100_gr_pack_mmio, | |
1736 | .fecs.ucode = &gf100_gr_fecs_ucode, | |
1737 | .gpccs.ucode = &gf100_gr_gpccs_ucode, | |
30f4e087 | 1738 | }.base; |