[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / gk20a.c

/*
 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
#include "gf100.h"
#include "ctxgf100.h"

#include <subdev/timer.h>

#include <nvif/class.h>

struct gk20a_fw_av
{
	u32 addr;
	u32 data;
};

int
gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name,
		    struct gf100_gr_pack **ppack)
{
	struct gf100_gr_fuc fuc;
	struct gf100_gr_init *init;
	struct gf100_gr_pack *pack;
	int nent;
	int ret;
	int i;

	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	if (ret)
		return ret;

	nent = (fuc.size / sizeof(struct gk20a_fw_av));
	pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
	if (!pack) {
		ret = -ENOMEM;
		goto end;
	}

	init = (void *)(pack + 2);
	pack[0].init = init;

	for (i = 0; i < nent; i++) {
		struct gf100_gr_init *ent = &init[i];
		struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i];

		ent->addr = av->addr;
		ent->data = av->data;
		ent->count = 1;
		ent->pitch = 1;
	}

	*ppack = pack;

end:
	gf100_gr_dtor_fw(&fuc);
	return ret;
}

struct gk20a_fw_aiv
{
	u32 addr;
	u32 index;
	u32 data;
};

int
gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name,
		     struct gf100_gr_pack **ppack)
{
	struct gf100_gr_fuc fuc;
	struct gf100_gr_init *init;
	struct gf100_gr_pack *pack;
	int nent;
	int ret;
	int i;

	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	if (ret)
		return ret;

	nent = (fuc.size / sizeof(struct gk20a_fw_aiv));
	pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
	if (!pack) {
		ret = -ENOMEM;
		goto end;
	}

	init = (void *)(pack + 2);
	pack[0].init = init;

	for (i = 0; i < nent; i++) {
		struct gf100_gr_init *ent = &init[i];
		struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc.data)[i];

		ent->addr = av->addr;
		ent->data = av->data;
		ent->count = 1;
		ent->pitch = 1;
	}

	*ppack = pack;

end:
	gf100_gr_dtor_fw(&fuc);
	return ret;
}

int
gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name,
		      struct gf100_gr_pack **ppack)
{
	struct gf100_gr_fuc fuc;
	struct gf100_gr_init *init;
	struct gf100_gr_pack *pack;
	/* We don't suppose we will initialize more than 16 classes here... */
	static const unsigned int max_classes = 16;
	u32 classidx = 0, prevclass = 0;
	int nent;
	int ret;
	int i;

	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	if (ret)
		return ret;

	nent = (fuc.size / sizeof(struct gk20a_fw_av));

	pack = vzalloc((sizeof(*pack) * max_classes) +
		       (sizeof(*init) * (nent + 1)));
	if (!pack) {
		ret = -ENOMEM;
		goto end;
	}

	init = (void *)(pack + max_classes);

	for (i = 0; i < nent; i++) {
		struct gf100_gr_init *ent = &init[i];
		struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i];
		u32 class = av->addr & 0xffff;
		u32 addr = (av->addr & 0xffff0000) >> 14;

		if (prevclass != class) {
			pack[classidx].init = ent;
			pack[classidx].type = class;
			prevclass = class;
			if (++classidx >= max_classes) {
				vfree(pack);
				ret = -ENOSPC;
				goto end;
			}
		}

		ent->addr = addr;
		ent->data = av->data;
		ent->count = 1;
		ent->pitch = 1;
	}

	*ppack = pack;

end:
	gf100_gr_dtor_fw(&fuc);
	return ret;
}

static int
gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;

	if (nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
			break;
	) < 0) {
		nvkm_error(subdev, "FECS mem scrubbing timeout\n");
		return -ETIMEDOUT;
	}

	if (nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
			break;
	) < 0) {
		nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static void
gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	nvkm_wr32(device, 0x419e44, 0x1ffffe);
	nvkm_wr32(device, 0x419e4c, 0x7f);
}

int
gk20a_gr_init(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
	u32 data[TPC_MAX / 8] = {};
	u8  tpcnr[GPC_MAX];
	int gpc, tpc;
	int ret, i;

	/* Clear SCC RAM */
	nvkm_wr32(device, 0x40802c, 0x1);

	gf100_gr_mmio(gr, gr->fuc_sw_nonctx);

	ret = gk20a_gr_wait_mem_scrubbing(gr);
	if (ret)
		return ret;

	ret = gf100_gr_wait_idle(gr);
	if (ret)
		return ret;

	/* MMU debug buffer */
	if (gr->func->init_gpc_mmu)
		gr->func->init_gpc_mmu(gr);

	/* Set the PE as stream master */
	nvkm_mask(device, 0x503018, 0x1, 0x1);

	/* Zcull init */
	memset(data, 0x00, sizeof(data));
	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
	for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
		do {
			gpc = (gpc + 1) % gr->gpc_nr;
		} while (!tpcnr[gpc]);
		tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;

		data[i / 8] |= tpc << ((i % 8) * 4);
	}

	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
			  gr->tpc_total);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
	}

	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);

	gr->func->init_rop_active_fbps(gr);

	/* Enable FIFO access */
	nvkm_wr32(device, 0x400500, 0x00010001);

	/* Enable interrupts */
	nvkm_wr32(device, 0x400100, 0xffffffff);
	nvkm_wr32(device, 0x40013c, 0xffffffff);

	/* Enable FECS error interrupts */
	nvkm_wr32(device, 0x409c24, 0x000f0000);

	/* Enable hardware warning exceptions */
	nvkm_wr32(device, 0x404000, 0xc0000000);
	nvkm_wr32(device, 0x404600, 0xc0000000);

	if (gr->func->set_hww_esr_report_mask)
		gr->func->set_hww_esr_report_mask(gr);

	/* Enable TPC exceptions per GPC */
	nvkm_wr32(device, 0x419d0c, 0x2);
	nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);

	/* Reset and enable all exceptions */
	nvkm_wr32(device, 0x400108, 0xffffffff);
	nvkm_wr32(device, 0x400138, 0xffffffff);
	nvkm_wr32(device, 0x400118, 0xffffffff);
	nvkm_wr32(device, 0x400130, 0xffffffff);
	nvkm_wr32(device, 0x40011c, 0xffffffff);
	nvkm_wr32(device, 0x400134, 0xffffffff);

	gf100_gr_zbc_init(gr);

	return gf100_gr_init_ctxctl(gr);
}

static const struct gf100_gr_func
gk20a_gr = {
	.init = gk20a_gr_init,
	.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
	.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
	.rops = gf100_gr_rops,
	.ppc_nr = 1,
	.grctx = &gk20a_grctx,
	.sclass = {
		{ -1, -1, FERMI_TWOD_A },
		{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },
		{ -1, -1, KEPLER_C, &gf100_fermi },
		{ -1, -1, KEPLER_COMPUTE_A },
		{}
	}
};

int
gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
{
	struct gf100_gr *gr;
	int ret;

	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
		return -ENOMEM;
	*pgr = &gr->base;

	ret = gf100_gr_ctor(&gk20a_gr, device, index, gr);
	if (ret)
		return ret;

	if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
	    gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
	    gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
	    gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
		return -ENODEV;

	ret = gk20a_gr_av_to_init(gr, "sw_nonctx", &gr->fuc_sw_nonctx);
	if (ret)
		return ret;

	ret = gk20a_gr_aiv_to_init(gr, "sw_ctx", &gr->fuc_sw_ctx);
	if (ret)
		return ret;

	ret = gk20a_gr_av_to_init(gr, "sw_bundle_init", &gr->fuc_bundle);
	if (ret)
		return ret;

	ret = gk20a_gr_av_to_method(gr, "sw_method_init", &gr->fuc_method);
	if (ret)
		return ret;

	return 0;
}
Commit	Line	Data
a4d4bbf1	1	/*
c4d0f8f6	2	* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
a4d4bbf1 AC	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	20	* DEALINGS IN THE SOFTWARE.
	21	*/
c85ee6ca	22	#include "gf100.h"
e3c71eb2	23	#include "ctxgf100.h"
a4d4bbf1	24
c4d0f8f6	25	#include <subdev/timer.h>
a4d4bbf1	26
27f3d6cf	27	#include <nvif/class.h>
a4d4bbf1	28
c4d0f8f6 AC	29	struct gk20a_fw_av
	30	{
	31	u32 addr;
	32	u32 data;
	33	};
	34
2e404b0d	35	int
5986d3e1 AC	36	gk20a_gr_av_to_init(struct gf100_gr gr, const char fw_name,
5986d3e1 AC	37	struct gf100_gr_pack **ppack)
c4d0f8f6	38	{
5986d3e1	39	struct gf100_gr_fuc fuc;
c4d0f8f6 AC	40	struct gf100_gr_init *init;
c4d0f8f6 AC	41	struct gf100_gr_pack *pack;
5986d3e1 AC	42	int nent;
5986d3e1 AC	43	int ret;
c4d0f8f6 AC	44	int i;
c4d0f8f6 AC	45
5986d3e1 AC	46	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	47	if (ret)
	48	return ret;
	49
	50	nent = (fuc.size / sizeof(struct gk20a_fw_av));
c4d0f8f6	51	pack = vzalloc((sizeof(pack) 2) + (sizeof(init) (nent + 1)));
5986d3e1 AC	52	if (!pack) {
	53	ret = -ENOMEM;
	54	goto end;
	55	}
c4d0f8f6 AC	56
c4d0f8f6 AC	57	init = (void *)(pack + 2);
c4d0f8f6 AC	58	pack[0].init = init;
	59
	60	for (i = 0; i < nent; i++) {
	61	struct gf100_gr_init *ent = &init[i];
5986d3e1	62	struct gk20a_fw_av av = &((struct gk20a_fw_av )fuc.data)[i];
c4d0f8f6 AC	63
	64	ent->addr = av->addr;
	65	ent->data = av->data;
	66	ent->count = 1;
	67	ent->pitch = 1;
	68	}
	69
5986d3e1 AC	70	*ppack = pack;
	71
	72	end:
	73	gf100_gr_dtor_fw(&fuc);
	74	return ret;
c4d0f8f6 AC	75	}
	76
	77	struct gk20a_fw_aiv
	78	{
	79	u32 addr;
	80	u32 index;
	81	u32 data;
	82	};
	83
2e404b0d	84	int
5986d3e1 AC	85	gk20a_gr_aiv_to_init(struct gf100_gr gr, const char fw_name,
5986d3e1 AC	86	struct gf100_gr_pack **ppack)
c4d0f8f6	87	{
5986d3e1	88	struct gf100_gr_fuc fuc;
c4d0f8f6 AC	89	struct gf100_gr_init *init;
c4d0f8f6 AC	90	struct gf100_gr_pack *pack;
5986d3e1 AC	91	int nent;
5986d3e1 AC	92	int ret;
c4d0f8f6 AC	93	int i;
c4d0f8f6 AC	94
5986d3e1 AC	95	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	96	if (ret)
	97	return ret;
	98
	99	nent = (fuc.size / sizeof(struct gk20a_fw_aiv));
c4d0f8f6	100	pack = vzalloc((sizeof(pack) 2) + (sizeof(init) (nent + 1)));
5986d3e1 AC	101	if (!pack) {
	102	ret = -ENOMEM;
	103	goto end;
	104	}
c4d0f8f6 AC	105
c4d0f8f6 AC	106	init = (void *)(pack + 2);
c4d0f8f6 AC	107	pack[0].init = init;
	108
	109	for (i = 0; i < nent; i++) {
	110	struct gf100_gr_init *ent = &init[i];
5986d3e1	111	struct gk20a_fw_aiv av = &((struct gk20a_fw_aiv )fuc.data)[i];
c4d0f8f6 AC	112
	113	ent->addr = av->addr;
	114	ent->data = av->data;
	115	ent->count = 1;
	116	ent->pitch = 1;
	117	}
	118
5986d3e1 AC	119	*ppack = pack;
	120
	121	end:
	122	gf100_gr_dtor_fw(&fuc);
	123	return ret;
c4d0f8f6 AC	124	}
c4d0f8f6 AC	125
2e404b0d	126	int
5986d3e1 AC	127	gk20a_gr_av_to_method(struct gf100_gr gr, const char fw_name,
5986d3e1 AC	128	struct gf100_gr_pack **ppack)
c4d0f8f6	129	{
5986d3e1	130	struct gf100_gr_fuc fuc;
c4d0f8f6 AC	131	struct gf100_gr_init *init;
	132	struct gf100_gr_pack *pack;
	133	/* We don't suppose we will initialize more than 16 classes here... */
	134	static const unsigned int max_classes = 16;
5986d3e1 AC	135	u32 classidx = 0, prevclass = 0;
	136	int nent;
	137	int ret;
	138	int i;
	139
	140	ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
	141	if (ret)
	142	return ret;
	143
	144	nent = (fuc.size / sizeof(struct gk20a_fw_av));
c4d0f8f6 AC	145
	146	pack = vzalloc((sizeof(pack) max_classes) +
	147	(sizeof(init) (nent + 1)));
5986d3e1 AC	148	if (!pack) {
	149	ret = -ENOMEM;
	150	goto end;
	151	}
c4d0f8f6 AC	152
	153	init = (void *)(pack + max_classes);
	154
	155	for (i = 0; i < nent; i++) {
	156	struct gf100_gr_init *ent = &init[i];
5986d3e1	157	struct gk20a_fw_av av = &((struct gk20a_fw_av )fuc.data)[i];
c4d0f8f6 AC	158	u32 class = av->addr & 0xffff;
	159	u32 addr = (av->addr & 0xffff0000) >> 14;
	160
	161	if (prevclass != class) {
	162	pack[classidx].init = ent;
	163	pack[classidx].type = class;
	164	prevclass = class;
	165	if (++classidx >= max_classes) {
	166	vfree(pack);
5986d3e1 AC	167	ret = -ENOSPC;
5986d3e1 AC	168	goto end;
c4d0f8f6 AC	169	}
	170	}
	171
	172	ent->addr = addr;
	173	ent->data = av->data;
	174	ent->count = 1;
	175	ent->pitch = 1;
	176	}
	177
5986d3e1 AC	178	*ppack = pack;
	179
	180	end:
	181	gf100_gr_dtor_fw(&fuc);
	182	return ret;
c4d0f8f6 AC	183	}
c4d0f8f6 AC	184
c4d0f8f6	185	static int
bfee3f3d	186	gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
c4d0f8f6	187	{
109c2f2f BS	188	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
109c2f2f BS	189	struct nvkm_device *device = subdev->device;
c4584adc BS	190
	191	if (nvkm_msec(device, 2000,
	192	if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
	193	break;
	194	) < 0) {
109c2f2f	195	nvkm_error(subdev, "FECS mem scrubbing timeout\n");
c4d0f8f6 AC	196	return -ETIMEDOUT;
	197	}
	198
c4584adc BS	199	if (nvkm_msec(device, 2000,
	200	if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
	201	break;
	202	) < 0) {
109c2f2f	203	nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
c4d0f8f6 AC	204	return -ETIMEDOUT;
	205	}
	206
	207	return 0;
	208	}
	209
	210	static void
bfee3f3d	211	gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
c4d0f8f6	212	{
276836d4 BS	213	struct nvkm_device *device = gr->base.engine.subdev.device;
	214	nvkm_wr32(device, 0x419e44, 0x1ffffe);
	215	nvkm_wr32(device, 0x419e4c, 0x7f);
c4d0f8f6 AC	216	}
c4d0f8f6 AC	217
a032fb9d	218	int
c85ee6ca	219	gk20a_gr_init(struct gf100_gr *gr)
c4d0f8f6	220	{
276836d4	221	struct nvkm_device *device = gr->base.engine.subdev.device;
bfee3f3d	222	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
c4d0f8f6 AC	223	u32 data[TPC_MAX / 8] = {};
	224	u8 tpcnr[GPC_MAX];
	225	int gpc, tpc;
	226	int ret, i;
	227
c4d0f8f6	228	/* Clear SCC RAM */
276836d4	229	nvkm_wr32(device, 0x40802c, 0x1);
c4d0f8f6	230
bfee3f3d	231	gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
c4d0f8f6	232
bfee3f3d	233	ret = gk20a_gr_wait_mem_scrubbing(gr);
c4d0f8f6 AC	234	if (ret)
	235	return ret;
	236
bfee3f3d	237	ret = gf100_gr_wait_idle(gr);
c4d0f8f6 AC	238	if (ret)
	239	return ret;
	240
	241	/* MMU debug buffer */
c85ee6ca BS	242	if (gr->func->init_gpc_mmu)
c85ee6ca BS	243	gr->func->init_gpc_mmu(gr);
c4d0f8f6 AC	244
c4d0f8f6 AC	245	/* Set the PE as stream master */
276836d4	246	nvkm_mask(device, 0x503018, 0x1, 0x1);
c4d0f8f6 AC	247
	248	/* Zcull init */
	249	memset(data, 0x00, sizeof(data));
bfee3f3d BS	250	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
bfee3f3d BS	251	for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
c4d0f8f6	252	do {
bfee3f3d	253	gpc = (gpc + 1) % gr->gpc_nr;
c4d0f8f6	254	} while (!tpcnr[gpc]);
bfee3f3d	255	tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
c4d0f8f6 AC	256
	257	data[i / 8] \|= tpc << ((i % 8) * 4);
	258	}
	259
276836d4 BS	260	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
	261	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
	262	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
	263	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
bfee3f3d BS	264
bfee3f3d BS	265	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
276836d4	266	nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
5ec3def7	267	gr->screen_tile_row_offset << 8 \| gr->tpc_nr[gpc]);
276836d4 BS	268	nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 \|
	269	gr->tpc_total);
	270	nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
c4d0f8f6 AC	271	}
c4d0f8f6 AC	272
276836d4	273	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
c4d0f8f6	274
87ac331e BS	275	gr->func->init_rop_active_fbps(gr);
87ac331e BS	276
c4d0f8f6	277	/* Enable FIFO access */
276836d4	278	nvkm_wr32(device, 0x400500, 0x00010001);
c4d0f8f6 AC	279
c4d0f8f6 AC	280	/* Enable interrupts */
276836d4 BS	281	nvkm_wr32(device, 0x400100, 0xffffffff);
276836d4 BS	282	nvkm_wr32(device, 0x40013c, 0xffffffff);
c4d0f8f6 AC	283
c4d0f8f6 AC	284	/* Enable FECS error interrupts */
276836d4	285	nvkm_wr32(device, 0x409c24, 0x000f0000);
c4d0f8f6 AC	286
c4d0f8f6 AC	287	/* Enable hardware warning exceptions */
276836d4 BS	288	nvkm_wr32(device, 0x404000, 0xc0000000);
276836d4 BS	289	nvkm_wr32(device, 0x404600, 0xc0000000);
c4d0f8f6	290
c85ee6ca BS	291	if (gr->func->set_hww_esr_report_mask)
c85ee6ca BS	292	gr->func->set_hww_esr_report_mask(gr);
c4d0f8f6 AC	293
c4d0f8f6 AC	294	/* Enable TPC exceptions per GPC */
276836d4 BS	295	nvkm_wr32(device, 0x419d0c, 0x2);
276836d4 BS	296	nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
c4d0f8f6 AC	297
c4d0f8f6 AC	298	/* Reset and enable all exceptions */
276836d4 BS	299	nvkm_wr32(device, 0x400108, 0xffffffff);
	300	nvkm_wr32(device, 0x400138, 0xffffffff);
	301	nvkm_wr32(device, 0x400118, 0xffffffff);
	302	nvkm_wr32(device, 0x400130, 0xffffffff);
	303	nvkm_wr32(device, 0x40011c, 0xffffffff);
	304	nvkm_wr32(device, 0x400134, 0xffffffff);
c4d0f8f6	305
bfee3f3d	306	gf100_gr_zbc_init(gr);
c4d0f8f6	307
bfee3f3d	308	return gf100_gr_init_ctxctl(gr);
c4d0f8f6 AC	309	}
c4d0f8f6 AC	310
f008d8c7 AC	311	static const struct gf100_gr_func
	312	gk20a_gr = {
	313	.init = gk20a_gr_init,
87ac331e	314	.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
f008d8c7	315	.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
64cb5a31	316	.rops = gf100_gr_rops,
f008d8c7 AC	317	.ppc_nr = 1,
	318	.grctx = &gk20a_grctx,
	319	.sclass = {
	320	{ -1, -1, FERMI_TWOD_A },
	321	{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },
	322	{ -1, -1, KEPLER_C, &gf100_fermi },
	323	{ -1, -1, KEPLER_COMPUTE_A },
	324	{}
	325	}
	326	};
	327
c85ee6ca	328	int
f008d8c7	329	gk20a_gr_new(struct nvkm_device device, int index, struct nvkm_gr *pgr)
c85ee6ca	330	{
c85ee6ca BS	331	struct gf100_gr *gr;
	332	int ret;
	333
	334	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
	335	return -ENOMEM;
	336	*pgr = &gr->base;
	337
f008d8c7	338	ret = gf100_gr_ctor(&gk20a_gr, device, index, gr);
c85ee6ca BS	339	if (ret)
	340	return ret;
	341
18cd5bc8 AC	342	if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) \|\|
	343	gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) \|\|
	344	gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) \|\|
	345	gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
	346	return -ENODEV;
	347
5986d3e1	348	ret = gk20a_gr_av_to_init(gr, "sw_nonctx", &gr->fuc_sw_nonctx);
c85ee6ca BS	349	if (ret)
c85ee6ca BS	350	return ret;
c85ee6ca	351
5986d3e1	352	ret = gk20a_gr_aiv_to_init(gr, "sw_ctx", &gr->fuc_sw_ctx);
c85ee6ca BS	353	if (ret)
c85ee6ca BS	354	return ret;
c85ee6ca	355
5986d3e1	356	ret = gk20a_gr_av_to_init(gr, "sw_bundle_init", &gr->fuc_bundle);
c85ee6ca BS	357	if (ret)
c85ee6ca BS	358	return ret;
c85ee6ca	359
5986d3e1	360	ret = gk20a_gr_av_to_method(gr, "sw_method_init", &gr->fuc_method);
c85ee6ca BS	361	if (ret)
c85ee6ca BS	362	return ret;
5986d3e1	363
c85ee6ca BS	364	return 0;
c85ee6ca BS	365	}