[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / base.c

/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
#include <subdev/fb.h>
#include <subdev/therm.h>
#include <subdev/volt.h>

#include <core/option.h>

/******************************************************************************
 * misc
 *****************************************************************************/
static u32
nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
		u8 pstate, u8 domain, u32 input)
{
	struct nvkm_bios *bios = clk->subdev.device->bios;
	struct nvbios_boostE boostE;
	u8  ver, hdr, cnt, len;
	u16 data;

	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
	if (data) {
		struct nvbios_boostS boostS;
		u8  idx = 0, sver, shdr;
		u16 subd;

		input = max(boostE.min, input);
		input = min(boostE.max, input);
		do {
			sver = ver;
			shdr = hdr;
			subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
					      cnt, len, &boostS);
			if (subd && boostS.domain == domain) {
				if (adjust)
					input = input * boostS.percent / 100;
				input = max(boostS.min, input);
				input = min(boostS.max, input);
				break;
			}
		} while (subd);
	}

	return input;
}

/******************************************************************************
 * C-States
 *****************************************************************************/
static int
nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
{
	struct nvkm_subdev *subdev = &clk->subdev;
	struct nvkm_device *device = subdev->device;
	struct nvkm_therm *therm = device->therm;
	struct nvkm_volt *volt = device->volt;
	struct nvkm_cstate *cstate;
	int ret;

	if (!list_empty(&pstate->list)) {
		cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
	} else {
		cstate = &pstate->base;
	}

	if (therm) {
		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
		if (ret && ret != -ENODEV) {
			nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
			return ret;
		}
	}

	if (volt) {
		ret = nvkm_volt_set_id(volt, cstate->voltage, +1);
		if (ret && ret != -ENODEV) {
			nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
			return ret;
		}
	}

	ret = clk->func->calc(clk, cstate);
	if (ret == 0) {
		ret = clk->func->prog(clk);
		clk->func->tidy(clk);
	}

	if (volt) {
		ret = nvkm_volt_set_id(volt, cstate->voltage, -1);
		if (ret && ret != -ENODEV)
			nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
	}

	if (therm) {
		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
		if (ret && ret != -ENODEV)
			nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
	}

	return ret;
}

static void
nvkm_cstate_del(struct nvkm_cstate *cstate)
{
	list_del(&cstate->head);
	kfree(cstate);
}

static int
nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
{
	struct nvkm_bios *bios = clk->subdev.device->bios;
	const struct nvkm_domain *domain = clk->domains;
	struct nvkm_cstate *cstate = NULL;
	struct nvbios_cstepX cstepX;
	u8  ver, hdr;
	u16 data;

	data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
	if (!data)
		return -ENOENT;

	cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
	if (!cstate)
		return -ENOMEM;

	*cstate = pstate->base;
	cstate->voltage = cstepX.voltage;

	while (domain && domain->name != nv_clk_src_max) {
		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
			u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
						   domain->bios, cstepX.freq);
			cstate->domain[domain->name] = freq;
		}
		domain++;
	}

	list_add(&cstate->head, &pstate->list);
	return 0;
}

/******************************************************************************
 * P-States
 *****************************************************************************/
static int
nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
{
	struct nvkm_subdev *subdev = &clk->subdev;
	struct nvkm_ram *ram = subdev->device->fb->ram;
	struct nvkm_pci *pci = subdev->device->pci;
	struct nvkm_pstate *pstate;
	int ret, idx = 0;

	list_for_each_entry(pstate, &clk->states, head) {
		if (idx++ == pstatei)
			break;
	}

	nvkm_debug(subdev, "setting performance state %d\n", pstatei);
	clk->pstate = pstatei;

	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);

	if (ram && ram->func->calc) {
		int khz = pstate->base.domain[nv_clk_src_mem];
		do {
			ret = ram->func->calc(ram, khz);
			if (ret == 0)
				ret = ram->func->prog(ram);
		} while (ret > 0);
		ram->func->tidy(ram);
	}

	return nvkm_cstate_prog(clk, pstate, 0);
}

static void
nvkm_pstate_work(struct work_struct *work)
{
	struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
	struct nvkm_subdev *subdev = &clk->subdev;
	int pstate;

	if (!atomic_xchg(&clk->waiting, 0))
		return;
	clk->pwrsrc = power_supply_is_system_supplied();

	nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
		   clk->astate, clk->tstate, clk->dstate);

	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
	if (clk->state_nr && pstate != -1) {
		pstate = (pstate < 0) ? clk->astate : pstate;
		pstate = min(pstate, clk->state_nr - 1 + clk->tstate);
		pstate = max(pstate, clk->dstate);
	} else {
		pstate = clk->pstate = -1;
	}

	nvkm_trace(subdev, "-> %d\n", pstate);
	if (pstate != clk->pstate) {
		int ret = nvkm_pstate_prog(clk, pstate);
		if (ret) {
			nvkm_error(subdev, "error setting pstate %d: %d\n",
				   pstate, ret);
		}
	}

	wake_up_all(&clk->wait);
	nvkm_notify_get(&clk->pwrsrc_ntfy);
}

static int
nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
{
	atomic_set(&clk->waiting, 1);
	schedule_work(&clk->work);
	if (wait)
		wait_event(clk->wait, !atomic_read(&clk->waiting));
	return 0;
}

static void
nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
{
	const struct nvkm_domain *clock = clk->domains - 1;
	struct nvkm_cstate *cstate;
	struct nvkm_subdev *subdev = &clk->subdev;
	char info[3][32] = { "", "", "" };
	char name[4] = "--";
	int i = -1;

	if (pstate->pstate != 0xff)
		snprintf(name, sizeof(name), "%02x", pstate->pstate);

	while ((++clock)->name != nv_clk_src_max) {
		u32 lo = pstate->base.domain[clock->name];
		u32 hi = lo;
		if (hi == 0)
			continue;

		nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
		list_for_each_entry(cstate, &pstate->list, head) {
			u32 freq = cstate->domain[clock->name];
			lo = min(lo, freq);
			hi = max(hi, freq);
			nvkm_debug(subdev, "%10d KHz\n", freq);
		}

		if (clock->mname && ++i < ARRAY_SIZE(info)) {
			lo /= clock->mdiv;
			hi /= clock->mdiv;
			if (lo == hi) {
				snprintf(info[i], sizeof(info[i]), "%s %d MHz",
					 clock->mname, lo);
			} else {
				snprintf(info[i], sizeof(info[i]),
					 "%s %d-%d MHz", clock->mname, lo, hi);
			}
		}
	}

	nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
}

static void
nvkm_pstate_del(struct nvkm_pstate *pstate)
{
	struct nvkm_cstate *cstate, *temp;

	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
		nvkm_cstate_del(cstate);
	}

	list_del(&pstate->head);
	kfree(pstate);
}

static int
nvkm_pstate_new(struct nvkm_clk *clk, int idx)
{
	struct nvkm_bios *bios = clk->subdev.device->bios;
	const struct nvkm_domain *domain = clk->domains - 1;
	struct nvkm_pstate *pstate;
	struct nvkm_cstate *cstate;
	struct nvbios_cstepE cstepE;
	struct nvbios_perfE perfE;
	u8  ver, hdr, cnt, len;
	u16 data;

	data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
	if (!data)
		return -EINVAL;
	if (perfE.pstate == 0xff)
		return 0;

	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
	cstate = &pstate->base;
	if (!pstate)
		return -ENOMEM;

	INIT_LIST_HEAD(&pstate->list);

	pstate->pstate = perfE.pstate;
	pstate->fanspeed = perfE.fanspeed;
	pstate->pcie_speed = perfE.pcie_speed;
	pstate->pcie_width = perfE.pcie_width;
	cstate->voltage = perfE.voltage;
	cstate->domain[nv_clk_src_core] = perfE.core;
	cstate->domain[nv_clk_src_shader] = perfE.shader;
	cstate->domain[nv_clk_src_mem] = perfE.memory;
	cstate->domain[nv_clk_src_vdec] = perfE.vdec;
	cstate->domain[nv_clk_src_dom6] = perfE.disp;

	while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
		struct nvbios_perfS perfS;
		u8  sver = ver, shdr = hdr;
		u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
					  &sver, &shdr, cnt, len, &perfS);
		if (perfSe == 0 || sver != 0x40)
			continue;

		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
			perfS.v40.freq = nvkm_clk_adjust(clk, false,
							 pstate->pstate,
							 domain->bios,
							 perfS.v40.freq);
		}

		cstate->domain[domain->name] = perfS.v40.freq;
	}

	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
	if (data) {
		int idx = cstepE.index;
		do {
			nvkm_cstate_new(clk, idx, pstate);
		} while(idx--);
	}

	nvkm_pstate_info(clk, pstate);
	list_add_tail(&pstate->head, &clk->states);
	clk->state_nr++;
	return 0;
}

/******************************************************************************
 * Adjustment triggers
 *****************************************************************************/
static int
nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
{
	struct nvkm_pstate *pstate;
	int i = 0;

	if (!clk->allow_reclock)
		return -ENOSYS;

	if (req != -1 && req != -2) {
		list_for_each_entry(pstate, &clk->states, head) {
			if (pstate->pstate == req)
				break;
			i++;
		}

		if (pstate->pstate != req)
			return -EINVAL;
		req = i;
	}

	return req + 2;
}

static int
nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen)
{
	int ret = 1;

	if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
		return -2;

	if (strncasecmpz(mode, "disabled", arglen)) {
		char save = mode[arglen];
		long v;

		((char *)mode)[arglen] = '\0';
		if (!kstrtol(mode, 0, &v)) {
			ret = nvkm_clk_ustate_update(clk, v);
			if (ret < 0)
				ret = 1;
		}
		((char *)mode)[arglen] = save;
	}

	return ret - 2;
}

int
nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
{
	int ret = nvkm_clk_ustate_update(clk, req);
	if (ret >= 0) {
		if (ret -= 2, pwr) clk->ustate_ac = ret;
		else		   clk->ustate_dc = ret;
		return nvkm_pstate_calc(clk, true);
	}
	return ret;
}

int
nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
{
	if (!rel) clk->astate  = req;
	if ( rel) clk->astate += rel;
	clk->astate = min(clk->astate, clk->state_nr - 1);
	clk->astate = max(clk->astate, 0);
	return nvkm_pstate_calc(clk, wait);
}

int
nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel)
{
	if (!rel) clk->tstate  = req;
	if ( rel) clk->tstate += rel;
	clk->tstate = min(clk->tstate, 0);
	clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
	return nvkm_pstate_calc(clk, true);
}

int
nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
{
	if (!rel) clk->dstate  = req;
	if ( rel) clk->dstate += rel;
	clk->dstate = min(clk->dstate, clk->state_nr - 1);
	clk->dstate = max(clk->dstate, 0);
	return nvkm_pstate_calc(clk, true);
}

static int
nvkm_clk_pwrsrc(struct nvkm_notify *notify)
{
	struct nvkm_clk *clk =
		container_of(notify, typeof(*clk), pwrsrc_ntfy);
	nvkm_pstate_calc(clk, false);
	return NVKM_NOTIFY_DROP;
}

/******************************************************************************
 * subdev base class implementation
 *****************************************************************************/

int
nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
	return clk->func->read(clk, src);
}

static int
nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
{
	struct nvkm_clk *clk = nvkm_clk(subdev);
	nvkm_notify_put(&clk->pwrsrc_ntfy);
	flush_work(&clk->work);
	if (clk->func->fini)
		clk->func->fini(clk);
	return 0;
}

static int
nvkm_clk_init(struct nvkm_subdev *subdev)
{
	struct nvkm_clk *clk = nvkm_clk(subdev);
	const struct nvkm_domain *clock = clk->domains;
	int ret;

	memset(&clk->bstate, 0x00, sizeof(clk->bstate));
	INIT_LIST_HEAD(&clk->bstate.list);
	clk->bstate.pstate = 0xff;

	while (clock->name != nv_clk_src_max) {
		ret = nvkm_clk_read(clk, clock->name);
		if (ret < 0) {
			nvkm_error(subdev, "%02x freq unknown\n", clock->name);
			return ret;
		}
		clk->bstate.base.domain[clock->name] = ret;
		clock++;
	}

	nvkm_pstate_info(clk, &clk->bstate);

	if (clk->func->init)
		return clk->func->init(clk);

	clk->astate = clk->state_nr - 1;
	clk->tstate = 0;
	clk->dstate = 0;
	clk->pstate = -1;
	nvkm_pstate_calc(clk, true);
	return 0;
}

static void *
nvkm_clk_dtor(struct nvkm_subdev *subdev)
{
	struct nvkm_clk *clk = nvkm_clk(subdev);
	struct nvkm_pstate *pstate, *temp;

	nvkm_notify_fini(&clk->pwrsrc_ntfy);

	/* Early return if the pstates have been provided statically */
	if (clk->func->pstates)
		return clk;

	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
		nvkm_pstate_del(pstate);
	}

	return clk;
}

static const struct nvkm_subdev_func
nvkm_clk = {
	.dtor = nvkm_clk_dtor,
	.init = nvkm_clk_init,
	.fini = nvkm_clk_fini,
};

int
nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
	      int index, bool allow_reclock, struct nvkm_clk *clk)
{
	int ret, idx, arglen;
	const char *mode;

	nvkm_subdev_ctor(&nvkm_clk, device, index, 0, &clk->subdev);
	clk->func = func;
	INIT_LIST_HEAD(&clk->states);
	clk->domains = func->domains;
	clk->ustate_ac = -1;
	clk->ustate_dc = -1;
	clk->allow_reclock = allow_reclock;

	INIT_WORK(&clk->work, nvkm_pstate_work);
	init_waitqueue_head(&clk->wait);
	atomic_set(&clk->waiting, 0);

	/* If no pstates are provided, try and fetch them from the BIOS */
	if (!func->pstates) {
		idx = 0;
		do {
			ret = nvkm_pstate_new(clk, idx++);
		} while (ret == 0);
	} else {
		for (idx = 0; idx < func->nr_pstates; idx++)
			list_add_tail(&func->pstates[idx].head, &clk->states);
		clk->state_nr = func->nr_pstates;
	}

	ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
			       NULL, 0, 0, &clk->pwrsrc_ntfy);
	if (ret)
		return ret;

	mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
	if (mode) {
		clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
		clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
	}

	mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
	if (mode)
		clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);

	mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
	if (mode)
		clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);

	return 0;
}

int
nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
	      int index, bool allow_reclock, struct nvkm_clk **pclk)
{
	if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL)))
		return -ENOMEM;
	return nvkm_clk_ctor(func, device, index, allow_reclock, *pclk);
}
Commit	Line	Data
7c856522 BS	1	/*
	2	* Copyright 2013 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
6625f55c BS	24	#include "priv.h"
6625f55c BS	25
7c856522 BS	26	#include <subdev/bios.h>
	27	#include <subdev/bios/boost.h>
	28	#include <subdev/bios/cstep.h>
	29	#include <subdev/bios/perf.h>
7632b30e BS	30	#include <subdev/fb.h>
	31	#include <subdev/therm.h>
	32	#include <subdev/volt.h>
	33
	34	#include <core/option.h>
7c856522 BS	35
	36	/******************************************************************************
	37	* misc
	38	*****************************************************************************/
	39	static u32
7632b30e BS	40	nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
7632b30e BS	41	u8 pstate, u8 domain, u32 input)
7c856522	42	{
46484438	43	struct nvkm_bios *bios = clk->subdev.device->bios;
7c856522 BS	44	struct nvbios_boostE boostE;
	45	u8 ver, hdr, cnt, len;
	46	u16 data;
	47
	48	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
	49	if (data) {
	50	struct nvbios_boostS boostS;
	51	u8 idx = 0, sver, shdr;
	52	u16 subd;
	53
	54	input = max(boostE.min, input);
	55	input = min(boostE.max, input);
	56	do {
	57	sver = ver;
	58	shdr = hdr;
	59	subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
	60	cnt, len, &boostS);
	61	if (subd && boostS.domain == domain) {
	62	if (adjust)
	63	input = input * boostS.percent / 100;
	64	input = max(boostS.min, input);
	65	input = min(boostS.max, input);
	66	break;
	67	}
	68	} while (subd);
	69	}
	70
	71	return input;
	72	}
	73
	74	/******************************************************************************
	75	* C-States
	76	*****************************************************************************/
	77	static int
7632b30e	78	nvkm_cstate_prog(struct nvkm_clk clk, struct nvkm_pstate pstate, int cstatei)
7c856522	79	{
b907649e BS	80	struct nvkm_subdev *subdev = &clk->subdev;
	81	struct nvkm_device *device = subdev->device;
	82	struct nvkm_therm *therm = device->therm;
	83	struct nvkm_volt *volt = device->volt;
7632b30e	84	struct nvkm_cstate *cstate;
7c856522 BS	85	int ret;
	86
	87	if (!list_empty(&pstate->list)) {
	88	cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
	89	} else {
	90	cstate = &pstate->base;
	91	}
	92
da06b46b BS	93	if (therm) {
da06b46b BS	94	ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
2cfd22f4	95	if (ret && ret != -ENODEV) {
b907649e	96	nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
2cfd22f4 AC	97	return ret;
2cfd22f4 AC	98	}
7c856522 BS	99	}
7c856522 BS	100
2cfd22f4	101	if (volt) {
437b2296	102	ret = nvkm_volt_set_id(volt, cstate->voltage, +1);
2cfd22f4	103	if (ret && ret != -ENODEV) {
b907649e	104	nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
2cfd22f4 AC	105	return ret;
2cfd22f4 AC	106	}
7c856522 BS	107	}
7c856522 BS	108
6625f55c	109	ret = clk->func->calc(clk, cstate);
7c856522	110	if (ret == 0) {
6625f55c BS	111	ret = clk->func->prog(clk);
6625f55c BS	112	clk->func->tidy(clk);
7c856522 BS	113	}
7c856522 BS	114
2cfd22f4	115	if (volt) {
437b2296	116	ret = nvkm_volt_set_id(volt, cstate->voltage, -1);
2cfd22f4	117	if (ret && ret != -ENODEV)
b907649e	118	nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
2cfd22f4	119	}
7c856522	120
da06b46b BS	121	if (therm) {
da06b46b BS	122	ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
2cfd22f4	123	if (ret && ret != -ENODEV)
b907649e	124	nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
2cfd22f4	125	}
7c856522	126
3eca809b	127	return ret;
7c856522 BS	128	}
	129
	130	static void
7632b30e	131	nvkm_cstate_del(struct nvkm_cstate *cstate)
7c856522 BS	132	{
	133	list_del(&cstate->head);
	134	kfree(cstate);
	135	}
	136
	137	static int
7632b30e	138	nvkm_cstate_new(struct nvkm_clk clk, int idx, struct nvkm_pstate pstate)
7c856522	139	{
46484438	140	struct nvkm_bios *bios = clk->subdev.device->bios;
6625f55c	141	const struct nvkm_domain *domain = clk->domains;
7632b30e	142	struct nvkm_cstate *cstate = NULL;
7c856522 BS	143	struct nvbios_cstepX cstepX;
	144	u8 ver, hdr;
	145	u16 data;
	146
	147	data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
	148	if (!data)
	149	return -ENOENT;
	150
	151	cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
	152	if (!cstate)
	153	return -ENOMEM;
	154
	155	*cstate = pstate->base;
	156	cstate->voltage = cstepX.voltage;
	157
	158	while (domain && domain->name != nv_clk_src_max) {
	159	if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
7632b30e BS	160	u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
7632b30e BS	161	domain->bios, cstepX.freq);
7c856522 BS	162	cstate->domain[domain->name] = freq;
	163	}
	164	domain++;
	165	}
	166
	167	list_add(&cstate->head, &pstate->list);
	168	return 0;
	169	}
	170
	171	/******************************************************************************
	172	* P-States
	173	*****************************************************************************/
	174	static int
7632b30e	175	nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
7c856522	176	{
b907649e	177	struct nvkm_subdev *subdev = &clk->subdev;
d36a99d2	178	struct nvkm_ram *ram = subdev->device->fb->ram;
f68f4c96	179	struct nvkm_pci *pci = subdev->device->pci;
7632b30e	180	struct nvkm_pstate *pstate;
7c856522 BS	181	int ret, idx = 0;
	182
	183	list_for_each_entry(pstate, &clk->states, head) {
	184	if (idx++ == pstatei)
	185	break;
	186	}
	187
b907649e	188	nvkm_debug(subdev, "setting performance state %d\n", pstatei);
7c856522 BS	189	clk->pstate = pstatei;
7c856522 BS	190
f68f4c96 KH	191	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);
f68f4c96 KH	192
d36a99d2	193	if (ram && ram->func->calc) {
1789cab4 BS	194	int khz = pstate->base.domain[nv_clk_src_mem];
1789cab4 BS	195	do {
d36a99d2	196	ret = ram->func->calc(ram, khz);
1789cab4	197	if (ret == 0)
d36a99d2	198	ret = ram->func->prog(ram);
1789cab4	199	} while (ret > 0);
d36a99d2	200	ram->func->tidy(ram);
7c856522 BS	201	}
7c856522 BS	202
7632b30e	203	return nvkm_cstate_prog(clk, pstate, 0);
7c856522 BS	204	}
7c856522 BS	205
d5d7a0fa	206	static void
7632b30e	207	nvkm_pstate_work(struct work_struct *work)
7c856522	208	{
7632b30e	209	struct nvkm_clk clk = container_of(work, typeof(clk), work);
b907649e	210	struct nvkm_subdev *subdev = &clk->subdev;
d5d7a0fa BS	211	int pstate;
	212
	213	if (!atomic_xchg(&clk->waiting, 0))
	214	return;
7e1ee633	215	clk->pwrsrc = power_supply_is_system_supplied();
7c856522	216
b907649e BS	217	nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
	218	clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
	219	clk->astate, clk->tstate, clk->dstate);
7c856522	220
7e1ee633 BS	221	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
	222	if (clk->state_nr && pstate != -1) {
	223	pstate = (pstate < 0) ? clk->astate : pstate;
85fa319d	224	pstate = min(pstate, clk->state_nr - 1 + clk->tstate);
7c856522 BS	225	pstate = max(pstate, clk->dstate);
	226	} else {
	227	pstate = clk->pstate = -1;
	228	}
	229
b907649e	230	nvkm_trace(subdev, "-> %d\n", pstate);
d5d7a0fa	231	if (pstate != clk->pstate) {
7632b30e	232	int ret = nvkm_pstate_prog(clk, pstate);
d5d7a0fa	233	if (ret) {
b907649e BS	234	nvkm_error(subdev, "error setting pstate %d: %d\n",
b907649e BS	235	pstate, ret);
d5d7a0fa BS	236	}
	237	}
	238
	239	wake_up_all(&clk->wait);
79ca2770	240	nvkm_notify_get(&clk->pwrsrc_ntfy);
d5d7a0fa BS	241	}
	242
	243	static int
7632b30e	244	nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
d5d7a0fa BS	245	{
	246	atomic_set(&clk->waiting, 1);
	247	schedule_work(&clk->work);
	248	if (wait)
	249	wait_event(clk->wait, !atomic_read(&clk->waiting));
	250	return 0;
7c856522 BS	251	}
	252
	253	static void
7632b30e	254	nvkm_pstate_info(struct nvkm_clk clk, struct nvkm_pstate pstate)
7c856522	255	{
6625f55c	256	const struct nvkm_domain *clock = clk->domains - 1;
7632b30e	257	struct nvkm_cstate *cstate;
b907649e	258	struct nvkm_subdev *subdev = &clk->subdev;
7c856522 BS	259	char info[3][32] = { "", "", "" };
	260	char name[4] = "--";
	261	int i = -1;
	262
	263	if (pstate->pstate != 0xff)
	264	snprintf(name, sizeof(name), "%02x", pstate->pstate);
	265
	266	while ((++clock)->name != nv_clk_src_max) {
	267	u32 lo = pstate->base.domain[clock->name];
	268	u32 hi = lo;
	269	if (hi == 0)
	270	continue;
	271
b907649e	272	nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
7c856522 BS	273	list_for_each_entry(cstate, &pstate->list, head) {
	274	u32 freq = cstate->domain[clock->name];
	275	lo = min(lo, freq);
	276	hi = max(hi, freq);
b907649e	277	nvkm_debug(subdev, "%10d KHz\n", freq);
7c856522 BS	278	}
	279
	280	if (clock->mname && ++i < ARRAY_SIZE(info)) {
	281	lo /= clock->mdiv;
	282	hi /= clock->mdiv;
	283	if (lo == hi) {
	284	snprintf(info[i], sizeof(info[i]), "%s %d MHz",
	285	clock->mname, lo);
	286	} else {
	287	snprintf(info[i], sizeof(info[i]),
	288	"%s %d-%d MHz", clock->mname, lo, hi);
	289	}
	290	}
	291	}
	292
b907649e	293	nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
7c856522 BS	294	}
	295
	296	static void
7632b30e	297	nvkm_pstate_del(struct nvkm_pstate *pstate)
7c856522	298	{
7632b30e	299	struct nvkm_cstate cstate, temp;
7c856522 BS	300
7c856522 BS	301	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
7632b30e	302	nvkm_cstate_del(cstate);
7c856522 BS	303	}
	304
	305	list_del(&pstate->head);
	306	kfree(pstate);
	307	}
	308
	309	static int
7632b30e	310	nvkm_pstate_new(struct nvkm_clk *clk, int idx)
7c856522	311	{
46484438	312	struct nvkm_bios *bios = clk->subdev.device->bios;
6625f55c	313	const struct nvkm_domain *domain = clk->domains - 1;
7632b30e BS	314	struct nvkm_pstate *pstate;
7632b30e BS	315	struct nvkm_cstate *cstate;
7c856522 BS	316	struct nvbios_cstepE cstepE;
	317	struct nvbios_perfE perfE;
	318	u8 ver, hdr, cnt, len;
	319	u16 data;
	320
	321	data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
	322	if (!data)
	323	return -EINVAL;
	324	if (perfE.pstate == 0xff)
	325	return 0;
	326
	327	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
	328	cstate = &pstate->base;
	329	if (!pstate)
	330	return -ENOMEM;
	331
	332	INIT_LIST_HEAD(&pstate->list);
	333
	334	pstate->pstate = perfE.pstate;
	335	pstate->fanspeed = perfE.fanspeed;
d3b378c0 KH	336	pstate->pcie_speed = perfE.pcie_speed;
d3b378c0 KH	337	pstate->pcie_width = perfE.pcie_width;
7c856522 BS	338	cstate->voltage = perfE.voltage;
	339	cstate->domain[nv_clk_src_core] = perfE.core;
	340	cstate->domain[nv_clk_src_shader] = perfE.shader;
	341	cstate->domain[nv_clk_src_mem] = perfE.memory;
	342	cstate->domain[nv_clk_src_vdec] = perfE.vdec;
	343	cstate->domain[nv_clk_src_dom6] = perfE.disp;
	344
	345	while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
	346	struct nvbios_perfS perfS;
	347	u8 sver = ver, shdr = hdr;
	348	u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
	349	&sver, &shdr, cnt, len, &perfS);
	350	if (perfSe == 0 \|\| sver != 0x40)
	351	continue;
	352
	353	if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
7632b30e BS	354	perfS.v40.freq = nvkm_clk_adjust(clk, false,
	355	pstate->pstate,
	356	domain->bios,
	357	perfS.v40.freq);
7c856522 BS	358	}
	359
	360	cstate->domain[domain->name] = perfS.v40.freq;
	361	}
	362
	363	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
	364	if (data) {
	365	int idx = cstepE.index;
	366	do {
7632b30e	367	nvkm_cstate_new(clk, idx, pstate);
7c856522 BS	368	} while(idx--);
	369	}
	370
7632b30e	371	nvkm_pstate_info(clk, pstate);
7c856522 BS	372	list_add_tail(&pstate->head, &clk->states);
	373	clk->state_nr++;
	374	return 0;
	375	}
	376
	377	/******************************************************************************
	378	* Adjustment triggers
	379	*****************************************************************************/
	380	static int
7632b30e	381	nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
7c856522	382	{
7632b30e	383	struct nvkm_pstate *pstate;
7c856522 BS	384	int i = 0;
7c856522 BS	385
ed05ba72 IM	386	if (!clk->allow_reclock)
ed05ba72 IM	387	return -ENOSYS;
7c856522 BS	388
	389	if (req != -1 && req != -2) {
	390	list_for_each_entry(pstate, &clk->states, head) {
	391	if (pstate->pstate == req)
	392	break;
	393	i++;
	394	}
	395
	396	if (pstate->pstate != req)
	397	return -EINVAL;
	398	req = i;
	399	}
	400
7e1ee633 BS	401	return req + 2;
	402	}
	403
	404	static int
7632b30e	405	nvkm_clk_nstate(struct nvkm_clk clk, const char mode, int arglen)
7e1ee633 BS	406	{
	407	int ret = 1;
	408
9f79b5ce VH	409	if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
	410	return -2;
	411
7e1ee633 BS	412	if (strncasecmpz(mode, "disabled", arglen)) {
	413	char save = mode[arglen];
	414	long v;
	415
	416	((char *)mode)[arglen] = '\0';
	417	if (!kstrtol(mode, 0, &v)) {
7632b30e	418	ret = nvkm_clk_ustate_update(clk, v);
7e1ee633 BS	419	if (ret < 0)
	420	ret = 1;
	421	}
	422	((char *)mode)[arglen] = save;
	423	}
	424
	425	return ret - 2;
7c856522 BS	426	}
	427
	428	int
7632b30e	429	nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
7c856522	430	{
7632b30e	431	int ret = nvkm_clk_ustate_update(clk, req);
7e1ee633 BS	432	if (ret >= 0) {
	433	if (ret -= 2, pwr) clk->ustate_ac = ret;
	434	else clk->ustate_dc = ret;
7632b30e	435	return nvkm_pstate_calc(clk, true);
7e1ee633 BS	436	}
7e1ee633 BS	437	return ret;
7c856522 BS	438	}
	439
	440	int
7632b30e	441	nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
7c856522 BS	442	{
	443	if (!rel) clk->astate = req;
	444	if ( rel) clk->astate += rel;
	445	clk->astate = min(clk->astate, clk->state_nr - 1);
	446	clk->astate = max(clk->astate, 0);
7632b30e	447	return nvkm_pstate_calc(clk, wait);
7c856522 BS	448	}
	449
	450	int
7632b30e	451	nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel)
7c856522 BS	452	{
	453	if (!rel) clk->tstate = req;
	454	if ( rel) clk->tstate += rel;
	455	clk->tstate = min(clk->tstate, 0);
	456	clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
7632b30e	457	return nvkm_pstate_calc(clk, true);
7c856522 BS	458	}
	459
	460	int
7632b30e	461	nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
7c856522 BS	462	{
	463	if (!rel) clk->dstate = req;
	464	if ( rel) clk->dstate += rel;
	465	clk->dstate = min(clk->dstate, clk->state_nr - 1);
	466	clk->dstate = max(clk->dstate, 0);
7632b30e	467	return nvkm_pstate_calc(clk, true);
7c856522 BS	468	}
7c856522 BS	469
7e1ee633	470	static int
7632b30e	471	nvkm_clk_pwrsrc(struct nvkm_notify *notify)
7e1ee633	472	{
7632b30e	473	struct nvkm_clk *clk =
79ca2770	474	container_of(notify, typeof(*clk), pwrsrc_ntfy);
7632b30e	475	nvkm_pstate_calc(clk, false);
79ca2770	476	return NVKM_NOTIFY_DROP;
7e1ee633 BS	477	}
7e1ee633 BS	478
7c856522 BS	479	/******************************************************************************
	480	* subdev base class implementation
	481	*****************************************************************************/
7e1ee633 BS	482
7e1ee633 BS	483	int
6625f55c	484	nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
7e1ee633	485	{
6625f55c BS	486	return clk->func->read(clk, src);
	487	}
	488
	489	static int
	490	nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
	491	{
	492	struct nvkm_clk *clk = nvkm_clk(subdev);
79ca2770	493	nvkm_notify_put(&clk->pwrsrc_ntfy);
6625f55c BS	494	flush_work(&clk->work);
	495	if (clk->func->fini)
	496	clk->func->fini(clk);
	497	return 0;
7e1ee633 BS	498	}
7e1ee633 BS	499
6625f55c BS	500	static int
6625f55c BS	501	nvkm_clk_init(struct nvkm_subdev *subdev)
7c856522	502	{
6625f55c BS	503	struct nvkm_clk *clk = nvkm_clk(subdev);
6625f55c BS	504	const struct nvkm_domain *clock = clk->domains;
7c856522 BS	505	int ret;
	506
	507	memset(&clk->bstate, 0x00, sizeof(clk->bstate));
	508	INIT_LIST_HEAD(&clk->bstate.list);
	509	clk->bstate.pstate = 0xff;
	510
	511	while (clock->name != nv_clk_src_max) {
6625f55c	512	ret = nvkm_clk_read(clk, clock->name);
7c856522	513	if (ret < 0) {
b907649e	514	nvkm_error(subdev, "%02x freq unknown\n", clock->name);
7c856522 BS	515	return ret;
	516	}
	517	clk->bstate.base.domain[clock->name] = ret;
	518	clock++;
	519	}
	520
7632b30e	521	nvkm_pstate_info(clk, &clk->bstate);
7c856522	522
6625f55c BS	523	if (clk->func->init)
	524	return clk->func->init(clk);
	525
7c856522 BS	526	clk->astate = clk->state_nr - 1;
	527	clk->tstate = 0;
	528	clk->dstate = 0;
	529	clk->pstate = -1;
7632b30e	530	nvkm_pstate_calc(clk, true);
7c856522 BS	531	return 0;
	532	}
	533
6625f55c BS	534	static void *
6625f55c BS	535	nvkm_clk_dtor(struct nvkm_subdev *subdev)
7c856522	536	{
6625f55c	537	struct nvkm_clk *clk = nvkm_clk(subdev);
7632b30e	538	struct nvkm_pstate pstate, temp;
7c856522	539
79ca2770	540	nvkm_notify_fini(&clk->pwrsrc_ntfy);
7e1ee633	541
6625f55c BS	542	/* Early return if the pstates have been provided statically */
	543	if (clk->func->pstates)
	544	return clk;
	545
7c856522	546	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
7632b30e	547	nvkm_pstate_del(pstate);
7c856522 BS	548	}
7c856522 BS	549
6625f55c	550	return clk;
7c856522 BS	551	}
7c856522 BS	552
6625f55c BS	553	static const struct nvkm_subdev_func
	554	nvkm_clk = {
	555	.dtor = nvkm_clk_dtor,
	556	.init = nvkm_clk_init,
	557	.fini = nvkm_clk_fini,
	558	};
	559
7c856522	560	int
6625f55c BS	561	nvkm_clk_ctor(const struct nvkm_clk_func func, struct nvkm_device device,
6625f55c BS	562	int index, bool allow_reclock, struct nvkm_clk *clk)
7c856522	563	{
7c856522 BS	564	int ret, idx, arglen;
	565	const char *mode;
	566
6625f55c BS	567	nvkm_subdev_ctor(&nvkm_clk, device, index, 0, &clk->subdev);
6625f55c BS	568	clk->func = func;
7c856522	569	INIT_LIST_HEAD(&clk->states);
6625f55c	570	clk->domains = func->domains;
7e1ee633 BS	571	clk->ustate_ac = -1;
7e1ee633 BS	572	clk->ustate_dc = -1;
6625f55c	573	clk->allow_reclock = allow_reclock;
7c856522	574
7632b30e	575	INIT_WORK(&clk->work, nvkm_pstate_work);
d5d7a0fa BS	576	init_waitqueue_head(&clk->wait);
	577	atomic_set(&clk->waiting, 0);
	578
bb4d29df	579	/* If no pstates are provided, try and fetch them from the BIOS */
6625f55c	580	if (!func->pstates) {
bb4d29df AC	581	idx = 0;
bb4d29df AC	582	do {
7632b30e	583	ret = nvkm_pstate_new(clk, idx++);
bb4d29df AC	584	} while (ret == 0);
bb4d29df AC	585	} else {
6625f55c BS	586	for (idx = 0; idx < func->nr_pstates; idx++)
	587	list_add_tail(&func->pstates[idx].head, &clk->states);
	588	clk->state_nr = func->nr_pstates;
bb4d29df	589	}
7c856522	590
7632b30e	591	ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
79ca2770	592	NULL, 0, 0, &clk->pwrsrc_ntfy);
7e1ee633 BS	593	if (ret)
	594	return ret;
	595
7632b30e	596	mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
7c856522	597	if (mode) {
7632b30e BS	598	clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
7632b30e BS	599	clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
7c856522 BS	600	}
7c856522 BS	601
7632b30e	602	mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
7e1ee633	603	if (mode)
7632b30e	604	clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
7e1ee633	605
7632b30e	606	mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
7e1ee633	607	if (mode)
7632b30e	608	clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
7e1ee633	609
7c856522 BS	610	return 0;
7c856522 BS	611	}
6625f55c BS	612
	613	int
	614	nvkm_clk_new_(const struct nvkm_clk_func func, struct nvkm_device device,
	615	int index, bool allow_reclock, struct nvkm_clk **pclk)
	616	{
	617	if (!(pclk = kzalloc(sizeof(*pclk), GFP_KERNEL)))
	618	return -ENOMEM;
	619	return nvkm_clk_ctor(func, device, index, allow_reclock, *pclk);
	620	}