[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#define gf100_clk(p) container_of((p), struct gf100_clk, base)
#include "priv.h"
#include "pll.h"

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

struct gf100_clk_info {
	u32 freq;
	u32 ssel;
	u32 mdiv;
	u32 dsrc;
	u32 ddiv;
	u32 coef;
};

struct gf100_clk {
	struct nvkm_clk base;
	struct gf100_clk_info eng[16];
};

static u32 read_div(struct gf100_clk *, int, u32, u32);

static u32
read_vco(struct gf100_clk *clk, u32 dsrc)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc);
	if (!(ssrc & 0x00000100))
		return nvkm_clk_read(&clk->base, nv_clk_src_sppll0);
	return nvkm_clk_read(&clk->base, nv_clk_src_sppll1);
}

static u32
read_pll(struct gf100_clk *clk, u32 pll)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	u32 coef = nvkm_rd32(device, pll + 0x04);
	u32 P = (coef & 0x003f0000) >> 16;
	u32 N = (coef & 0x0000ff00) >> 8;
	u32 M = (coef & 0x000000ff) >> 0;
	u32 sclk;

	if (!(ctrl & 0x00000001))
		return 0;

	switch (pll) {
	case 0x00e800:
	case 0x00e820:
		sclk = device->crystal;
		P = 1;
		break;
	case 0x132000:
		sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
		break;
	case 0x132020:
		sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
		break;
	case 0x137000:
	case 0x137020:
	case 0x137040:
	case 0x1370e0:
		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
		break;
	default:
		return 0;
	}

	return sclk * N / M / P;
}

static u32
read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
	u32 sclk, sctl, sdiv = 2;

	switch (ssrc & 0x00000003) {
	case 0:
		if ((ssrc & 0x00030000) != 0x00030000)
			return device->crystal;
		return 108000;
	case 2:
		return 100000;
	case 3:
		sclk = read_vco(clk, dsrc + (doff * 4));

		/* Memclk has doff of 0 despite its alt. location */
		if (doff <= 2) {
			sctl = nvkm_rd32(device, dctl + (doff * 4));

			if (sctl & 0x80000000) {
				if (ssrc & 0x100)
					sctl >>= 8;

				sdiv = (sctl & 0x3f) + 2;
			}
		}

		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_clk(struct gf100_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
	u32 ssel = nvkm_rd32(device, 0x137100);
	u32 sclk, sdiv;

	if (ssel & (1 << idx)) {
		if (idx < 7)
			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
		else
			sclk = read_pll(clk, 0x1370e0);
		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	} else {
		sclk = read_div(clk, idx, 0x137160, 0x1371d0);
		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	}

	if (sctl & 0x80000000)
		return (sclk * 2) / sdiv;

	return sclk;
}

static int
gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
{
	struct gf100_clk *clk = gf100_clk(base);
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_device *device = subdev->device;

	switch (src) {
	case nv_clk_src_crystal:
		return device->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_sppll0:
		return read_pll(clk, 0x00e800);
	case nv_clk_src_sppll1:
		return read_pll(clk, 0x00e820);

	case nv_clk_src_mpllsrcref:
		return read_div(clk, 0, 0x137320, 0x137330);
	case nv_clk_src_mpllsrc:
		return read_pll(clk, 0x132020);
	case nv_clk_src_mpll:
		return read_pll(clk, 0x132000);
	case nv_clk_src_mdiv:
		return read_div(clk, 0, 0x137300, 0x137310);
	case nv_clk_src_mem:
		if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
			return nvkm_clk_read(&clk->base, nv_clk_src_mpll);
		return nvkm_clk_read(&clk->base, nv_clk_src_mdiv);

	case nv_clk_src_gpc:
		return read_clk(clk, 0x00);
	case nv_clk_src_rop:
		return read_clk(clk, 0x01);
	case nv_clk_src_hubk07:
		return read_clk(clk, 0x02);
	case nv_clk_src_hubk06:
		return read_clk(clk, 0x07);
	case nv_clk_src_hubk01:
		return read_clk(clk, 0x08);
	case nv_clk_src_copy:
		return read_clk(clk, 0x09);
	case nv_clk_src_pmu:
		return read_clk(clk, 0x0c);
	case nv_clk_src_vdec:
		return read_clk(clk, 0x0e);
	default:
		nvkm_error(subdev, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static u32
calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
{
	u32 div = min((ref * 2) / freq, (u32)65);
	if (div < 2)
		div = 2;

	*ddiv = div - 2;
	return (ref * 2) / div;
}

static u32
calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
{
	u32 sclk;

	/* use one of the fixed frequencies if possible */
	*ddiv = 0x00000000;
	switch (freq) {
	case  27000:
	case 108000:
		*dsrc = 0x00000000;
		if (freq == 108000)
			*dsrc |= 0x00030000;
		return freq;
	case 100000:
		*dsrc = 0x00000002;
		return freq;
	default:
		*dsrc = 0x00000003;
		break;
	}

	/* otherwise, calculate the closest divider */
	sclk = read_vco(clk, 0x137160 + (idx * 4));
	if (idx < 7)
		sclk = calc_div(clk, idx, sclk, freq, ddiv);
	return sclk;
}

static u32
calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
{
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_bios *bios = subdev->device->bios;
	struct nvbios_pll limits;
	int N, M, P, ret;

	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
	if (ret)
		return 0;

	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
	if (!limits.refclk)
		return 0;

	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
	if (ret <= 0)
		return 0;

	*coef = (P << 16) | (N << 8) | M;
	return ret;
}

static int
calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	u32 freq = cstate->domain[dom];
	u32 src0, div0, div1D, div1P = 0;
	u32 clk0, clk1 = 0;

	/* invalid clock domain */
	if (!freq)
		return 0;

	/* first possible path, using only dividers */
	clk0 = calc_src(clk, idx, freq, &src0, &div0);
	clk0 = calc_div(clk, idx, clk0, freq, &div1D);

	/* see if we can get any closer using PLLs */
	if (clk0 != freq && (0x00004387 & (1 << idx))) {
		if (idx <= 7)
			clk1 = calc_pll(clk, idx, freq, &info->coef);
		else
			clk1 = cstate->domain[nv_clk_src_hubk06];
		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
	}

	/* select the method which gets closest to target freq */
	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
		info->dsrc = src0;
		if (div0) {
			info->ddiv |= 0x80000000;
			info->ddiv |= div0 << 8;
			info->ddiv |= div0;
		}
		if (div1D) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1D;
		}
		info->ssel = info->coef = 0;
		info->freq = clk0;
	} else {
		if (div1P) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1P << 8;
		}
		info->ssel = (1 << idx);
		info->freq = clk1;
	}

	return 0;
}

static int
gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
{
	struct gf100_clk *clk = gf100_clk(base);
	int ret;

	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
	    (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) ||
	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) ||
	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static void
gf100_clk_prog_0(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (idx < 7 && !info->ssel) {
		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
	}
}

static void
gf100_clk_prog_1(struct gf100_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
	nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
			break;
	);
}

static void
gf100_clk_prog_2(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	const u32 addr = 0x137000 + (idx * 0x20);
	if (idx <= 7) {
		nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
		if (info->coef) {
			nvkm_wr32(device, addr + 0x04, info->coef);
			nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);

			/* Test PLL lock */
			nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
			nvkm_msec(device, 2000,
				if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
					break;
			);
			nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);

			/* Enable sync mode */
			nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
		}
	}
}

static void
gf100_clk_prog_3(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (info->ssel) {
		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
		nvkm_msec(device, 2000,
			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
			if (tmp == info->ssel)
				break;
		);
	}
}

static void
gf100_clk_prog_4(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
}

static int
gf100_clk_prog(struct nvkm_clk *base)
{
	struct gf100_clk *clk = gf100_clk(base);
	struct {
		void (*exec)(struct gf100_clk *, int);
	} stage[] = {
		{ gf100_clk_prog_0 }, /* div programming */
		{ gf100_clk_prog_1 }, /* select div mode */
		{ gf100_clk_prog_2 }, /* (maybe) program pll */
		{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
		{ gf100_clk_prog_4 }, /* final divider */
	};
	int i, j;

	for (i = 0; i < ARRAY_SIZE(stage); i++) {
		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
			if (!clk->eng[j].freq)
				continue;
			stage[i].exec(clk, j);
		}
	}

	return 0;
}

static void
gf100_clk_tidy(struct nvkm_clk *base)
{
	struct gf100_clk *clk = gf100_clk(base);
	memset(clk->eng, 0x00, sizeof(clk->eng));
}

static const struct nvkm_clk_func
gf100_clk = {
	.read = gf100_clk_read,
	.calc = gf100_clk_calc,
	.prog = gf100_clk_prog,
	.tidy = gf100_clk_tidy,
	.domains = {
		{ nv_clk_src_crystal, 0xff },
		{ nv_clk_src_href   , 0xff },
		{ nv_clk_src_hubk06 , 0x00 },
		{ nv_clk_src_hubk01 , 0x01 },
		{ nv_clk_src_copy   , 0x02 },
		{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
		{ nv_clk_src_rop    , 0x04 },
		{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
		{ nv_clk_src_vdec   , 0x06 },
		{ nv_clk_src_pmu    , 0x0a },
		{ nv_clk_src_hubk07 , 0x0b },
		{ nv_clk_src_max }
	}
};

int
gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
{
	struct gf100_clk *clk;

	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
		return -ENOMEM;
	*pclk = &clk->base;

	return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base);
}
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
6625f55c BS	24	#define gf100_clk(p) container_of((p), struct gf100_clk, base)
6625f55c BS	25	#include "priv.h"
7632b30e BS	26	#include "pll.h"
7632b30e BS	27
70790f4f BS	28	#include <subdev/bios.h>
70790f4f BS	29	#include <subdev/bios/pll.h>
7c856522	30	#include <subdev/timer.h>
70790f4f	31
7632b30e	32	struct gf100_clk_info {
7c856522 BS	33	u32 freq;
	34	u32 ssel;
	35	u32 mdiv;
	36	u32 dsrc;
	37	u32 ddiv;
	38	u32 coef;
	39	};
	40
3eca809b	41	struct gf100_clk {
7632b30e BS	42	struct nvkm_clk base;
7632b30e BS	43	struct gf100_clk_info eng[16];
7c856522 BS	44	};
7c856522 BS	45
3eca809b	46	static u32 read_div(struct gf100_clk *, int, u32, u32);
7c856522 BS	47
7c856522 BS	48	static u32
3eca809b	49	read_vco(struct gf100_clk *clk, u32 dsrc)
7c856522	50	{
822ad79f BS	51	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	52	u32 ssrc = nvkm_rd32(device, dsrc);
7c856522	53	if (!(ssrc & 0x00000100))
6625f55c BS	54	return nvkm_clk_read(&clk->base, nv_clk_src_sppll0);
6625f55c BS	55	return nvkm_clk_read(&clk->base, nv_clk_src_sppll1);
7c856522 BS	56	}
	57
	58	static u32
3eca809b	59	read_pll(struct gf100_clk *clk, u32 pll)
7c856522	60	{
822ad79f BS	61	struct nvkm_device *device = clk->base.subdev.device;
	62	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	63	u32 coef = nvkm_rd32(device, pll + 0x04);
7c856522 BS	64	u32 P = (coef & 0x003f0000) >> 16;
	65	u32 N = (coef & 0x0000ff00) >> 8;
	66	u32 M = (coef & 0x000000ff) >> 0;
	67	u32 sclk;
	68
	69	if (!(ctrl & 0x00000001))
	70	return 0;
	71
	72	switch (pll) {
	73	case 0x00e800:
	74	case 0x00e820:
822ad79f	75	sclk = device->crystal;
7c856522 BS	76	P = 1;
	77	break;
	78	case 0x132000:
6625f55c	79	sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
7c856522 BS	80	break;
7c856522 BS	81	case 0x132020:
6625f55c	82	sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
7c856522 BS	83	break;
	84	case 0x137000:
	85	case 0x137020:
	86	case 0x137040:
	87	case 0x1370e0:
3eca809b	88	sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
7c856522 BS	89	break;
	90	default:
	91	return 0;
	92	}
	93
	94	return sclk * N / M / P;
	95	}
	96
	97	static u32
3eca809b	98	read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
7c856522	99	{
822ad79f BS	100	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	101	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
f8fa2e4b	102	u32 sclk, sctl, sdiv = 2;
7c856522 BS	103
	104	switch (ssrc & 0x00000003) {
	105	case 0:
	106	if ((ssrc & 0x00030000) != 0x00030000)
822ad79f	107	return device->crystal;
7c856522 BS	108	return 108000;
	109	case 2:
	110	return 100000;
	111	case 3:
f8fa2e4b RS	112	sclk = read_vco(clk, dsrc + (doff * 4));
	113
	114	/* Memclk has doff of 0 despite its alt. location */
	115	if (doff <= 2) {
	116	sctl = nvkm_rd32(device, dctl + (doff * 4));
	117
	118	if (sctl & 0x80000000) {
	119	if (ssrc & 0x100)
	120	sctl >>= 8;
	121
	122	sdiv = (sctl & 0x3f) + 2;
	123	}
7c856522 BS	124	}
7c856522 BS	125
f8fa2e4b	126	return (sclk * 2) / sdiv;
7c856522 BS	127	default:
	128	return 0;
	129	}
	130	}
	131
	132	static u32
3eca809b	133	read_clk(struct gf100_clk *clk, int idx)
7c856522	134	{
822ad79f BS	135	struct nvkm_device *device = clk->base.subdev.device;
	136	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
	137	u32 ssel = nvkm_rd32(device, 0x137100);
7c856522 BS	138	u32 sclk, sdiv;
7c856522 BS	139
3eca809b BS	140	if (ssel & (1 << idx)) {
	141	if (idx < 7)
	142	sclk = read_pll(clk, 0x137000 + (idx * 0x20));
7c856522	143	else
3eca809b	144	sclk = read_pll(clk, 0x1370e0);
7c856522 BS	145	sdiv = ((sctl & 0x00003f00) >> 8) + 2;
7c856522 BS	146	} else {
3eca809b	147	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	148	sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	149	}
	150
	151	if (sctl & 0x80000000)
	152	return (sclk * 2) / sdiv;
	153
	154	return sclk;
	155	}
	156
	157	static int
6625f55c	158	gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
7c856522	159	{
6625f55c	160	struct gf100_clk *clk = gf100_clk(base);
b907649e BS	161	struct nvkm_subdev *subdev = &clk->base.subdev;
b907649e BS	162	struct nvkm_device *device = subdev->device;
7c856522 BS	163
	164	switch (src) {
	165	case nv_clk_src_crystal:
	166	return device->crystal;
	167	case nv_clk_src_href:
	168	return 100000;
	169	case nv_clk_src_sppll0:
3eca809b	170	return read_pll(clk, 0x00e800);
7c856522	171	case nv_clk_src_sppll1:
3eca809b	172	return read_pll(clk, 0x00e820);
7c856522 BS	173
7c856522 BS	174	case nv_clk_src_mpllsrcref:
3eca809b	175	return read_div(clk, 0, 0x137320, 0x137330);
7c856522	176	case nv_clk_src_mpllsrc:
3eca809b	177	return read_pll(clk, 0x132020);
7c856522	178	case nv_clk_src_mpll:
3eca809b	179	return read_pll(clk, 0x132000);
7c856522	180	case nv_clk_src_mdiv:
3eca809b	181	return read_div(clk, 0, 0x137300, 0x137310);
7c856522	182	case nv_clk_src_mem:
822ad79f	183	if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
6625f55c BS	184	return nvkm_clk_read(&clk->base, nv_clk_src_mpll);
6625f55c BS	185	return nvkm_clk_read(&clk->base, nv_clk_src_mdiv);
7c856522 BS	186
7c856522 BS	187	case nv_clk_src_gpc:
3eca809b	188	return read_clk(clk, 0x00);
7c856522	189	case nv_clk_src_rop:
3eca809b	190	return read_clk(clk, 0x01);
7c856522	191	case nv_clk_src_hubk07:
3eca809b	192	return read_clk(clk, 0x02);
7c856522	193	case nv_clk_src_hubk06:
3eca809b	194	return read_clk(clk, 0x07);
7c856522	195	case nv_clk_src_hubk01:
3eca809b	196	return read_clk(clk, 0x08);
7c856522	197	case nv_clk_src_copy:
3eca809b	198	return read_clk(clk, 0x09);
547dd271	199	case nv_clk_src_pmu:
3eca809b	200	return read_clk(clk, 0x0c);
7c856522	201	case nv_clk_src_vdec:
3eca809b	202	return read_clk(clk, 0x0e);
7c856522	203	default:
b907649e	204	nvkm_error(subdev, "invalid clock source %d\n", src);
7c856522 BS	205	return -EINVAL;
	206	}
	207	}
	208
	209	static u32
3eca809b	210	calc_div(struct gf100_clk clk, int idx, u32 ref, u32 freq, u32 ddiv)
7c856522 BS	211	{
	212	u32 div = min((ref * 2) / freq, (u32)65);
	213	if (div < 2)
	214	div = 2;
	215
	216	*ddiv = div - 2;
	217	return (ref * 2) / div;
	218	}
	219
	220	static u32
3eca809b	221	calc_src(struct gf100_clk clk, int idx, u32 freq, u32 dsrc, u32 *ddiv)
7c856522 BS	222	{
	223	u32 sclk;
	224
	225	/* use one of the fixed frequencies if possible */
	226	*ddiv = 0x00000000;
	227	switch (freq) {
	228	case 27000:
	229	case 108000:
	230	*dsrc = 0x00000000;
	231	if (freq == 108000)
	232	*dsrc \|= 0x00030000;
	233	return freq;
	234	case 100000:
	235	*dsrc = 0x00000002;
	236	return freq;
	237	default:
	238	*dsrc = 0x00000003;
	239	break;
	240	}
	241
	242	/* otherwise, calculate the closest divider */
3eca809b BS	243	sclk = read_vco(clk, 0x137160 + (idx * 4));
	244	if (idx < 7)
	245	sclk = calc_div(clk, idx, sclk, freq, ddiv);
7c856522 BS	246	return sclk;
	247	}
	248
	249	static u32
3eca809b	250	calc_pll(struct gf100_clk clk, int idx, u32 freq, u32 coef)
7c856522	251	{
46484438 BS	252	struct nvkm_subdev *subdev = &clk->base.subdev;
46484438 BS	253	struct nvkm_bios *bios = subdev->device->bios;
7c856522 BS	254	struct nvbios_pll limits;
	255	int N, M, P, ret;
	256
3eca809b	257	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
7c856522 BS	258	if (ret)
	259	return 0;
	260
3eca809b	261	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
7c856522 BS	262	if (!limits.refclk)
	263	return 0;
	264
46484438	265	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
7c856522 BS	266	if (ret <= 0)
	267	return 0;
	268
	269	*coef = (P << 16) \| (N << 8) \| M;
	270	return ret;
	271	}
	272
	273	static int
3eca809b	274	calc_clk(struct gf100_clk clk, struct nvkm_cstate cstate, int idx, int dom)
7c856522	275	{
3eca809b	276	struct gf100_clk_info *info = &clk->eng[idx];
7c856522 BS	277	u32 freq = cstate->domain[dom];
	278	u32 src0, div0, div1D, div1P = 0;
	279	u32 clk0, clk1 = 0;
	280
	281	/* invalid clock domain */
	282	if (!freq)
	283	return 0;
	284
	285	/* first possible path, using only dividers */
3eca809b BS	286	clk0 = calc_src(clk, idx, freq, &src0, &div0);
3eca809b BS	287	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
7c856522 BS	288
7c856522 BS	289	/* see if we can get any closer using PLLs */
3eca809b BS	290	if (clk0 != freq && (0x00004387 & (1 << idx))) {
	291	if (idx <= 7)
	292	clk1 = calc_pll(clk, idx, freq, &info->coef);
7c856522 BS	293	else
7c856522 BS	294	clk1 = cstate->domain[nv_clk_src_hubk06];
3eca809b	295	clk1 = calc_div(clk, idx, clk1, freq, &div1P);
7c856522 BS	296	}
	297
	298	/* select the method which gets closest to target freq */
	299	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
	300	info->dsrc = src0;
	301	if (div0) {
	302	info->ddiv \|= 0x80000000;
	303	info->ddiv \|= div0 << 8;
	304	info->ddiv \|= div0;
	305	}
	306	if (div1D) {
	307	info->mdiv \|= 0x80000000;
	308	info->mdiv \|= div1D;
	309	}
	310	info->ssel = info->coef = 0;
	311	info->freq = clk0;
	312	} else {
	313	if (div1P) {
	314	info->mdiv \|= 0x80000000;
	315	info->mdiv \|= div1P << 8;
	316	}
3eca809b	317	info->ssel = (1 << idx);
7c856522 BS	318	info->freq = clk1;
	319	}
	320
	321	return 0;
	322	}
	323
	324	static int
6625f55c	325	gf100_clk_calc(struct nvkm_clk base, struct nvkm_cstate cstate)
7c856522	326	{
6625f55c	327	struct gf100_clk *clk = gf100_clk(base);
7c856522 BS	328	int ret;
7c856522 BS	329
3eca809b BS	330	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) \|\|
	331	(ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) \|\|
	332	(ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) \|\|
	333	(ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) \|\|
	334	(ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) \|\|
	335	(ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) \|\|
547dd271	336	(ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) \|\|
3eca809b	337	(ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
7c856522 BS	338	return ret;
	339
	340	return 0;
	341	}
	342
	343	static void
3eca809b	344	gf100_clk_prog_0(struct gf100_clk *clk, int idx)
7c856522	345	{
3eca809b	346	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	347	struct nvkm_device *device = clk->base.subdev.device;
3eca809b	348	if (idx < 7 && !info->ssel) {
822ad79f BS	349	nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
822ad79f BS	350	nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
7c856522 BS	351	}
	352	}
	353
	354	static void
3eca809b	355	gf100_clk_prog_1(struct gf100_clk *clk, int idx)
7c856522	356	{
822ad79f BS	357	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	358	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
6979c630 BS	359	nvkm_msec(device, 2000,
	360	if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
	361	break;
	362	);
7c856522 BS	363	}
	364
	365	static void
3eca809b	366	gf100_clk_prog_2(struct gf100_clk *clk, int idx)
7c856522	367	{
3eca809b	368	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	369	struct nvkm_device *device = clk->base.subdev.device;
3eca809b BS	370	const u32 addr = 0x137000 + (idx * 0x20);
3eca809b BS	371	if (idx <= 7) {
822ad79f BS	372	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
822ad79f BS	373	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
7c856522	374	if (info->coef) {
822ad79f BS	375	nvkm_wr32(device, addr + 0x04, info->coef);
822ad79f BS	376	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
0f7fbb99 RS	377
	378	/* Test PLL lock */
	379	nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
6979c630 BS	380	nvkm_msec(device, 2000,
	381	if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
	382	break;
	383	);
0f7fbb99 RS	384	nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
	385
	386	/* Enable sync mode */
	387	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
7c856522 BS	388	}
	389	}
	390	}
	391
	392	static void
3eca809b	393	gf100_clk_prog_3(struct gf100_clk *clk, int idx)
7c856522	394	{
3eca809b	395	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	396	struct nvkm_device *device = clk->base.subdev.device;
7c856522	397	if (info->ssel) {
822ad79f	398	nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
6979c630 BS	399	nvkm_msec(device, 2000,
	400	u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
	401	if (tmp == info->ssel)
	402	break;
	403	);
7c856522 BS	404	}
	405	}
	406
	407	static void
3eca809b	408	gf100_clk_prog_4(struct gf100_clk *clk, int idx)
7c856522	409	{
3eca809b	410	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f BS	411	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	412	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
7c856522 BS	413	}
	414
	415	static int
6625f55c	416	gf100_clk_prog(struct nvkm_clk *base)
7c856522	417	{
6625f55c	418	struct gf100_clk *clk = gf100_clk(base);
7c856522	419	struct {
3eca809b	420	void (exec)(struct gf100_clk , int);
7c856522	421	} stage[] = {
7632b30e BS	422	{ gf100_clk_prog_0 }, /* div programming */
	423	{ gf100_clk_prog_1 }, /* select div mode */
	424	{ gf100_clk_prog_2 }, /* (maybe) program pll */
	425	{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
	426	{ gf100_clk_prog_4 }, /* final divider */
7c856522 BS	427	};
	428	int i, j;
	429
	430	for (i = 0; i < ARRAY_SIZE(stage); i++) {
3eca809b BS	431	for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
3eca809b BS	432	if (!clk->eng[j].freq)
7c856522	433	continue;
3eca809b	434	stage[i].exec(clk, j);
7c856522 BS	435	}
	436	}
	437
	438	return 0;
	439	}
	440
	441	static void
6625f55c	442	gf100_clk_tidy(struct nvkm_clk *base)
7c856522	443	{
6625f55c	444	struct gf100_clk *clk = gf100_clk(base);
3eca809b	445	memset(clk->eng, 0x00, sizeof(clk->eng));
7c856522 BS	446	}
7c856522 BS	447
6625f55c BS	448	static const struct nvkm_clk_func
	449	gf100_clk = {
	450	.read = gf100_clk_read,
	451	.calc = gf100_clk_calc,
	452	.prog = gf100_clk_prog,
	453	.tidy = gf100_clk_tidy,
	454	.domains = {
	455	{ nv_clk_src_crystal, 0xff },
	456	{ nv_clk_src_href , 0xff },
	457	{ nv_clk_src_hubk06 , 0x00 },
	458	{ nv_clk_src_hubk01 , 0x01 },
	459	{ nv_clk_src_copy , 0x02 },
	460	{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
	461	{ nv_clk_src_rop , 0x04 },
	462	{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
	463	{ nv_clk_src_vdec , 0x06 },
547dd271	464	{ nv_clk_src_pmu , 0x0a },
6625f55c BS	465	{ nv_clk_src_hubk07 , 0x0b },
	466	{ nv_clk_src_max }
	467	}
8aceb7de BS	468	};
8aceb7de BS	469
6625f55c BS	470	int
6625f55c BS	471	gf100_clk_new(struct nvkm_device device, int index, struct nvkm_clk *pclk)
8aceb7de	472	{
3eca809b	473	struct gf100_clk *clk;
8aceb7de	474
6625f55c BS	475	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
	476	return -ENOMEM;
	477	*pclk = &clk->base;
8aceb7de	478
6625f55c	479	return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base);
8aceb7de	480	}