[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include <subdev/clk.h>
#include "pll.h"

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

struct gf100_clk_info {
	u32 freq;
	u32 ssel;
	u32 mdiv;
	u32 dsrc;
	u32 ddiv;
	u32 coef;
};

struct gf100_clk_priv {
	struct nvkm_clk base;
	struct gf100_clk_info eng[16];
};

static u32 read_div(struct gf100_clk_priv *, int, u32, u32);

static u32
read_vco(struct gf100_clk_priv *priv, u32 dsrc)
{
	struct nvkm_clk *clk = &priv->base;
	u32 ssrc = nv_rd32(priv, dsrc);
	if (!(ssrc & 0x00000100))
		return clk->read(clk, nv_clk_src_sppll0);
	return clk->read(clk, nv_clk_src_sppll1);
}

static u32
read_pll(struct gf100_clk_priv *priv, u32 pll)
{
	struct nvkm_clk *clk = &priv->base;
	u32 ctrl = nv_rd32(priv, pll + 0x00);
	u32 coef = nv_rd32(priv, pll + 0x04);
	u32 P = (coef & 0x003f0000) >> 16;
	u32 N = (coef & 0x0000ff00) >> 8;
	u32 M = (coef & 0x000000ff) >> 0;
	u32 sclk;

	if (!(ctrl & 0x00000001))
		return 0;

	switch (pll) {
	case 0x00e800:
	case 0x00e820:
		sclk = nv_device(priv)->crystal;
		P = 1;
		break;
	case 0x132000:
		sclk = clk->read(clk, nv_clk_src_mpllsrc);
		break;
	case 0x132020:
		sclk = clk->read(clk, nv_clk_src_mpllsrcref);
		break;
	case 0x137000:
	case 0x137020:
	case 0x137040:
	case 0x1370e0:
		sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
		break;
	default:
		return 0;
	}

	return sclk * N / M / P;
}

static u32
read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
	u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
	u32 sctl = nv_rd32(priv, dctl + (doff * 4));

	switch (ssrc & 0x00000003) {
	case 0:
		if ((ssrc & 0x00030000) != 0x00030000)
			return nv_device(priv)->crystal;
		return 108000;
	case 2:
		return 100000;
	case 3:
		if (sctl & 0x80000000) {
			u32 sclk = read_vco(priv, dsrc + (doff * 4));
			u32 sdiv = (sctl & 0x0000003f) + 2;
			return (sclk * 2) / sdiv;
		}

		return read_vco(priv, dsrc + (doff * 4));
	default:
		return 0;
	}
}

static u32
read_clk(struct gf100_clk_priv *priv, int clk)
{
	u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
	u32 ssel = nv_rd32(priv, 0x137100);
	u32 sclk, sdiv;

	if (ssel & (1 << clk)) {
		if (clk < 7)
			sclk = read_pll(priv, 0x137000 + (clk * 0x20));
		else
			sclk = read_pll(priv, 0x1370e0);
		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	} else {
		sclk = read_div(priv, clk, 0x137160, 0x1371d0);
		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	}

	if (sctl & 0x80000000)
		return (sclk * 2) / sdiv;

	return sclk;
}

static int
gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
	struct nvkm_device *device = nv_device(clk);
	struct gf100_clk_priv *priv = (void *)clk;

	switch (src) {
	case nv_clk_src_crystal:
		return device->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_sppll0:
		return read_pll(priv, 0x00e800);
	case nv_clk_src_sppll1:
		return read_pll(priv, 0x00e820);

	case nv_clk_src_mpllsrcref:
		return read_div(priv, 0, 0x137320, 0x137330);
	case nv_clk_src_mpllsrc:
		return read_pll(priv, 0x132020);
	case nv_clk_src_mpll:
		return read_pll(priv, 0x132000);
	case nv_clk_src_mdiv:
		return read_div(priv, 0, 0x137300, 0x137310);
	case nv_clk_src_mem:
		if (nv_rd32(priv, 0x1373f0) & 0x00000002)
			return clk->read(clk, nv_clk_src_mpll);
		return clk->read(clk, nv_clk_src_mdiv);

	case nv_clk_src_gpc:
		return read_clk(priv, 0x00);
	case nv_clk_src_rop:
		return read_clk(priv, 0x01);
	case nv_clk_src_hubk07:
		return read_clk(priv, 0x02);
	case nv_clk_src_hubk06:
		return read_clk(priv, 0x07);
	case nv_clk_src_hubk01:
		return read_clk(priv, 0x08);
	case nv_clk_src_copy:
		return read_clk(priv, 0x09);
	case nv_clk_src_daemon:
		return read_clk(priv, 0x0c);
	case nv_clk_src_vdec:
		return read_clk(priv, 0x0e);
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static u32
calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
	u32 div = min((ref * 2) / freq, (u32)65);
	if (div < 2)
		div = 2;

	*ddiv = div - 2;
	return (ref * 2) / div;
}

static u32
calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
	u32 sclk;

	/* use one of the fixed frequencies if possible */
	*ddiv = 0x00000000;
	switch (freq) {
	case  27000:
	case 108000:
		*dsrc = 0x00000000;
		if (freq == 108000)
			*dsrc |= 0x00030000;
		return freq;
	case 100000:
		*dsrc = 0x00000002;
		return freq;
	default:
		*dsrc = 0x00000003;
		break;
	}

	/* otherwise, calculate the closest divider */
	sclk = read_vco(priv, 0x137160 + (clk * 4));
	if (clk < 7)
		sclk = calc_div(priv, clk, sclk, freq, ddiv);
	return sclk;
}

static u32
calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
	struct nvkm_bios *bios = nvkm_bios(priv);
	struct nvbios_pll limits;
	int N, M, P, ret;

	ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
	if (ret)
		return 0;

	limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
	if (!limits.refclk)
		return 0;

	ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
	if (ret <= 0)
		return 0;

	*coef = (P << 16) | (N << 8) | M;
	return ret;
}

static int
calc_clk(struct gf100_clk_priv *priv,
	 struct nvkm_cstate *cstate, int clk, int dom)
{
	struct gf100_clk_info *info = &priv->eng[clk];
	u32 freq = cstate->domain[dom];
	u32 src0, div0, div1D, div1P = 0;
	u32 clk0, clk1 = 0;

	/* invalid clock domain */
	if (!freq)
		return 0;

	/* first possible path, using only dividers */
	clk0 = calc_src(priv, clk, freq, &src0, &div0);
	clk0 = calc_div(priv, clk, clk0, freq, &div1D);

	/* see if we can get any closer using PLLs */
	if (clk0 != freq && (0x00004387 & (1 << clk))) {
		if (clk <= 7)
			clk1 = calc_pll(priv, clk, freq, &info->coef);
		else
			clk1 = cstate->domain[nv_clk_src_hubk06];
		clk1 = calc_div(priv, clk, clk1, freq, &div1P);
	}

	/* select the method which gets closest to target freq */
	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
		info->dsrc = src0;
		if (div0) {
			info->ddiv |= 0x80000000;
			info->ddiv |= div0 << 8;
			info->ddiv |= div0;
		}
		if (div1D) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1D;
		}
		info->ssel = info->coef = 0;
		info->freq = clk0;
	} else {
		if (div1P) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1P << 8;
		}
		info->ssel = (1 << clk);
		info->freq = clk1;
	}

	return 0;
}

static int
gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
	struct gf100_clk_priv *priv = (void *)clk;
	int ret;

	if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
	    (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
	    (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
	    (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
	    (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
	    (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
	    (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
	    (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static void
gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk)
{
	struct gf100_clk_info *info = &priv->eng[clk];
	if (clk < 7 && !info->ssel) {
		nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
		nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
	}
}

static void
gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk)
{
	nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
	nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}

static void
gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk)
{
	struct gf100_clk_info *info = &priv->eng[clk];
	const u32 addr = 0x137000 + (clk * 0x20);
	if (clk <= 7) {
		nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
		nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
		if (info->coef) {
			nv_wr32(priv, addr + 0x04, info->coef);
			nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
			nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
			nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
		}
	}
}

static void
gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk)
{
	struct gf100_clk_info *info = &priv->eng[clk];
	if (info->ssel) {
		nv_mask(priv, 0x137100, (1 << clk), info->ssel);
		nv_wait(priv, 0x137100, (1 << clk), info->ssel);
	}
}

static void
gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk)
{
	struct gf100_clk_info *info = &priv->eng[clk];
	nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}

static int
gf100_clk_prog(struct nvkm_clk *clk)
{
	struct gf100_clk_priv *priv = (void *)clk;
	struct {
		void (*exec)(struct gf100_clk_priv *, int);
	} stage[] = {
		{ gf100_clk_prog_0 }, /* div programming */
		{ gf100_clk_prog_1 }, /* select div mode */
		{ gf100_clk_prog_2 }, /* (maybe) program pll */
		{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
		{ gf100_clk_prog_4 }, /* final divider */
	};
	int i, j;

	for (i = 0; i < ARRAY_SIZE(stage); i++) {
		for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
			if (!priv->eng[j].freq)
				continue;
			stage[i].exec(priv, j);
		}
	}

	return 0;
}

static void
gf100_clk_tidy(struct nvkm_clk *clk)
{
	struct gf100_clk_priv *priv = (void *)clk;
	memset(priv->eng, 0x00, sizeof(priv->eng));
}

static struct nvkm_domain
gf100_domain[] = {
	{ nv_clk_src_crystal, 0xff },
	{ nv_clk_src_href   , 0xff },
	{ nv_clk_src_hubk06 , 0x00 },
	{ nv_clk_src_hubk01 , 0x01 },
	{ nv_clk_src_copy   , 0x02 },
	{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
	{ nv_clk_src_rop    , 0x04 },
	{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
	{ nv_clk_src_vdec   , 0x06 },
	{ nv_clk_src_daemon , 0x0a },
	{ nv_clk_src_hubk07 , 0x0b },
	{ nv_clk_src_max }
};

static int
gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	       struct nvkm_oclass *oclass, void *data, u32 size,
	       struct nvkm_object **pobject)
{
	struct gf100_clk_priv *priv;
	int ret;

	ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
			      NULL, 0, false, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.read = gf100_clk_read;
	priv->base.calc = gf100_clk_calc;
	priv->base.prog = gf100_clk_prog;
	priv->base.tidy = gf100_clk_tidy;
	return 0;
}

struct nvkm_oclass
gf100_clk_oclass = {
	.handle = NV_SUBDEV(CLK, 0xc0),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = gf100_clk_ctor,
		.dtor = _nvkm_clk_dtor,
		.init = _nvkm_clk_init,
		.fini = _nvkm_clk_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
f3867f43	24	#include <subdev/clk.h>
7632b30e BS	25	#include "pll.h"
7632b30e BS	26
70790f4f BS	27	#include <subdev/bios.h>
70790f4f BS	28	#include <subdev/bios/pll.h>
7c856522	29	#include <subdev/timer.h>
70790f4f	30
7632b30e	31	struct gf100_clk_info {
7c856522 BS	32	u32 freq;
	33	u32 ssel;
	34	u32 mdiv;
	35	u32 dsrc;
	36	u32 ddiv;
	37	u32 coef;
	38	};
	39
7632b30e BS	40	struct gf100_clk_priv {
	41	struct nvkm_clk base;
	42	struct gf100_clk_info eng[16];
7c856522 BS	43	};
7c856522 BS	44
7632b30e	45	static u32 read_div(struct gf100_clk_priv *, int, u32, u32);
7c856522 BS	46
7c856522 BS	47	static u32
7632b30e	48	read_vco(struct gf100_clk_priv *priv, u32 dsrc)
7c856522	49	{
7632b30e	50	struct nvkm_clk *clk = &priv->base;
7c856522 BS	51	u32 ssrc = nv_rd32(priv, dsrc);
	52	if (!(ssrc & 0x00000100))
	53	return clk->read(clk, nv_clk_src_sppll0);
	54	return clk->read(clk, nv_clk_src_sppll1);
	55	}
	56
	57	static u32
7632b30e	58	read_pll(struct gf100_clk_priv *priv, u32 pll)
7c856522	59	{
7632b30e	60	struct nvkm_clk *clk = &priv->base;
7c856522 BS	61	u32 ctrl = nv_rd32(priv, pll + 0x00);
	62	u32 coef = nv_rd32(priv, pll + 0x04);
	63	u32 P = (coef & 0x003f0000) >> 16;
	64	u32 N = (coef & 0x0000ff00) >> 8;
	65	u32 M = (coef & 0x000000ff) >> 0;
	66	u32 sclk;
	67
	68	if (!(ctrl & 0x00000001))
	69	return 0;
	70
	71	switch (pll) {
	72	case 0x00e800:
	73	case 0x00e820:
	74	sclk = nv_device(priv)->crystal;
	75	P = 1;
	76	break;
	77	case 0x132000:
	78	sclk = clk->read(clk, nv_clk_src_mpllsrc);
	79	break;
	80	case 0x132020:
	81	sclk = clk->read(clk, nv_clk_src_mpllsrcref);
	82	break;
	83	case 0x137000:
	84	case 0x137020:
	85	case 0x137040:
	86	case 0x1370e0:
	87	sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
	88	break;
	89	default:
	90	return 0;
	91	}
	92
	93	return sclk * N / M / P;
	94	}
	95
	96	static u32
7632b30e	97	read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
7c856522 BS	98	{
	99	u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
	100	u32 sctl = nv_rd32(priv, dctl + (doff * 4));
	101
	102	switch (ssrc & 0x00000003) {
	103	case 0:
	104	if ((ssrc & 0x00030000) != 0x00030000)
	105	return nv_device(priv)->crystal;
	106	return 108000;
	107	case 2:
	108	return 100000;
	109	case 3:
	110	if (sctl & 0x80000000) {
	111	u32 sclk = read_vco(priv, dsrc + (doff * 4));
	112	u32 sdiv = (sctl & 0x0000003f) + 2;
	113	return (sclk * 2) / sdiv;
	114	}
	115
	116	return read_vco(priv, dsrc + (doff * 4));
	117	default:
	118	return 0;
	119	}
	120	}
	121
	122	static u32
7632b30e	123	read_clk(struct gf100_clk_priv *priv, int clk)
7c856522 BS	124	{
	125	u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
	126	u32 ssel = nv_rd32(priv, 0x137100);
	127	u32 sclk, sdiv;
	128
	129	if (ssel & (1 << clk)) {
	130	if (clk < 7)
	131	sclk = read_pll(priv, 0x137000 + (clk * 0x20));
	132	else
	133	sclk = read_pll(priv, 0x1370e0);
	134	sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	135	} else {
	136	sclk = read_div(priv, clk, 0x137160, 0x1371d0);
	137	sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	138	}
	139
	140	if (sctl & 0x80000000)
	141	return (sclk * 2) / sdiv;
	142
	143	return sclk;
	144	}
	145
	146	static int
7632b30e	147	gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
7c856522	148	{
7632b30e BS	149	struct nvkm_device *device = nv_device(clk);
7632b30e BS	150	struct gf100_clk_priv priv = (void )clk;
7c856522 BS	151
	152	switch (src) {
	153	case nv_clk_src_crystal:
	154	return device->crystal;
	155	case nv_clk_src_href:
	156	return 100000;
	157	case nv_clk_src_sppll0:
	158	return read_pll(priv, 0x00e800);
	159	case nv_clk_src_sppll1:
	160	return read_pll(priv, 0x00e820);
	161
	162	case nv_clk_src_mpllsrcref:
	163	return read_div(priv, 0, 0x137320, 0x137330);
	164	case nv_clk_src_mpllsrc:
	165	return read_pll(priv, 0x132020);
	166	case nv_clk_src_mpll:
	167	return read_pll(priv, 0x132000);
	168	case nv_clk_src_mdiv:
	169	return read_div(priv, 0, 0x137300, 0x137310);
	170	case nv_clk_src_mem:
	171	if (nv_rd32(priv, 0x1373f0) & 0x00000002)
	172	return clk->read(clk, nv_clk_src_mpll);
	173	return clk->read(clk, nv_clk_src_mdiv);
	174
	175	case nv_clk_src_gpc:
	176	return read_clk(priv, 0x00);
	177	case nv_clk_src_rop:
	178	return read_clk(priv, 0x01);
	179	case nv_clk_src_hubk07:
	180	return read_clk(priv, 0x02);
	181	case nv_clk_src_hubk06:
	182	return read_clk(priv, 0x07);
	183	case nv_clk_src_hubk01:
	184	return read_clk(priv, 0x08);
	185	case nv_clk_src_copy:
	186	return read_clk(priv, 0x09);
	187	case nv_clk_src_daemon:
	188	return read_clk(priv, 0x0c);
	189	case nv_clk_src_vdec:
	190	return read_clk(priv, 0x0e);
	191	default:
	192	nv_error(clk, "invalid clock source %d\n", src);
	193	return -EINVAL;
	194	}
	195	}
	196
	197	static u32
7632b30e	198	calc_div(struct gf100_clk_priv priv, int clk, u32 ref, u32 freq, u32 ddiv)
7c856522 BS	199	{
	200	u32 div = min((ref * 2) / freq, (u32)65);
	201	if (div < 2)
	202	div = 2;
	203
	204	*ddiv = div - 2;
	205	return (ref * 2) / div;
	206	}
	207
	208	static u32
7632b30e	209	calc_src(struct gf100_clk_priv priv, int clk, u32 freq, u32 dsrc, u32 *ddiv)
7c856522 BS	210	{
	211	u32 sclk;
	212
	213	/* use one of the fixed frequencies if possible */
	214	*ddiv = 0x00000000;
	215	switch (freq) {
	216	case 27000:
	217	case 108000:
	218	*dsrc = 0x00000000;
	219	if (freq == 108000)
	220	*dsrc \|= 0x00030000;
	221	return freq;
	222	case 100000:
	223	*dsrc = 0x00000002;
	224	return freq;
	225	default:
	226	*dsrc = 0x00000003;
	227	break;
	228	}
	229
	230	/* otherwise, calculate the closest divider */
	231	sclk = read_vco(priv, 0x137160 + (clk * 4));
	232	if (clk < 7)
	233	sclk = calc_div(priv, clk, sclk, freq, ddiv);
	234	return sclk;
	235	}
	236
	237	static u32
7632b30e	238	calc_pll(struct gf100_clk_priv priv, int clk, u32 freq, u32 coef)
7c856522	239	{
7632b30e	240	struct nvkm_bios *bios = nvkm_bios(priv);
7c856522 BS	241	struct nvbios_pll limits;
	242	int N, M, P, ret;
	243
	244	ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
	245	if (ret)
	246	return 0;
	247
	248	limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
	249	if (!limits.refclk)
	250	return 0;
	251
7632b30e	252	ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
7c856522 BS	253	if (ret <= 0)
	254	return 0;
	255
	256	*coef = (P << 16) \| (N << 8) \| M;
	257	return ret;
	258	}
	259
	260	static int
7632b30e BS	261	calc_clk(struct gf100_clk_priv *priv,
7632b30e BS	262	struct nvkm_cstate *cstate, int clk, int dom)
7c856522	263	{
7632b30e	264	struct gf100_clk_info *info = &priv->eng[clk];
7c856522 BS	265	u32 freq = cstate->domain[dom];
	266	u32 src0, div0, div1D, div1P = 0;
	267	u32 clk0, clk1 = 0;
	268
	269	/* invalid clock domain */
	270	if (!freq)
	271	return 0;
	272
	273	/* first possible path, using only dividers */
	274	clk0 = calc_src(priv, clk, freq, &src0, &div0);
	275	clk0 = calc_div(priv, clk, clk0, freq, &div1D);
	276
	277	/* see if we can get any closer using PLLs */
	278	if (clk0 != freq && (0x00004387 & (1 << clk))) {
	279	if (clk <= 7)
	280	clk1 = calc_pll(priv, clk, freq, &info->coef);
	281	else
	282	clk1 = cstate->domain[nv_clk_src_hubk06];
	283	clk1 = calc_div(priv, clk, clk1, freq, &div1P);
	284	}
	285
	286	/* select the method which gets closest to target freq */
	287	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
	288	info->dsrc = src0;
	289	if (div0) {
	290	info->ddiv \|= 0x80000000;
	291	info->ddiv \|= div0 << 8;
	292	info->ddiv \|= div0;
	293	}
	294	if (div1D) {
	295	info->mdiv \|= 0x80000000;
	296	info->mdiv \|= div1D;
	297	}
	298	info->ssel = info->coef = 0;
	299	info->freq = clk0;
	300	} else {
	301	if (div1P) {
	302	info->mdiv \|= 0x80000000;
	303	info->mdiv \|= div1P << 8;
	304	}
	305	info->ssel = (1 << clk);
	306	info->freq = clk1;
	307	}
	308
	309	return 0;
	310	}
	311
	312	static int
7632b30e	313	gf100_clk_calc(struct nvkm_clk clk, struct nvkm_cstate cstate)
7c856522	314	{
7632b30e	315	struct gf100_clk_priv priv = (void )clk;
7c856522 BS	316	int ret;
	317
	318	if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) \|\|
	319	(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) \|\|
	320	(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) \|\|
	321	(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) \|\|
	322	(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) \|\|
	323	(ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) \|\|
	324	(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) \|\|
	325	(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
	326	return ret;
	327
	328	return 0;
	329	}
	330
	331	static void
7632b30e	332	gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk)
7c856522	333	{
7632b30e	334	struct gf100_clk_info *info = &priv->eng[clk];
7c856522 BS	335	if (clk < 7 && !info->ssel) {
	336	nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
	337	nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
	338	}
	339	}
	340
	341	static void
7632b30e	342	gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk)
7c856522 BS	343	{
	344	nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
	345	nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
	346	}
	347
	348	static void
7632b30e	349	gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk)
7c856522	350	{
7632b30e	351	struct gf100_clk_info *info = &priv->eng[clk];
7c856522 BS	352	const u32 addr = 0x137000 + (clk * 0x20);
	353	if (clk <= 7) {
	354	nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
	355	nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
	356	if (info->coef) {
	357	nv_wr32(priv, addr + 0x04, info->coef);
	358	nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
	359	nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
	360	nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
	361	}
	362	}
	363	}
	364
	365	static void
7632b30e	366	gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk)
7c856522	367	{
7632b30e	368	struct gf100_clk_info *info = &priv->eng[clk];
7c856522 BS	369	if (info->ssel) {
	370	nv_mask(priv, 0x137100, (1 << clk), info->ssel);
	371	nv_wait(priv, 0x137100, (1 << clk), info->ssel);
	372	}
	373	}
	374
	375	static void
7632b30e	376	gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk)
7c856522	377	{
7632b30e	378	struct gf100_clk_info *info = &priv->eng[clk];
7c856522 BS	379	nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
	380	}
	381
	382	static int
7632b30e	383	gf100_clk_prog(struct nvkm_clk *clk)
7c856522	384	{
7632b30e	385	struct gf100_clk_priv priv = (void )clk;
7c856522	386	struct {
7632b30e	387	void (exec)(struct gf100_clk_priv , int);
7c856522	388	} stage[] = {
7632b30e BS	389	{ gf100_clk_prog_0 }, /* div programming */
	390	{ gf100_clk_prog_1 }, /* select div mode */
	391	{ gf100_clk_prog_2 }, /* (maybe) program pll */
	392	{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
	393	{ gf100_clk_prog_4 }, /* final divider */
7c856522 BS	394	};
	395	int i, j;
	396
	397	for (i = 0; i < ARRAY_SIZE(stage); i++) {
	398	for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
	399	if (!priv->eng[j].freq)
	400	continue;
	401	stage[i].exec(priv, j);
	402	}
	403	}
	404
	405	return 0;
	406	}
	407
	408	static void
7632b30e	409	gf100_clk_tidy(struct nvkm_clk *clk)
7c856522	410	{
7632b30e	411	struct gf100_clk_priv priv = (void )clk;
7c856522 BS	412	memset(priv->eng, 0x00, sizeof(priv->eng));
	413	}
	414
7632b30e BS	415	static struct nvkm_domain
7632b30e BS	416	gf100_domain[] = {
7c856522 BS	417	{ nv_clk_src_crystal, 0xff },
	418	{ nv_clk_src_href , 0xff },
	419	{ nv_clk_src_hubk06 , 0x00 },
	420	{ nv_clk_src_hubk01 , 0x01 },
	421	{ nv_clk_src_copy , 0x02 },
	422	{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
	423	{ nv_clk_src_rop , 0x04 },
	424	{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
	425	{ nv_clk_src_vdec , 0x06 },
	426	{ nv_clk_src_daemon , 0x0a },
	427	{ nv_clk_src_hubk07 , 0x0b },
	428	{ nv_clk_src_max }
8aceb7de BS	429	};
8aceb7de BS	430
8aceb7de	431	static int
7632b30e BS	432	gf100_clk_ctor(struct nvkm_object parent, struct nvkm_object engine,
	433	struct nvkm_oclass oclass, void data, u32 size,
	434	struct nvkm_object **pobject)
8aceb7de	435	{
7632b30e	436	struct gf100_clk_priv *priv;
8aceb7de BS	437	int ret;
8aceb7de BS	438
7632b30e BS	439	ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
7632b30e BS	440	NULL, 0, false, &priv);
8aceb7de BS	441	*pobject = nv_object(priv);
	442	if (ret)
	443	return ret;
	444
7632b30e BS	445	priv->base.read = gf100_clk_read;
	446	priv->base.calc = gf100_clk_calc;
	447	priv->base.prog = gf100_clk_prog;
	448	priv->base.tidy = gf100_clk_tidy;
8aceb7de BS	449	return 0;
	450	}
	451
7632b30e BS	452	struct nvkm_oclass
7632b30e BS	453	gf100_clk_oclass = {
f3867f43	454	.handle = NV_SUBDEV(CLK, 0xc0),
7632b30e BS	455	.ofuncs = &(struct nvkm_ofuncs) {
	456	.ctor = gf100_clk_ctor,
	457	.dtor = _nvkm_clk_dtor,
	458	.init = _nvkm_clk_init,
	459	.fini = _nvkm_clk_fini,
8aceb7de BS	460	},
8aceb7de BS	461	};