[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include <subdev/clk.h>
#include "pll.h"

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

struct gf100_clk_info {
	u32 freq;
	u32 ssel;
	u32 mdiv;
	u32 dsrc;
	u32 ddiv;
	u32 coef;
};

struct gf100_clk {
	struct nvkm_clk base;
	struct gf100_clk_info eng[16];
};

static u32 read_div(struct gf100_clk *, int, u32, u32);

static u32
read_vco(struct gf100_clk *clk, u32 dsrc)
{
	u32 ssrc = nv_rd32(clk, dsrc);
	if (!(ssrc & 0x00000100))
		return clk->base.read(&clk->base, nv_clk_src_sppll0);
	return clk->base.read(&clk->base, nv_clk_src_sppll1);
}

static u32
read_pll(struct gf100_clk *clk, u32 pll)
{
	u32 ctrl = nv_rd32(clk, pll + 0x00);
	u32 coef = nv_rd32(clk, pll + 0x04);
	u32 P = (coef & 0x003f0000) >> 16;
	u32 N = (coef & 0x0000ff00) >> 8;
	u32 M = (coef & 0x000000ff) >> 0;
	u32 sclk;

	if (!(ctrl & 0x00000001))
		return 0;

	switch (pll) {
	case 0x00e800:
	case 0x00e820:
		sclk = nv_device(clk)->crystal;
		P = 1;
		break;
	case 0x132000:
		sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc);
		break;
	case 0x132020:
		sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref);
		break;
	case 0x137000:
	case 0x137020:
	case 0x137040:
	case 0x1370e0:
		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
		break;
	default:
		return 0;
	}

	return sclk * N / M / P;
}

static u32
read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
	u32 ssrc = nv_rd32(clk, dsrc + (doff * 4));
	u32 sctl = nv_rd32(clk, dctl + (doff * 4));

	switch (ssrc & 0x00000003) {
	case 0:
		if ((ssrc & 0x00030000) != 0x00030000)
			return nv_device(clk)->crystal;
		return 108000;
	case 2:
		return 100000;
	case 3:
		if (sctl & 0x80000000) {
			u32 sclk = read_vco(clk, dsrc + (doff * 4));
			u32 sdiv = (sctl & 0x0000003f) + 2;
			return (sclk * 2) / sdiv;
		}

		return read_vco(clk, dsrc + (doff * 4));
	default:
		return 0;
	}
}

static u32
read_clk(struct gf100_clk *clk, int idx)
{
	u32 sctl = nv_rd32(clk, 0x137250 + (idx * 4));
	u32 ssel = nv_rd32(clk, 0x137100);
	u32 sclk, sdiv;

	if (ssel & (1 << idx)) {
		if (idx < 7)
			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
		else
			sclk = read_pll(clk, 0x1370e0);
		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	} else {
		sclk = read_div(clk, idx, 0x137160, 0x1371d0);
		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	}

	if (sctl & 0x80000000)
		return (sclk * 2) / sdiv;

	return sclk;
}

static int
gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
	struct nvkm_device *device = nv_device(clk);

	switch (src) {
	case nv_clk_src_crystal:
		return device->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_sppll0:
		return read_pll(clk, 0x00e800);
	case nv_clk_src_sppll1:
		return read_pll(clk, 0x00e820);

	case nv_clk_src_mpllsrcref:
		return read_div(clk, 0, 0x137320, 0x137330);
	case nv_clk_src_mpllsrc:
		return read_pll(clk, 0x132020);
	case nv_clk_src_mpll:
		return read_pll(clk, 0x132000);
	case nv_clk_src_mdiv:
		return read_div(clk, 0, 0x137300, 0x137310);
	case nv_clk_src_mem:
		if (nv_rd32(clk, 0x1373f0) & 0x00000002)
			return clk->base.read(&clk->base, nv_clk_src_mpll);
		return clk->base.read(&clk->base, nv_clk_src_mdiv);

	case nv_clk_src_gpc:
		return read_clk(clk, 0x00);
	case nv_clk_src_rop:
		return read_clk(clk, 0x01);
	case nv_clk_src_hubk07:
		return read_clk(clk, 0x02);
	case nv_clk_src_hubk06:
		return read_clk(clk, 0x07);
	case nv_clk_src_hubk01:
		return read_clk(clk, 0x08);
	case nv_clk_src_copy:
		return read_clk(clk, 0x09);
	case nv_clk_src_daemon:
		return read_clk(clk, 0x0c);
	case nv_clk_src_vdec:
		return read_clk(clk, 0x0e);
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static u32
calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
{
	u32 div = min((ref * 2) / freq, (u32)65);
	if (div < 2)
		div = 2;

	*ddiv = div - 2;
	return (ref * 2) / div;
}

static u32
calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
{
	u32 sclk;

	/* use one of the fixed frequencies if possible */
	*ddiv = 0x00000000;
	switch (freq) {
	case  27000:
	case 108000:
		*dsrc = 0x00000000;
		if (freq == 108000)
			*dsrc |= 0x00030000;
		return freq;
	case 100000:
		*dsrc = 0x00000002;
		return freq;
	default:
		*dsrc = 0x00000003;
		break;
	}

	/* otherwise, calculate the closest divider */
	sclk = read_vco(clk, 0x137160 + (idx * 4));
	if (idx < 7)
		sclk = calc_div(clk, idx, sclk, freq, ddiv);
	return sclk;
}

static u32
calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
{
	struct nvkm_bios *bios = nvkm_bios(clk);
	struct nvbios_pll limits;
	int N, M, P, ret;

	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
	if (ret)
		return 0;

	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
	if (!limits.refclk)
		return 0;

	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
	if (ret <= 0)
		return 0;

	*coef = (P << 16) | (N << 8) | M;
	return ret;
}

static int
calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	u32 freq = cstate->domain[dom];
	u32 src0, div0, div1D, div1P = 0;
	u32 clk0, clk1 = 0;

	/* invalid clock domain */
	if (!freq)
		return 0;

	/* first possible path, using only dividers */
	clk0 = calc_src(clk, idx, freq, &src0, &div0);
	clk0 = calc_div(clk, idx, clk0, freq, &div1D);

	/* see if we can get any closer using PLLs */
	if (clk0 != freq && (0x00004387 & (1 << idx))) {
		if (idx <= 7)
			clk1 = calc_pll(clk, idx, freq, &info->coef);
		else
			clk1 = cstate->domain[nv_clk_src_hubk06];
		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
	}

	/* select the method which gets closest to target freq */
	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
		info->dsrc = src0;
		if (div0) {
			info->ddiv |= 0x80000000;
			info->ddiv |= div0 << 8;
			info->ddiv |= div0;
		}
		if (div1D) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1D;
		}
		info->ssel = info->coef = 0;
		info->freq = clk0;
	} else {
		if (div1P) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1P << 8;
		}
		info->ssel = (1 << idx);
		info->freq = clk1;
	}

	return 0;
}

static int
gf100_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
{
	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
	int ret;

	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
	    (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) ||
	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static void
gf100_clk_prog_0(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	if (idx < 7 && !info->ssel) {
		nv_mask(clk, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
		nv_wr32(clk, 0x137160 + (idx * 0x04), info->dsrc);
	}
}

static void
gf100_clk_prog_1(struct gf100_clk *clk, int idx)
{
	nv_mask(clk, 0x137100, (1 << idx), 0x00000000);
	nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
}

static void
gf100_clk_prog_2(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	const u32 addr = 0x137000 + (idx * 0x20);
	if (idx <= 7) {
		nv_mask(clk, addr + 0x00, 0x00000004, 0x00000000);
		nv_mask(clk, addr + 0x00, 0x00000001, 0x00000000);
		if (info->coef) {
			nv_wr32(clk, addr + 0x04, info->coef);
			nv_mask(clk, addr + 0x00, 0x00000001, 0x00000001);
			nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
			nv_mask(clk, addr + 0x00, 0x00020004, 0x00000004);
		}
	}
}

static void
gf100_clk_prog_3(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	if (info->ssel) {
		nv_mask(clk, 0x137100, (1 << idx), info->ssel);
		nv_wait(clk, 0x137100, (1 << idx), info->ssel);
	}
}

static void
gf100_clk_prog_4(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	nv_mask(clk, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
}

static int
gf100_clk_prog(struct nvkm_clk *obj)
{
	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
	struct {
		void (*exec)(struct gf100_clk *, int);
	} stage[] = {
		{ gf100_clk_prog_0 }, /* div programming */
		{ gf100_clk_prog_1 }, /* select div mode */
		{ gf100_clk_prog_2 }, /* (maybe) program pll */
		{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
		{ gf100_clk_prog_4 }, /* final divider */
	};
	int i, j;

	for (i = 0; i < ARRAY_SIZE(stage); i++) {
		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
			if (!clk->eng[j].freq)
				continue;
			stage[i].exec(clk, j);
		}
	}

	return 0;
}

static void
gf100_clk_tidy(struct nvkm_clk *obj)
{
	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
	memset(clk->eng, 0x00, sizeof(clk->eng));
}

static struct nvkm_domain
gf100_domain[] = {
	{ nv_clk_src_crystal, 0xff },
	{ nv_clk_src_href   , 0xff },
	{ nv_clk_src_hubk06 , 0x00 },
	{ nv_clk_src_hubk01 , 0x01 },
	{ nv_clk_src_copy   , 0x02 },
	{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
	{ nv_clk_src_rop    , 0x04 },
	{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
	{ nv_clk_src_vdec   , 0x06 },
	{ nv_clk_src_daemon , 0x0a },
	{ nv_clk_src_hubk07 , 0x0b },
	{ nv_clk_src_max }
};

static int
gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	       struct nvkm_oclass *oclass, void *data, u32 size,
	       struct nvkm_object **pobject)
{
	struct gf100_clk *clk;
	int ret;

	ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
			      NULL, 0, false, &clk);
	*pobject = nv_object(clk);
	if (ret)
		return ret;

	clk->base.read = gf100_clk_read;
	clk->base.calc = gf100_clk_calc;
	clk->base.prog = gf100_clk_prog;
	clk->base.tidy = gf100_clk_tidy;
	return 0;
}

struct nvkm_oclass
gf100_clk_oclass = {
	.handle = NV_SUBDEV(CLK, 0xc0),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = gf100_clk_ctor,
		.dtor = _nvkm_clk_dtor,
		.init = _nvkm_clk_init,
		.fini = _nvkm_clk_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
f3867f43	24	#include <subdev/clk.h>
7632b30e BS	25	#include "pll.h"
7632b30e BS	26
70790f4f BS	27	#include <subdev/bios.h>
70790f4f BS	28	#include <subdev/bios/pll.h>
7c856522	29	#include <subdev/timer.h>
70790f4f	30
7632b30e	31	struct gf100_clk_info {
7c856522 BS	32	u32 freq;
	33	u32 ssel;
	34	u32 mdiv;
	35	u32 dsrc;
	36	u32 ddiv;
	37	u32 coef;
	38	};
	39
3eca809b	40	struct gf100_clk {
7632b30e BS	41	struct nvkm_clk base;
7632b30e BS	42	struct gf100_clk_info eng[16];
7c856522 BS	43	};
7c856522 BS	44
3eca809b	45	static u32 read_div(struct gf100_clk *, int, u32, u32);
7c856522 BS	46
7c856522 BS	47	static u32
3eca809b	48	read_vco(struct gf100_clk *clk, u32 dsrc)
7c856522	49	{
3eca809b	50	u32 ssrc = nv_rd32(clk, dsrc);
7c856522	51	if (!(ssrc & 0x00000100))
3eca809b BS	52	return clk->base.read(&clk->base, nv_clk_src_sppll0);
3eca809b BS	53	return clk->base.read(&clk->base, nv_clk_src_sppll1);
7c856522 BS	54	}
	55
	56	static u32
3eca809b	57	read_pll(struct gf100_clk *clk, u32 pll)
7c856522	58	{
3eca809b BS	59	u32 ctrl = nv_rd32(clk, pll + 0x00);
3eca809b BS	60	u32 coef = nv_rd32(clk, pll + 0x04);
7c856522 BS	61	u32 P = (coef & 0x003f0000) >> 16;
	62	u32 N = (coef & 0x0000ff00) >> 8;
	63	u32 M = (coef & 0x000000ff) >> 0;
	64	u32 sclk;
	65
	66	if (!(ctrl & 0x00000001))
	67	return 0;
	68
	69	switch (pll) {
	70	case 0x00e800:
	71	case 0x00e820:
3eca809b	72	sclk = nv_device(clk)->crystal;
7c856522 BS	73	P = 1;
	74	break;
	75	case 0x132000:
3eca809b	76	sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc);
7c856522 BS	77	break;
7c856522 BS	78	case 0x132020:
3eca809b	79	sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref);
7c856522 BS	80	break;
	81	case 0x137000:
	82	case 0x137020:
	83	case 0x137040:
	84	case 0x1370e0:
3eca809b	85	sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
7c856522 BS	86	break;
	87	default:
	88	return 0;
	89	}
	90
	91	return sclk * N / M / P;
	92	}
	93
	94	static u32
3eca809b	95	read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
7c856522	96	{
3eca809b BS	97	u32 ssrc = nv_rd32(clk, dsrc + (doff * 4));
3eca809b BS	98	u32 sctl = nv_rd32(clk, dctl + (doff * 4));
7c856522 BS	99
	100	switch (ssrc & 0x00000003) {
	101	case 0:
	102	if ((ssrc & 0x00030000) != 0x00030000)
3eca809b	103	return nv_device(clk)->crystal;
7c856522 BS	104	return 108000;
	105	case 2:
	106	return 100000;
	107	case 3:
	108	if (sctl & 0x80000000) {
3eca809b	109	u32 sclk = read_vco(clk, dsrc + (doff * 4));
7c856522 BS	110	u32 sdiv = (sctl & 0x0000003f) + 2;
	111	return (sclk * 2) / sdiv;
	112	}
	113
3eca809b	114	return read_vco(clk, dsrc + (doff * 4));
7c856522 BS	115	default:
	116	return 0;
	117	}
	118	}
	119
	120	static u32
3eca809b	121	read_clk(struct gf100_clk *clk, int idx)
7c856522	122	{
3eca809b BS	123	u32 sctl = nv_rd32(clk, 0x137250 + (idx * 4));
3eca809b BS	124	u32 ssel = nv_rd32(clk, 0x137100);
7c856522 BS	125	u32 sclk, sdiv;
7c856522 BS	126
3eca809b BS	127	if (ssel & (1 << idx)) {
	128	if (idx < 7)
	129	sclk = read_pll(clk, 0x137000 + (idx * 0x20));
7c856522	130	else
3eca809b	131	sclk = read_pll(clk, 0x1370e0);
7c856522 BS	132	sdiv = ((sctl & 0x00003f00) >> 8) + 2;
7c856522 BS	133	} else {
3eca809b	134	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	135	sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	136	}
	137
	138	if (sctl & 0x80000000)
	139	return (sclk * 2) / sdiv;
	140
	141	return sclk;
	142	}
	143
	144	static int
3eca809b	145	gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
7c856522	146	{
3eca809b	147	struct gf100_clk clk = container_of(obj, typeof(clk), base);
7632b30e	148	struct nvkm_device *device = nv_device(clk);
7c856522 BS	149
	150	switch (src) {
	151	case nv_clk_src_crystal:
	152	return device->crystal;
	153	case nv_clk_src_href:
	154	return 100000;
	155	case nv_clk_src_sppll0:
3eca809b	156	return read_pll(clk, 0x00e800);
7c856522	157	case nv_clk_src_sppll1:
3eca809b	158	return read_pll(clk, 0x00e820);
7c856522 BS	159
7c856522 BS	160	case nv_clk_src_mpllsrcref:
3eca809b	161	return read_div(clk, 0, 0x137320, 0x137330);
7c856522	162	case nv_clk_src_mpllsrc:
3eca809b	163	return read_pll(clk, 0x132020);
7c856522	164	case nv_clk_src_mpll:
3eca809b	165	return read_pll(clk, 0x132000);
7c856522	166	case nv_clk_src_mdiv:
3eca809b	167	return read_div(clk, 0, 0x137300, 0x137310);
7c856522	168	case nv_clk_src_mem:
3eca809b BS	169	if (nv_rd32(clk, 0x1373f0) & 0x00000002)
	170	return clk->base.read(&clk->base, nv_clk_src_mpll);
	171	return clk->base.read(&clk->base, nv_clk_src_mdiv);
7c856522 BS	172
7c856522 BS	173	case nv_clk_src_gpc:
3eca809b	174	return read_clk(clk, 0x00);
7c856522	175	case nv_clk_src_rop:
3eca809b	176	return read_clk(clk, 0x01);
7c856522	177	case nv_clk_src_hubk07:
3eca809b	178	return read_clk(clk, 0x02);
7c856522	179	case nv_clk_src_hubk06:
3eca809b	180	return read_clk(clk, 0x07);
7c856522	181	case nv_clk_src_hubk01:
3eca809b	182	return read_clk(clk, 0x08);
7c856522	183	case nv_clk_src_copy:
3eca809b	184	return read_clk(clk, 0x09);
7c856522	185	case nv_clk_src_daemon:
3eca809b	186	return read_clk(clk, 0x0c);
7c856522	187	case nv_clk_src_vdec:
3eca809b	188	return read_clk(clk, 0x0e);
7c856522 BS	189	default:
	190	nv_error(clk, "invalid clock source %d\n", src);
	191	return -EINVAL;
	192	}
	193	}
	194
	195	static u32
3eca809b	196	calc_div(struct gf100_clk clk, int idx, u32 ref, u32 freq, u32 ddiv)
7c856522 BS	197	{
	198	u32 div = min((ref * 2) / freq, (u32)65);
	199	if (div < 2)
	200	div = 2;
	201
	202	*ddiv = div - 2;
	203	return (ref * 2) / div;
	204	}
	205
	206	static u32
3eca809b	207	calc_src(struct gf100_clk clk, int idx, u32 freq, u32 dsrc, u32 *ddiv)
7c856522 BS	208	{
	209	u32 sclk;
	210
	211	/* use one of the fixed frequencies if possible */
	212	*ddiv = 0x00000000;
	213	switch (freq) {
	214	case 27000:
	215	case 108000:
	216	*dsrc = 0x00000000;
	217	if (freq == 108000)
	218	*dsrc \|= 0x00030000;
	219	return freq;
	220	case 100000:
	221	*dsrc = 0x00000002;
	222	return freq;
	223	default:
	224	*dsrc = 0x00000003;
	225	break;
	226	}
	227
	228	/* otherwise, calculate the closest divider */
3eca809b BS	229	sclk = read_vco(clk, 0x137160 + (idx * 4));
	230	if (idx < 7)
	231	sclk = calc_div(clk, idx, sclk, freq, ddiv);
7c856522 BS	232	return sclk;
	233	}
	234
	235	static u32
3eca809b	236	calc_pll(struct gf100_clk clk, int idx, u32 freq, u32 coef)
7c856522	237	{
3eca809b	238	struct nvkm_bios *bios = nvkm_bios(clk);
7c856522 BS	239	struct nvbios_pll limits;
	240	int N, M, P, ret;
	241
3eca809b	242	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
7c856522 BS	243	if (ret)
	244	return 0;
	245
3eca809b	246	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
7c856522 BS	247	if (!limits.refclk)
	248	return 0;
	249
3eca809b	250	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
7c856522 BS	251	if (ret <= 0)
	252	return 0;
	253
	254	*coef = (P << 16) \| (N << 8) \| M;
	255	return ret;
	256	}
	257
	258	static int
3eca809b	259	calc_clk(struct gf100_clk clk, struct nvkm_cstate cstate, int idx, int dom)
7c856522	260	{
3eca809b	261	struct gf100_clk_info *info = &clk->eng[idx];
7c856522 BS	262	u32 freq = cstate->domain[dom];
	263	u32 src0, div0, div1D, div1P = 0;
	264	u32 clk0, clk1 = 0;
	265
	266	/* invalid clock domain */
	267	if (!freq)
	268	return 0;
	269
	270	/* first possible path, using only dividers */
3eca809b BS	271	clk0 = calc_src(clk, idx, freq, &src0, &div0);
3eca809b BS	272	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
7c856522 BS	273
7c856522 BS	274	/* see if we can get any closer using PLLs */
3eca809b BS	275	if (clk0 != freq && (0x00004387 & (1 << idx))) {
	276	if (idx <= 7)
	277	clk1 = calc_pll(clk, idx, freq, &info->coef);
7c856522 BS	278	else
7c856522 BS	279	clk1 = cstate->domain[nv_clk_src_hubk06];
3eca809b	280	clk1 = calc_div(clk, idx, clk1, freq, &div1P);
7c856522 BS	281	}
	282
	283	/* select the method which gets closest to target freq */
	284	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
	285	info->dsrc = src0;
	286	if (div0) {
	287	info->ddiv \|= 0x80000000;
	288	info->ddiv \|= div0 << 8;
	289	info->ddiv \|= div0;
	290	}
	291	if (div1D) {
	292	info->mdiv \|= 0x80000000;
	293	info->mdiv \|= div1D;
	294	}
	295	info->ssel = info->coef = 0;
	296	info->freq = clk0;
	297	} else {
	298	if (div1P) {
	299	info->mdiv \|= 0x80000000;
	300	info->mdiv \|= div1P << 8;
	301	}
3eca809b	302	info->ssel = (1 << idx);
7c856522 BS	303	info->freq = clk1;
	304	}
	305
	306	return 0;
	307	}
	308
	309	static int
3eca809b	310	gf100_clk_calc(struct nvkm_clk obj, struct nvkm_cstate cstate)
7c856522	311	{
3eca809b	312	struct gf100_clk clk = container_of(obj, typeof(clk), base);
7c856522 BS	313	int ret;
7c856522 BS	314
3eca809b BS	315	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) \|\|
	316	(ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) \|\|
	317	(ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) \|\|
	318	(ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) \|\|
	319	(ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) \|\|
	320	(ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) \|\|
	321	(ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) \|\|
	322	(ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
7c856522 BS	323	return ret;
	324
	325	return 0;
	326	}
	327
	328	static void
3eca809b	329	gf100_clk_prog_0(struct gf100_clk *clk, int idx)
7c856522	330	{
3eca809b BS	331	struct gf100_clk_info *info = &clk->eng[idx];
	332	if (idx < 7 && !info->ssel) {
	333	nv_mask(clk, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
	334	nv_wr32(clk, 0x137160 + (idx * 0x04), info->dsrc);
7c856522 BS	335	}
	336	}
	337
	338	static void
3eca809b	339	gf100_clk_prog_1(struct gf100_clk *clk, int idx)
7c856522	340	{
3eca809b BS	341	nv_mask(clk, 0x137100, (1 << idx), 0x00000000);
3eca809b BS	342	nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
7c856522 BS	343	}
	344
	345	static void
3eca809b	346	gf100_clk_prog_2(struct gf100_clk *clk, int idx)
7c856522	347	{
3eca809b BS	348	struct gf100_clk_info *info = &clk->eng[idx];
	349	const u32 addr = 0x137000 + (idx * 0x20);
	350	if (idx <= 7) {
	351	nv_mask(clk, addr + 0x00, 0x00000004, 0x00000000);
	352	nv_mask(clk, addr + 0x00, 0x00000001, 0x00000000);
7c856522	353	if (info->coef) {
3eca809b BS	354	nv_wr32(clk, addr + 0x04, info->coef);
	355	nv_mask(clk, addr + 0x00, 0x00000001, 0x00000001);
	356	nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
	357	nv_mask(clk, addr + 0x00, 0x00020004, 0x00000004);
7c856522 BS	358	}
	359	}
	360	}
	361
	362	static void
3eca809b	363	gf100_clk_prog_3(struct gf100_clk *clk, int idx)
7c856522	364	{
3eca809b	365	struct gf100_clk_info *info = &clk->eng[idx];
7c856522	366	if (info->ssel) {
3eca809b BS	367	nv_mask(clk, 0x137100, (1 << idx), info->ssel);
3eca809b BS	368	nv_wait(clk, 0x137100, (1 << idx), info->ssel);
7c856522 BS	369	}
	370	}
	371
	372	static void
3eca809b	373	gf100_clk_prog_4(struct gf100_clk *clk, int idx)
7c856522	374	{
3eca809b BS	375	struct gf100_clk_info *info = &clk->eng[idx];
3eca809b BS	376	nv_mask(clk, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
7c856522 BS	377	}
	378
	379	static int
3eca809b	380	gf100_clk_prog(struct nvkm_clk *obj)
7c856522	381	{
3eca809b	382	struct gf100_clk clk = container_of(obj, typeof(clk), base);
7c856522	383	struct {
3eca809b	384	void (exec)(struct gf100_clk , int);
7c856522	385	} stage[] = {
7632b30e BS	386	{ gf100_clk_prog_0 }, /* div programming */
	387	{ gf100_clk_prog_1 }, /* select div mode */
	388	{ gf100_clk_prog_2 }, /* (maybe) program pll */
	389	{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
	390	{ gf100_clk_prog_4 }, /* final divider */
7c856522 BS	391	};
	392	int i, j;
	393
	394	for (i = 0; i < ARRAY_SIZE(stage); i++) {
3eca809b BS	395	for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
3eca809b BS	396	if (!clk->eng[j].freq)
7c856522	397	continue;
3eca809b	398	stage[i].exec(clk, j);
7c856522 BS	399	}
	400	}
	401
	402	return 0;
	403	}
	404
	405	static void
3eca809b	406	gf100_clk_tidy(struct nvkm_clk *obj)
7c856522	407	{
3eca809b BS	408	struct gf100_clk clk = container_of(obj, typeof(clk), base);
3eca809b BS	409	memset(clk->eng, 0x00, sizeof(clk->eng));
7c856522 BS	410	}
7c856522 BS	411
7632b30e BS	412	static struct nvkm_domain
7632b30e BS	413	gf100_domain[] = {
7c856522 BS	414	{ nv_clk_src_crystal, 0xff },
	415	{ nv_clk_src_href , 0xff },
	416	{ nv_clk_src_hubk06 , 0x00 },
	417	{ nv_clk_src_hubk01 , 0x01 },
	418	{ nv_clk_src_copy , 0x02 },
	419	{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
	420	{ nv_clk_src_rop , 0x04 },
	421	{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
	422	{ nv_clk_src_vdec , 0x06 },
	423	{ nv_clk_src_daemon , 0x0a },
	424	{ nv_clk_src_hubk07 , 0x0b },
	425	{ nv_clk_src_max }
8aceb7de BS	426	};
8aceb7de BS	427
8aceb7de	428	static int
7632b30e BS	429	gf100_clk_ctor(struct nvkm_object parent, struct nvkm_object engine,
	430	struct nvkm_oclass oclass, void data, u32 size,
	431	struct nvkm_object **pobject)
8aceb7de	432	{
3eca809b	433	struct gf100_clk *clk;
8aceb7de BS	434	int ret;
8aceb7de BS	435
7632b30e	436	ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
3eca809b BS	437	NULL, 0, false, &clk);
3eca809b BS	438	*pobject = nv_object(clk);
8aceb7de BS	439	if (ret)
	440	return ret;
	441
3eca809b BS	442	clk->base.read = gf100_clk_read;
	443	clk->base.calc = gf100_clk_calc;
	444	clk->base.prog = gf100_clk_prog;
	445	clk->base.tidy = gf100_clk_tidy;
8aceb7de BS	446	return 0;
	447	}
	448
7632b30e BS	449	struct nvkm_oclass
7632b30e BS	450	gf100_clk_oclass = {
f3867f43	451	.handle = NV_SUBDEV(CLK, 0xc0),
7632b30e BS	452	.ofuncs = &(struct nvkm_ofuncs) {
	453	.ctor = gf100_clk_ctor,
	454	.dtor = _nvkm_clk_dtor,
	455	.init = _nvkm_clk_init,
	456	.fini = _nvkm_clk_fini,
8aceb7de BS	457	},
8aceb7de BS	458	};