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8aceb7de BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
f3867f43 | 24 | #include <subdev/clk.h> |
7632b30e BS |
25 | #include "pll.h" |
26 | ||
70790f4f BS |
27 | #include <subdev/bios.h> |
28 | #include <subdev/bios/pll.h> | |
7c856522 | 29 | #include <subdev/timer.h> |
70790f4f | 30 | |
7632b30e | 31 | struct gf100_clk_info { |
7c856522 BS |
32 | u32 freq; |
33 | u32 ssel; | |
34 | u32 mdiv; | |
35 | u32 dsrc; | |
36 | u32 ddiv; | |
37 | u32 coef; | |
38 | }; | |
39 | ||
3eca809b | 40 | struct gf100_clk { |
7632b30e BS |
41 | struct nvkm_clk base; |
42 | struct gf100_clk_info eng[16]; | |
7c856522 BS |
43 | }; |
44 | ||
3eca809b | 45 | static u32 read_div(struct gf100_clk *, int, u32, u32); |
7c856522 BS |
46 | |
47 | static u32 | |
3eca809b | 48 | read_vco(struct gf100_clk *clk, u32 dsrc) |
7c856522 | 49 | { |
822ad79f BS |
50 | struct nvkm_device *device = clk->base.subdev.device; |
51 | u32 ssrc = nvkm_rd32(device, dsrc); | |
7c856522 | 52 | if (!(ssrc & 0x00000100)) |
3eca809b BS |
53 | return clk->base.read(&clk->base, nv_clk_src_sppll0); |
54 | return clk->base.read(&clk->base, nv_clk_src_sppll1); | |
7c856522 BS |
55 | } |
56 | ||
57 | static u32 | |
3eca809b | 58 | read_pll(struct gf100_clk *clk, u32 pll) |
7c856522 | 59 | { |
822ad79f BS |
60 | struct nvkm_device *device = clk->base.subdev.device; |
61 | u32 ctrl = nvkm_rd32(device, pll + 0x00); | |
62 | u32 coef = nvkm_rd32(device, pll + 0x04); | |
7c856522 BS |
63 | u32 P = (coef & 0x003f0000) >> 16; |
64 | u32 N = (coef & 0x0000ff00) >> 8; | |
65 | u32 M = (coef & 0x000000ff) >> 0; | |
66 | u32 sclk; | |
67 | ||
68 | if (!(ctrl & 0x00000001)) | |
69 | return 0; | |
70 | ||
71 | switch (pll) { | |
72 | case 0x00e800: | |
73 | case 0x00e820: | |
822ad79f | 74 | sclk = device->crystal; |
7c856522 BS |
75 | P = 1; |
76 | break; | |
77 | case 0x132000: | |
3eca809b | 78 | sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc); |
7c856522 BS |
79 | break; |
80 | case 0x132020: | |
3eca809b | 81 | sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref); |
7c856522 BS |
82 | break; |
83 | case 0x137000: | |
84 | case 0x137020: | |
85 | case 0x137040: | |
86 | case 0x1370e0: | |
3eca809b | 87 | sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); |
7c856522 BS |
88 | break; |
89 | default: | |
90 | return 0; | |
91 | } | |
92 | ||
93 | return sclk * N / M / P; | |
94 | } | |
95 | ||
96 | static u32 | |
3eca809b | 97 | read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl) |
7c856522 | 98 | { |
822ad79f BS |
99 | struct nvkm_device *device = clk->base.subdev.device; |
100 | u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4)); | |
101 | u32 sctl = nvkm_rd32(device, dctl + (doff * 4)); | |
7c856522 BS |
102 | |
103 | switch (ssrc & 0x00000003) { | |
104 | case 0: | |
105 | if ((ssrc & 0x00030000) != 0x00030000) | |
822ad79f | 106 | return device->crystal; |
7c856522 BS |
107 | return 108000; |
108 | case 2: | |
109 | return 100000; | |
110 | case 3: | |
111 | if (sctl & 0x80000000) { | |
3eca809b | 112 | u32 sclk = read_vco(clk, dsrc + (doff * 4)); |
7c856522 BS |
113 | u32 sdiv = (sctl & 0x0000003f) + 2; |
114 | return (sclk * 2) / sdiv; | |
115 | } | |
116 | ||
3eca809b | 117 | return read_vco(clk, dsrc + (doff * 4)); |
7c856522 BS |
118 | default: |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
123 | static u32 | |
3eca809b | 124 | read_clk(struct gf100_clk *clk, int idx) |
7c856522 | 125 | { |
822ad79f BS |
126 | struct nvkm_device *device = clk->base.subdev.device; |
127 | u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); | |
128 | u32 ssel = nvkm_rd32(device, 0x137100); | |
7c856522 BS |
129 | u32 sclk, sdiv; |
130 | ||
3eca809b BS |
131 | if (ssel & (1 << idx)) { |
132 | if (idx < 7) | |
133 | sclk = read_pll(clk, 0x137000 + (idx * 0x20)); | |
7c856522 | 134 | else |
3eca809b | 135 | sclk = read_pll(clk, 0x1370e0); |
7c856522 BS |
136 | sdiv = ((sctl & 0x00003f00) >> 8) + 2; |
137 | } else { | |
3eca809b | 138 | sclk = read_div(clk, idx, 0x137160, 0x1371d0); |
7c856522 BS |
139 | sdiv = ((sctl & 0x0000003f) >> 0) + 2; |
140 | } | |
141 | ||
142 | if (sctl & 0x80000000) | |
143 | return (sclk * 2) / sdiv; | |
144 | ||
145 | return sclk; | |
146 | } | |
147 | ||
148 | static int | |
3eca809b | 149 | gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) |
7c856522 | 150 | { |
3eca809b | 151 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
822ad79f | 152 | struct nvkm_device *device = clk->base.subdev.device; |
7c856522 BS |
153 | |
154 | switch (src) { | |
155 | case nv_clk_src_crystal: | |
156 | return device->crystal; | |
157 | case nv_clk_src_href: | |
158 | return 100000; | |
159 | case nv_clk_src_sppll0: | |
3eca809b | 160 | return read_pll(clk, 0x00e800); |
7c856522 | 161 | case nv_clk_src_sppll1: |
3eca809b | 162 | return read_pll(clk, 0x00e820); |
7c856522 BS |
163 | |
164 | case nv_clk_src_mpllsrcref: | |
3eca809b | 165 | return read_div(clk, 0, 0x137320, 0x137330); |
7c856522 | 166 | case nv_clk_src_mpllsrc: |
3eca809b | 167 | return read_pll(clk, 0x132020); |
7c856522 | 168 | case nv_clk_src_mpll: |
3eca809b | 169 | return read_pll(clk, 0x132000); |
7c856522 | 170 | case nv_clk_src_mdiv: |
3eca809b | 171 | return read_div(clk, 0, 0x137300, 0x137310); |
7c856522 | 172 | case nv_clk_src_mem: |
822ad79f | 173 | if (nvkm_rd32(device, 0x1373f0) & 0x00000002) |
3eca809b BS |
174 | return clk->base.read(&clk->base, nv_clk_src_mpll); |
175 | return clk->base.read(&clk->base, nv_clk_src_mdiv); | |
7c856522 BS |
176 | |
177 | case nv_clk_src_gpc: | |
3eca809b | 178 | return read_clk(clk, 0x00); |
7c856522 | 179 | case nv_clk_src_rop: |
3eca809b | 180 | return read_clk(clk, 0x01); |
7c856522 | 181 | case nv_clk_src_hubk07: |
3eca809b | 182 | return read_clk(clk, 0x02); |
7c856522 | 183 | case nv_clk_src_hubk06: |
3eca809b | 184 | return read_clk(clk, 0x07); |
7c856522 | 185 | case nv_clk_src_hubk01: |
3eca809b | 186 | return read_clk(clk, 0x08); |
7c856522 | 187 | case nv_clk_src_copy: |
3eca809b | 188 | return read_clk(clk, 0x09); |
7c856522 | 189 | case nv_clk_src_daemon: |
3eca809b | 190 | return read_clk(clk, 0x0c); |
7c856522 | 191 | case nv_clk_src_vdec: |
3eca809b | 192 | return read_clk(clk, 0x0e); |
7c856522 BS |
193 | default: |
194 | nv_error(clk, "invalid clock source %d\n", src); | |
195 | return -EINVAL; | |
196 | } | |
197 | } | |
198 | ||
199 | static u32 | |
3eca809b | 200 | calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) |
7c856522 BS |
201 | { |
202 | u32 div = min((ref * 2) / freq, (u32)65); | |
203 | if (div < 2) | |
204 | div = 2; | |
205 | ||
206 | *ddiv = div - 2; | |
207 | return (ref * 2) / div; | |
208 | } | |
209 | ||
210 | static u32 | |
3eca809b | 211 | calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) |
7c856522 BS |
212 | { |
213 | u32 sclk; | |
214 | ||
215 | /* use one of the fixed frequencies if possible */ | |
216 | *ddiv = 0x00000000; | |
217 | switch (freq) { | |
218 | case 27000: | |
219 | case 108000: | |
220 | *dsrc = 0x00000000; | |
221 | if (freq == 108000) | |
222 | *dsrc |= 0x00030000; | |
223 | return freq; | |
224 | case 100000: | |
225 | *dsrc = 0x00000002; | |
226 | return freq; | |
227 | default: | |
228 | *dsrc = 0x00000003; | |
229 | break; | |
230 | } | |
231 | ||
232 | /* otherwise, calculate the closest divider */ | |
3eca809b BS |
233 | sclk = read_vco(clk, 0x137160 + (idx * 4)); |
234 | if (idx < 7) | |
235 | sclk = calc_div(clk, idx, sclk, freq, ddiv); | |
7c856522 BS |
236 | return sclk; |
237 | } | |
238 | ||
239 | static u32 | |
3eca809b | 240 | calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef) |
7c856522 | 241 | { |
3eca809b | 242 | struct nvkm_bios *bios = nvkm_bios(clk); |
7c856522 BS |
243 | struct nvbios_pll limits; |
244 | int N, M, P, ret; | |
245 | ||
3eca809b | 246 | ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits); |
7c856522 BS |
247 | if (ret) |
248 | return 0; | |
249 | ||
3eca809b | 250 | limits.refclk = read_div(clk, idx, 0x137120, 0x137140); |
7c856522 BS |
251 | if (!limits.refclk) |
252 | return 0; | |
253 | ||
3eca809b | 254 | ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P); |
7c856522 BS |
255 | if (ret <= 0) |
256 | return 0; | |
257 | ||
258 | *coef = (P << 16) | (N << 8) | M; | |
259 | return ret; | |
260 | } | |
261 | ||
262 | static int | |
3eca809b | 263 | calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) |
7c856522 | 264 | { |
3eca809b | 265 | struct gf100_clk_info *info = &clk->eng[idx]; |
7c856522 BS |
266 | u32 freq = cstate->domain[dom]; |
267 | u32 src0, div0, div1D, div1P = 0; | |
268 | u32 clk0, clk1 = 0; | |
269 | ||
270 | /* invalid clock domain */ | |
271 | if (!freq) | |
272 | return 0; | |
273 | ||
274 | /* first possible path, using only dividers */ | |
3eca809b BS |
275 | clk0 = calc_src(clk, idx, freq, &src0, &div0); |
276 | clk0 = calc_div(clk, idx, clk0, freq, &div1D); | |
7c856522 BS |
277 | |
278 | /* see if we can get any closer using PLLs */ | |
3eca809b BS |
279 | if (clk0 != freq && (0x00004387 & (1 << idx))) { |
280 | if (idx <= 7) | |
281 | clk1 = calc_pll(clk, idx, freq, &info->coef); | |
7c856522 BS |
282 | else |
283 | clk1 = cstate->domain[nv_clk_src_hubk06]; | |
3eca809b | 284 | clk1 = calc_div(clk, idx, clk1, freq, &div1P); |
7c856522 BS |
285 | } |
286 | ||
287 | /* select the method which gets closest to target freq */ | |
288 | if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { | |
289 | info->dsrc = src0; | |
290 | if (div0) { | |
291 | info->ddiv |= 0x80000000; | |
292 | info->ddiv |= div0 << 8; | |
293 | info->ddiv |= div0; | |
294 | } | |
295 | if (div1D) { | |
296 | info->mdiv |= 0x80000000; | |
297 | info->mdiv |= div1D; | |
298 | } | |
299 | info->ssel = info->coef = 0; | |
300 | info->freq = clk0; | |
301 | } else { | |
302 | if (div1P) { | |
303 | info->mdiv |= 0x80000000; | |
304 | info->mdiv |= div1P << 8; | |
305 | } | |
3eca809b | 306 | info->ssel = (1 << idx); |
7c856522 BS |
307 | info->freq = clk1; |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int | |
3eca809b | 314 | gf100_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) |
7c856522 | 315 | { |
3eca809b | 316 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
7c856522 BS |
317 | int ret; |
318 | ||
3eca809b BS |
319 | if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || |
320 | (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || | |
321 | (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || | |
322 | (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || | |
323 | (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || | |
324 | (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || | |
325 | (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || | |
326 | (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) | |
7c856522 BS |
327 | return ret; |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static void | |
3eca809b | 333 | gf100_clk_prog_0(struct gf100_clk *clk, int idx) |
7c856522 | 334 | { |
3eca809b | 335 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 336 | struct nvkm_device *device = clk->base.subdev.device; |
3eca809b | 337 | if (idx < 7 && !info->ssel) { |
822ad79f BS |
338 | nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv); |
339 | nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); | |
7c856522 BS |
340 | } |
341 | } | |
342 | ||
343 | static void | |
3eca809b | 344 | gf100_clk_prog_1(struct gf100_clk *clk, int idx) |
7c856522 | 345 | { |
822ad79f BS |
346 | struct nvkm_device *device = clk->base.subdev.device; |
347 | nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); | |
3eca809b | 348 | nv_wait(clk, 0x137100, (1 << idx), 0x00000000); |
7c856522 BS |
349 | } |
350 | ||
351 | static void | |
3eca809b | 352 | gf100_clk_prog_2(struct gf100_clk *clk, int idx) |
7c856522 | 353 | { |
3eca809b | 354 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 355 | struct nvkm_device *device = clk->base.subdev.device; |
3eca809b BS |
356 | const u32 addr = 0x137000 + (idx * 0x20); |
357 | if (idx <= 7) { | |
822ad79f BS |
358 | nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); |
359 | nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); | |
7c856522 | 360 | if (info->coef) { |
822ad79f BS |
361 | nvkm_wr32(device, addr + 0x04, info->coef); |
362 | nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); | |
3eca809b | 363 | nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000); |
822ad79f | 364 | nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); |
7c856522 BS |
365 | } |
366 | } | |
367 | } | |
368 | ||
369 | static void | |
3eca809b | 370 | gf100_clk_prog_3(struct gf100_clk *clk, int idx) |
7c856522 | 371 | { |
3eca809b | 372 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 373 | struct nvkm_device *device = clk->base.subdev.device; |
7c856522 | 374 | if (info->ssel) { |
822ad79f | 375 | nvkm_mask(device, 0x137100, (1 << idx), info->ssel); |
3eca809b | 376 | nv_wait(clk, 0x137100, (1 << idx), info->ssel); |
7c856522 BS |
377 | } |
378 | } | |
379 | ||
380 | static void | |
3eca809b | 381 | gf100_clk_prog_4(struct gf100_clk *clk, int idx) |
7c856522 | 382 | { |
3eca809b | 383 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f BS |
384 | struct nvkm_device *device = clk->base.subdev.device; |
385 | nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); | |
7c856522 BS |
386 | } |
387 | ||
388 | static int | |
3eca809b | 389 | gf100_clk_prog(struct nvkm_clk *obj) |
7c856522 | 390 | { |
3eca809b | 391 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
7c856522 | 392 | struct { |
3eca809b | 393 | void (*exec)(struct gf100_clk *, int); |
7c856522 | 394 | } stage[] = { |
7632b30e BS |
395 | { gf100_clk_prog_0 }, /* div programming */ |
396 | { gf100_clk_prog_1 }, /* select div mode */ | |
397 | { gf100_clk_prog_2 }, /* (maybe) program pll */ | |
398 | { gf100_clk_prog_3 }, /* (maybe) select pll mode */ | |
399 | { gf100_clk_prog_4 }, /* final divider */ | |
7c856522 BS |
400 | }; |
401 | int i, j; | |
402 | ||
403 | for (i = 0; i < ARRAY_SIZE(stage); i++) { | |
3eca809b BS |
404 | for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { |
405 | if (!clk->eng[j].freq) | |
7c856522 | 406 | continue; |
3eca809b | 407 | stage[i].exec(clk, j); |
7c856522 BS |
408 | } |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static void | |
3eca809b | 415 | gf100_clk_tidy(struct nvkm_clk *obj) |
7c856522 | 416 | { |
3eca809b BS |
417 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
418 | memset(clk->eng, 0x00, sizeof(clk->eng)); | |
7c856522 BS |
419 | } |
420 | ||
7632b30e BS |
421 | static struct nvkm_domain |
422 | gf100_domain[] = { | |
7c856522 BS |
423 | { nv_clk_src_crystal, 0xff }, |
424 | { nv_clk_src_href , 0xff }, | |
425 | { nv_clk_src_hubk06 , 0x00 }, | |
426 | { nv_clk_src_hubk01 , 0x01 }, | |
427 | { nv_clk_src_copy , 0x02 }, | |
428 | { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, | |
429 | { nv_clk_src_rop , 0x04 }, | |
430 | { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, | |
431 | { nv_clk_src_vdec , 0x06 }, | |
432 | { nv_clk_src_daemon , 0x0a }, | |
433 | { nv_clk_src_hubk07 , 0x0b }, | |
434 | { nv_clk_src_max } | |
8aceb7de BS |
435 | }; |
436 | ||
8aceb7de | 437 | static int |
7632b30e BS |
438 | gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
439 | struct nvkm_oclass *oclass, void *data, u32 size, | |
440 | struct nvkm_object **pobject) | |
8aceb7de | 441 | { |
3eca809b | 442 | struct gf100_clk *clk; |
8aceb7de BS |
443 | int ret; |
444 | ||
7632b30e | 445 | ret = nvkm_clk_create(parent, engine, oclass, gf100_domain, |
3eca809b BS |
446 | NULL, 0, false, &clk); |
447 | *pobject = nv_object(clk); | |
8aceb7de BS |
448 | if (ret) |
449 | return ret; | |
450 | ||
3eca809b BS |
451 | clk->base.read = gf100_clk_read; |
452 | clk->base.calc = gf100_clk_calc; | |
453 | clk->base.prog = gf100_clk_prog; | |
454 | clk->base.tidy = gf100_clk_tidy; | |
8aceb7de BS |
455 | return 0; |
456 | } | |
457 | ||
7632b30e BS |
458 | struct nvkm_oclass |
459 | gf100_clk_oclass = { | |
f3867f43 | 460 | .handle = NV_SUBDEV(CLK, 0xc0), |
7632b30e BS |
461 | .ofuncs = &(struct nvkm_ofuncs) { |
462 | .ctor = gf100_clk_ctor, | |
463 | .dtor = _nvkm_clk_dtor, | |
464 | .init = _nvkm_clk_init, | |
465 | .fini = _nvkm_clk_fini, | |
8aceb7de BS |
466 | }, |
467 | }; |