[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#define gf100_clk(p) container_of((p), struct gf100_clk, base)
#include "priv.h"
#include "pll.h"

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

struct gf100_clk_info {
	u32 freq;
	u32 ssel;
	u32 mdiv;
	u32 dsrc;
	u32 ddiv;
	u32 coef;
};

struct gf100_clk {
	struct nvkm_clk base;
	struct gf100_clk_info eng[16];
};

static u32 read_div(struct gf100_clk *, int, u32, u32);

static u32
read_vco(struct gf100_clk *clk, u32 dsrc)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc);
	if (!(ssrc & 0x00000100))
		return nvkm_clk_read(&clk->base, nv_clk_src_sppll0);
	return nvkm_clk_read(&clk->base, nv_clk_src_sppll1);
}

static u32
read_pll(struct gf100_clk *clk, u32 pll)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	u32 coef = nvkm_rd32(device, pll + 0x04);
	u32 P = (coef & 0x003f0000) >> 16;
	u32 N = (coef & 0x0000ff00) >> 8;
	u32 M = (coef & 0x000000ff) >> 0;
	u32 sclk;

	if (!(ctrl & 0x00000001))
		return 0;

	switch (pll) {
	case 0x00e800:
	case 0x00e820:
		sclk = device->crystal;
		P = 1;
		break;
	case 0x132000:
		sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
		break;
	case 0x132020:
		sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
		break;
	case 0x137000:
	case 0x137020:
	case 0x137040:
	case 0x1370e0:
		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
		break;
	default:
		return 0;
	}

	return sclk * N / M / P;
}

static u32
read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));

	switch (ssrc & 0x00000003) {
	case 0:
		if ((ssrc & 0x00030000) != 0x00030000)
			return device->crystal;
		return 108000;
	case 2:
		return 100000;
	case 3:
		if (sctl & 0x80000000) {
			u32 sclk = read_vco(clk, dsrc + (doff * 4));
			u32 sdiv = (sctl & 0x0000003f) + 2;
			return (sclk * 2) / sdiv;
		}

		return read_vco(clk, dsrc + (doff * 4));
	default:
		return 0;
	}
}

static u32
read_clk(struct gf100_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
	u32 ssel = nvkm_rd32(device, 0x137100);
	u32 sclk, sdiv;

	if (ssel & (1 << idx)) {
		if (idx < 7)
			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
		else
			sclk = read_pll(clk, 0x1370e0);
		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	} else {
		sclk = read_div(clk, idx, 0x137160, 0x1371d0);
		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	}

	if (sctl & 0x80000000)
		return (sclk * 2) / sdiv;

	return sclk;
}

static int
gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
{
	struct gf100_clk *clk = gf100_clk(base);
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_device *device = subdev->device;

	switch (src) {
	case nv_clk_src_crystal:
		return device->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_sppll0:
		return read_pll(clk, 0x00e800);
	case nv_clk_src_sppll1:
		return read_pll(clk, 0x00e820);

	case nv_clk_src_mpllsrcref:
		return read_div(clk, 0, 0x137320, 0x137330);
	case nv_clk_src_mpllsrc:
		return read_pll(clk, 0x132020);
	case nv_clk_src_mpll:
		return read_pll(clk, 0x132000);
	case nv_clk_src_mdiv:
		return read_div(clk, 0, 0x137300, 0x137310);
	case nv_clk_src_mem:
		if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
			return nvkm_clk_read(&clk->base, nv_clk_src_mpll);
		return nvkm_clk_read(&clk->base, nv_clk_src_mdiv);

	case nv_clk_src_gpc:
		return read_clk(clk, 0x00);
	case nv_clk_src_rop:
		return read_clk(clk, 0x01);
	case nv_clk_src_hubk07:
		return read_clk(clk, 0x02);
	case nv_clk_src_hubk06:
		return read_clk(clk, 0x07);
	case nv_clk_src_hubk01:
		return read_clk(clk, 0x08);
	case nv_clk_src_copy:
		return read_clk(clk, 0x09);
	case nv_clk_src_daemon:
		return read_clk(clk, 0x0c);
	case nv_clk_src_vdec:
		return read_clk(clk, 0x0e);
	default:
		nvkm_error(subdev, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static u32
calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
{
	u32 div = min((ref * 2) / freq, (u32)65);
	if (div < 2)
		div = 2;

	*ddiv = div - 2;
	return (ref * 2) / div;
}

static u32
calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
{
	u32 sclk;

	/* use one of the fixed frequencies if possible */
	*ddiv = 0x00000000;
	switch (freq) {
	case  27000:
	case 108000:
		*dsrc = 0x00000000;
		if (freq == 108000)
			*dsrc |= 0x00030000;
		return freq;
	case 100000:
		*dsrc = 0x00000002;
		return freq;
	default:
		*dsrc = 0x00000003;
		break;
	}

	/* otherwise, calculate the closest divider */
	sclk = read_vco(clk, 0x137160 + (idx * 4));
	if (idx < 7)
		sclk = calc_div(clk, idx, sclk, freq, ddiv);
	return sclk;
}

static u32
calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
{
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_bios *bios = subdev->device->bios;
	struct nvbios_pll limits;
	int N, M, P, ret;

	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
	if (ret)
		return 0;

	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
	if (!limits.refclk)
		return 0;

	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
	if (ret <= 0)
		return 0;

	*coef = (P << 16) | (N << 8) | M;
	return ret;
}

static int
calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	u32 freq = cstate->domain[dom];
	u32 src0, div0, div1D, div1P = 0;
	u32 clk0, clk1 = 0;

	/* invalid clock domain */
	if (!freq)
		return 0;

	/* first possible path, using only dividers */
	clk0 = calc_src(clk, idx, freq, &src0, &div0);
	clk0 = calc_div(clk, idx, clk0, freq, &div1D);

	/* see if we can get any closer using PLLs */
	if (clk0 != freq && (0x00004387 & (1 << idx))) {
		if (idx <= 7)
			clk1 = calc_pll(clk, idx, freq, &info->coef);
		else
			clk1 = cstate->domain[nv_clk_src_hubk06];
		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
	}

	/* select the method which gets closest to target freq */
	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
		info->dsrc = src0;
		if (div0) {
			info->ddiv |= 0x80000000;
			info->ddiv |= div0 << 8;
			info->ddiv |= div0;
		}
		if (div1D) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1D;
		}
		info->ssel = info->coef = 0;
		info->freq = clk0;
	} else {
		if (div1P) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1P << 8;
		}
		info->ssel = (1 << idx);
		info->freq = clk1;
	}

	return 0;
}

static int
gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
{
	struct gf100_clk *clk = gf100_clk(base);
	int ret;

	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
	    (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) ||
	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static void
gf100_clk_prog_0(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (idx < 7 && !info->ssel) {
		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
	}
}

static void
gf100_clk_prog_1(struct gf100_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
	nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
			break;
	);
}

static void
gf100_clk_prog_2(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	const u32 addr = 0x137000 + (idx * 0x20);
	if (idx <= 7) {
		nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
		if (info->coef) {
			nvkm_wr32(device, addr + 0x04, info->coef);
			nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
			nvkm_msec(device, 2000,
				if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
					break;
			);
			nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
		}
	}
}

static void
gf100_clk_prog_3(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (info->ssel) {
		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
		nvkm_msec(device, 2000,
			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
			if (tmp == info->ssel)
				break;
		);
	}
}

static void
gf100_clk_prog_4(struct gf100_clk *clk, int idx)
{
	struct gf100_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
}

static int
gf100_clk_prog(struct nvkm_clk *base)
{
	struct gf100_clk *clk = gf100_clk(base);
	struct {
		void (*exec)(struct gf100_clk *, int);
	} stage[] = {
		{ gf100_clk_prog_0 }, /* div programming */
		{ gf100_clk_prog_1 }, /* select div mode */
		{ gf100_clk_prog_2 }, /* (maybe) program pll */
		{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
		{ gf100_clk_prog_4 }, /* final divider */
	};
	int i, j;

	for (i = 0; i < ARRAY_SIZE(stage); i++) {
		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
			if (!clk->eng[j].freq)
				continue;
			stage[i].exec(clk, j);
		}
	}

	return 0;
}

static void
gf100_clk_tidy(struct nvkm_clk *base)
{
	struct gf100_clk *clk = gf100_clk(base);
	memset(clk->eng, 0x00, sizeof(clk->eng));
}

static const struct nvkm_clk_func
gf100_clk = {
	.read = gf100_clk_read,
	.calc = gf100_clk_calc,
	.prog = gf100_clk_prog,
	.tidy = gf100_clk_tidy,
	.domains = {
		{ nv_clk_src_crystal, 0xff },
		{ nv_clk_src_href   , 0xff },
		{ nv_clk_src_hubk06 , 0x00 },
		{ nv_clk_src_hubk01 , 0x01 },
		{ nv_clk_src_copy   , 0x02 },
		{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
		{ nv_clk_src_rop    , 0x04 },
		{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
		{ nv_clk_src_vdec   , 0x06 },
		{ nv_clk_src_daemon , 0x0a },
		{ nv_clk_src_hubk07 , 0x0b },
		{ nv_clk_src_max }
	}
};

int
gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
{
	struct gf100_clk *clk;

	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
		return -ENOMEM;
	*pclk = &clk->base;

	return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base);
}
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
6625f55c BS	24	#define gf100_clk(p) container_of((p), struct gf100_clk, base)
6625f55c BS	25	#include "priv.h"
7632b30e BS	26	#include "pll.h"
7632b30e BS	27
70790f4f BS	28	#include <subdev/bios.h>
70790f4f BS	29	#include <subdev/bios/pll.h>
7c856522	30	#include <subdev/timer.h>
70790f4f	31
7632b30e	32	struct gf100_clk_info {
7c856522 BS	33	u32 freq;
	34	u32 ssel;
	35	u32 mdiv;
	36	u32 dsrc;
	37	u32 ddiv;
	38	u32 coef;
	39	};
	40
3eca809b	41	struct gf100_clk {
7632b30e BS	42	struct nvkm_clk base;
7632b30e BS	43	struct gf100_clk_info eng[16];
7c856522 BS	44	};
7c856522 BS	45
3eca809b	46	static u32 read_div(struct gf100_clk *, int, u32, u32);
7c856522 BS	47
7c856522 BS	48	static u32
3eca809b	49	read_vco(struct gf100_clk *clk, u32 dsrc)
7c856522	50	{
822ad79f BS	51	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	52	u32 ssrc = nvkm_rd32(device, dsrc);
7c856522	53	if (!(ssrc & 0x00000100))
6625f55c BS	54	return nvkm_clk_read(&clk->base, nv_clk_src_sppll0);
6625f55c BS	55	return nvkm_clk_read(&clk->base, nv_clk_src_sppll1);
7c856522 BS	56	}
	57
	58	static u32
3eca809b	59	read_pll(struct gf100_clk *clk, u32 pll)
7c856522	60	{
822ad79f BS	61	struct nvkm_device *device = clk->base.subdev.device;
	62	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	63	u32 coef = nvkm_rd32(device, pll + 0x04);
7c856522 BS	64	u32 P = (coef & 0x003f0000) >> 16;
	65	u32 N = (coef & 0x0000ff00) >> 8;
	66	u32 M = (coef & 0x000000ff) >> 0;
	67	u32 sclk;
	68
	69	if (!(ctrl & 0x00000001))
	70	return 0;
	71
	72	switch (pll) {
	73	case 0x00e800:
	74	case 0x00e820:
822ad79f	75	sclk = device->crystal;
7c856522 BS	76	P = 1;
	77	break;
	78	case 0x132000:
6625f55c	79	sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
7c856522 BS	80	break;
7c856522 BS	81	case 0x132020:
6625f55c	82	sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
7c856522 BS	83	break;
	84	case 0x137000:
	85	case 0x137020:
	86	case 0x137040:
	87	case 0x1370e0:
3eca809b	88	sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
7c856522 BS	89	break;
	90	default:
	91	return 0;
	92	}
	93
	94	return sclk * N / M / P;
	95	}
	96
	97	static u32
3eca809b	98	read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
7c856522	99	{
822ad79f BS	100	struct nvkm_device *device = clk->base.subdev.device;
	101	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
	102	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
7c856522 BS	103
	104	switch (ssrc & 0x00000003) {
	105	case 0:
	106	if ((ssrc & 0x00030000) != 0x00030000)
822ad79f	107	return device->crystal;
7c856522 BS	108	return 108000;
	109	case 2:
	110	return 100000;
	111	case 3:
	112	if (sctl & 0x80000000) {
3eca809b	113	u32 sclk = read_vco(clk, dsrc + (doff * 4));
7c856522 BS	114	u32 sdiv = (sctl & 0x0000003f) + 2;
	115	return (sclk * 2) / sdiv;
	116	}
	117
3eca809b	118	return read_vco(clk, dsrc + (doff * 4));
7c856522 BS	119	default:
	120	return 0;
	121	}
	122	}
	123
	124	static u32
3eca809b	125	read_clk(struct gf100_clk *clk, int idx)
7c856522	126	{
822ad79f BS	127	struct nvkm_device *device = clk->base.subdev.device;
	128	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
	129	u32 ssel = nvkm_rd32(device, 0x137100);
7c856522 BS	130	u32 sclk, sdiv;
7c856522 BS	131
3eca809b BS	132	if (ssel & (1 << idx)) {
	133	if (idx < 7)
	134	sclk = read_pll(clk, 0x137000 + (idx * 0x20));
7c856522	135	else
3eca809b	136	sclk = read_pll(clk, 0x1370e0);
7c856522 BS	137	sdiv = ((sctl & 0x00003f00) >> 8) + 2;
7c856522 BS	138	} else {
3eca809b	139	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	140	sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	141	}
	142
	143	if (sctl & 0x80000000)
	144	return (sclk * 2) / sdiv;
	145
	146	return sclk;
	147	}
	148
	149	static int
6625f55c	150	gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
7c856522	151	{
6625f55c	152	struct gf100_clk *clk = gf100_clk(base);
b907649e BS	153	struct nvkm_subdev *subdev = &clk->base.subdev;
b907649e BS	154	struct nvkm_device *device = subdev->device;
7c856522 BS	155
	156	switch (src) {
	157	case nv_clk_src_crystal:
	158	return device->crystal;
	159	case nv_clk_src_href:
	160	return 100000;
	161	case nv_clk_src_sppll0:
3eca809b	162	return read_pll(clk, 0x00e800);
7c856522	163	case nv_clk_src_sppll1:
3eca809b	164	return read_pll(clk, 0x00e820);
7c856522 BS	165
7c856522 BS	166	case nv_clk_src_mpllsrcref:
3eca809b	167	return read_div(clk, 0, 0x137320, 0x137330);
7c856522	168	case nv_clk_src_mpllsrc:
3eca809b	169	return read_pll(clk, 0x132020);
7c856522	170	case nv_clk_src_mpll:
3eca809b	171	return read_pll(clk, 0x132000);
7c856522	172	case nv_clk_src_mdiv:
3eca809b	173	return read_div(clk, 0, 0x137300, 0x137310);
7c856522	174	case nv_clk_src_mem:
822ad79f	175	if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
6625f55c BS	176	return nvkm_clk_read(&clk->base, nv_clk_src_mpll);
6625f55c BS	177	return nvkm_clk_read(&clk->base, nv_clk_src_mdiv);
7c856522 BS	178
7c856522 BS	179	case nv_clk_src_gpc:
3eca809b	180	return read_clk(clk, 0x00);
7c856522	181	case nv_clk_src_rop:
3eca809b	182	return read_clk(clk, 0x01);
7c856522	183	case nv_clk_src_hubk07:
3eca809b	184	return read_clk(clk, 0x02);
7c856522	185	case nv_clk_src_hubk06:
3eca809b	186	return read_clk(clk, 0x07);
7c856522	187	case nv_clk_src_hubk01:
3eca809b	188	return read_clk(clk, 0x08);
7c856522	189	case nv_clk_src_copy:
3eca809b	190	return read_clk(clk, 0x09);
7c856522	191	case nv_clk_src_daemon:
3eca809b	192	return read_clk(clk, 0x0c);
7c856522	193	case nv_clk_src_vdec:
3eca809b	194	return read_clk(clk, 0x0e);
7c856522	195	default:
b907649e	196	nvkm_error(subdev, "invalid clock source %d\n", src);
7c856522 BS	197	return -EINVAL;
	198	}
	199	}
	200
	201	static u32
3eca809b	202	calc_div(struct gf100_clk clk, int idx, u32 ref, u32 freq, u32 ddiv)
7c856522 BS	203	{
	204	u32 div = min((ref * 2) / freq, (u32)65);
	205	if (div < 2)
	206	div = 2;
	207
	208	*ddiv = div - 2;
	209	return (ref * 2) / div;
	210	}
	211
	212	static u32
3eca809b	213	calc_src(struct gf100_clk clk, int idx, u32 freq, u32 dsrc, u32 *ddiv)
7c856522 BS	214	{
	215	u32 sclk;
	216
	217	/* use one of the fixed frequencies if possible */
	218	*ddiv = 0x00000000;
	219	switch (freq) {
	220	case 27000:
	221	case 108000:
	222	*dsrc = 0x00000000;
	223	if (freq == 108000)
	224	*dsrc \|= 0x00030000;
	225	return freq;
	226	case 100000:
	227	*dsrc = 0x00000002;
	228	return freq;
	229	default:
	230	*dsrc = 0x00000003;
	231	break;
	232	}
	233
	234	/* otherwise, calculate the closest divider */
3eca809b BS	235	sclk = read_vco(clk, 0x137160 + (idx * 4));
	236	if (idx < 7)
	237	sclk = calc_div(clk, idx, sclk, freq, ddiv);
7c856522 BS	238	return sclk;
	239	}
	240
	241	static u32
3eca809b	242	calc_pll(struct gf100_clk clk, int idx, u32 freq, u32 coef)
7c856522	243	{
46484438 BS	244	struct nvkm_subdev *subdev = &clk->base.subdev;
46484438 BS	245	struct nvkm_bios *bios = subdev->device->bios;
7c856522 BS	246	struct nvbios_pll limits;
	247	int N, M, P, ret;
	248
3eca809b	249	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
7c856522 BS	250	if (ret)
	251	return 0;
	252
3eca809b	253	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
7c856522 BS	254	if (!limits.refclk)
	255	return 0;
	256
46484438	257	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
7c856522 BS	258	if (ret <= 0)
	259	return 0;
	260
	261	*coef = (P << 16) \| (N << 8) \| M;
	262	return ret;
	263	}
	264
	265	static int
3eca809b	266	calc_clk(struct gf100_clk clk, struct nvkm_cstate cstate, int idx, int dom)
7c856522	267	{
3eca809b	268	struct gf100_clk_info *info = &clk->eng[idx];
7c856522 BS	269	u32 freq = cstate->domain[dom];
	270	u32 src0, div0, div1D, div1P = 0;
	271	u32 clk0, clk1 = 0;
	272
	273	/* invalid clock domain */
	274	if (!freq)
	275	return 0;
	276
	277	/* first possible path, using only dividers */
3eca809b BS	278	clk0 = calc_src(clk, idx, freq, &src0, &div0);
3eca809b BS	279	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
7c856522 BS	280
7c856522 BS	281	/* see if we can get any closer using PLLs */
3eca809b BS	282	if (clk0 != freq && (0x00004387 & (1 << idx))) {
	283	if (idx <= 7)
	284	clk1 = calc_pll(clk, idx, freq, &info->coef);
7c856522 BS	285	else
7c856522 BS	286	clk1 = cstate->domain[nv_clk_src_hubk06];
3eca809b	287	clk1 = calc_div(clk, idx, clk1, freq, &div1P);
7c856522 BS	288	}
	289
	290	/* select the method which gets closest to target freq */
	291	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
	292	info->dsrc = src0;
	293	if (div0) {
	294	info->ddiv \|= 0x80000000;
	295	info->ddiv \|= div0 << 8;
	296	info->ddiv \|= div0;
	297	}
	298	if (div1D) {
	299	info->mdiv \|= 0x80000000;
	300	info->mdiv \|= div1D;
	301	}
	302	info->ssel = info->coef = 0;
	303	info->freq = clk0;
	304	} else {
	305	if (div1P) {
	306	info->mdiv \|= 0x80000000;
	307	info->mdiv \|= div1P << 8;
	308	}
3eca809b	309	info->ssel = (1 << idx);
7c856522 BS	310	info->freq = clk1;
	311	}
	312
	313	return 0;
	314	}
	315
	316	static int
6625f55c	317	gf100_clk_calc(struct nvkm_clk base, struct nvkm_cstate cstate)
7c856522	318	{
6625f55c	319	struct gf100_clk *clk = gf100_clk(base);
7c856522 BS	320	int ret;
7c856522 BS	321
3eca809b BS	322	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) \|\|
	323	(ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) \|\|
	324	(ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) \|\|
	325	(ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) \|\|
	326	(ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) \|\|
	327	(ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) \|\|
	328	(ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) \|\|
	329	(ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
7c856522 BS	330	return ret;
	331
	332	return 0;
	333	}
	334
	335	static void
3eca809b	336	gf100_clk_prog_0(struct gf100_clk *clk, int idx)
7c856522	337	{
3eca809b	338	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	339	struct nvkm_device *device = clk->base.subdev.device;
3eca809b	340	if (idx < 7 && !info->ssel) {
822ad79f BS	341	nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
822ad79f BS	342	nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
7c856522 BS	343	}
	344	}
	345
	346	static void
3eca809b	347	gf100_clk_prog_1(struct gf100_clk *clk, int idx)
7c856522	348	{
822ad79f BS	349	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	350	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
6979c630 BS	351	nvkm_msec(device, 2000,
	352	if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
	353	break;
	354	);
7c856522 BS	355	}
	356
	357	static void
3eca809b	358	gf100_clk_prog_2(struct gf100_clk *clk, int idx)
7c856522	359	{
3eca809b	360	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	361	struct nvkm_device *device = clk->base.subdev.device;
3eca809b BS	362	const u32 addr = 0x137000 + (idx * 0x20);
3eca809b BS	363	if (idx <= 7) {
822ad79f BS	364	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
822ad79f BS	365	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
7c856522	366	if (info->coef) {
822ad79f BS	367	nvkm_wr32(device, addr + 0x04, info->coef);
822ad79f BS	368	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
6979c630 BS	369	nvkm_msec(device, 2000,
	370	if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
	371	break;
	372	);
822ad79f	373	nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
7c856522 BS	374	}
	375	}
	376	}
	377
	378	static void
3eca809b	379	gf100_clk_prog_3(struct gf100_clk *clk, int idx)
7c856522	380	{
3eca809b	381	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f	382	struct nvkm_device *device = clk->base.subdev.device;
7c856522	383	if (info->ssel) {
822ad79f	384	nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
6979c630 BS	385	nvkm_msec(device, 2000,
	386	u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
	387	if (tmp == info->ssel)
	388	break;
	389	);
7c856522 BS	390	}
	391	}
	392
	393	static void
3eca809b	394	gf100_clk_prog_4(struct gf100_clk *clk, int idx)
7c856522	395	{
3eca809b	396	struct gf100_clk_info *info = &clk->eng[idx];
822ad79f BS	397	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	398	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
7c856522 BS	399	}
	400
	401	static int
6625f55c	402	gf100_clk_prog(struct nvkm_clk *base)
7c856522	403	{
6625f55c	404	struct gf100_clk *clk = gf100_clk(base);
7c856522	405	struct {
3eca809b	406	void (exec)(struct gf100_clk , int);
7c856522	407	} stage[] = {
7632b30e BS	408	{ gf100_clk_prog_0 }, /* div programming */
	409	{ gf100_clk_prog_1 }, /* select div mode */
	410	{ gf100_clk_prog_2 }, /* (maybe) program pll */
	411	{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
	412	{ gf100_clk_prog_4 }, /* final divider */
7c856522 BS	413	};
	414	int i, j;
	415
	416	for (i = 0; i < ARRAY_SIZE(stage); i++) {
3eca809b BS	417	for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
3eca809b BS	418	if (!clk->eng[j].freq)
7c856522	419	continue;
3eca809b	420	stage[i].exec(clk, j);
7c856522 BS	421	}
	422	}
	423
	424	return 0;
	425	}
	426
	427	static void
6625f55c	428	gf100_clk_tidy(struct nvkm_clk *base)
7c856522	429	{
6625f55c	430	struct gf100_clk *clk = gf100_clk(base);
3eca809b	431	memset(clk->eng, 0x00, sizeof(clk->eng));
7c856522 BS	432	}
7c856522 BS	433
6625f55c BS	434	static const struct nvkm_clk_func
	435	gf100_clk = {
	436	.read = gf100_clk_read,
	437	.calc = gf100_clk_calc,
	438	.prog = gf100_clk_prog,
	439	.tidy = gf100_clk_tidy,
	440	.domains = {
	441	{ nv_clk_src_crystal, 0xff },
	442	{ nv_clk_src_href , 0xff },
	443	{ nv_clk_src_hubk06 , 0x00 },
	444	{ nv_clk_src_hubk01 , 0x01 },
	445	{ nv_clk_src_copy , 0x02 },
	446	{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
	447	{ nv_clk_src_rop , 0x04 },
	448	{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
	449	{ nv_clk_src_vdec , 0x06 },
	450	{ nv_clk_src_daemon , 0x0a },
	451	{ nv_clk_src_hubk07 , 0x0b },
	452	{ nv_clk_src_max }
	453	}
8aceb7de BS	454	};
8aceb7de BS	455
6625f55c BS	456	int
6625f55c BS	457	gf100_clk_new(struct nvkm_device device, int index, struct nvkm_clk *pclk)
8aceb7de	458	{
3eca809b	459	struct gf100_clk *clk;
8aceb7de	460
6625f55c BS	461	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
	462	return -ENOMEM;
	463	*pclk = &clk->base;
8aceb7de	464
6625f55c	465	return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base);
8aceb7de	466	}