[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gk104.c

/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#define gk104_clk(p) container_of((p), struct gk104_clk, base)
#include "priv.h"
#include "pll.h"

#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

struct gk104_clk_info {
	u32 freq;
	u32 ssel;
	u32 mdiv;
	u32 dsrc;
	u32 ddiv;
	u32 coef;
};

struct gk104_clk {
	struct nvkm_clk base;
	struct gk104_clk_info eng[16];
};

static u32 read_div(struct gk104_clk *, int, u32, u32);
static u32 read_pll(struct gk104_clk *, u32);

static u32
read_vco(struct gk104_clk *clk, u32 dsrc)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc);
	if (!(ssrc & 0x00000100))
		return read_pll(clk, 0x00e800);
	return read_pll(clk, 0x00e820);
}

static u32
read_pll(struct gk104_clk *clk, u32 pll)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	u32 coef = nvkm_rd32(device, pll + 0x04);
	u32 P = (coef & 0x003f0000) >> 16;
	u32 N = (coef & 0x0000ff00) >> 8;
	u32 M = (coef & 0x000000ff) >> 0;
	u32 sclk;
	u16 fN = 0xf000;

	if (!(ctrl & 0x00000001))
		return 0;

	switch (pll) {
	case 0x00e800:
	case 0x00e820:
		sclk = device->crystal;
		P = 1;
		break;
	case 0x132000:
		sclk = read_pll(clk, 0x132020);
		P = (coef & 0x10000000) ? 2 : 1;
		break;
	case 0x132020:
		sclk = read_div(clk, 0, 0x137320, 0x137330);
		fN   = nvkm_rd32(device, pll + 0x10) >> 16;
		break;
	case 0x137000:
	case 0x137020:
	case 0x137040:
	case 0x1370e0:
		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
		break;
	default:
		return 0;
	}

	if (P == 0)
		P = 1;

	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
	return sclk / (M * P);
}

static u32
read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));

	switch (ssrc & 0x00000003) {
	case 0:
		if ((ssrc & 0x00030000) != 0x00030000)
			return device->crystal;
		return 108000;
	case 2:
		return 100000;
	case 3:
		if (sctl & 0x80000000) {
			u32 sclk = read_vco(clk, dsrc + (doff * 4));
			u32 sdiv = (sctl & 0x0000003f) + 2;
			return (sclk * 2) / sdiv;
		}

		return read_vco(clk, dsrc + (doff * 4));
	default:
		return 0;
	}
}

static u32
read_mem(struct gk104_clk *clk)
{
	struct nvkm_device *device = clk->base.subdev.device;
	switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) {
	case 1: return read_pll(clk, 0x132020);
	case 2: return read_pll(clk, 0x132000);
	default:
		return 0;
	}
}

static u32
read_clk(struct gk104_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
	u32 sclk, sdiv;

	if (idx < 7) {
		u32 ssel = nvkm_rd32(device, 0x137100);
		if (ssel & (1 << idx)) {
			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
			sdiv = 1;
		} else {
			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
			sdiv = 0;
		}
	} else {
		u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04));
		if ((ssrc & 0x00000003) == 0x00000003) {
			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
			if (ssrc & 0x00000100) {
				if (ssrc & 0x40000000)
					sclk = read_pll(clk, 0x1370e0);
				sdiv = 1;
			} else {
				sdiv = 0;
			}
		} else {
			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
			sdiv = 0;
		}
	}

	if (sctl & 0x80000000) {
		if (sdiv)
			sdiv = ((sctl & 0x00003f00) >> 8) + 2;
		else
			sdiv = ((sctl & 0x0000003f) >> 0) + 2;
		return (sclk * 2) / sdiv;
	}

	return sclk;
}

static int
gk104_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
{
	struct gk104_clk *clk = gk104_clk(base);
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_device *device = subdev->device;

	switch (src) {
	case nv_clk_src_crystal:
		return device->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_mem:
		return read_mem(clk);
	case nv_clk_src_gpc:
		return read_clk(clk, 0x00);
	case nv_clk_src_rop:
		return read_clk(clk, 0x01);
	case nv_clk_src_hubk07:
		return read_clk(clk, 0x02);
	case nv_clk_src_hubk06:
		return read_clk(clk, 0x07);
	case nv_clk_src_hubk01:
		return read_clk(clk, 0x08);
	case nv_clk_src_pmu:
		return read_clk(clk, 0x0c);
	case nv_clk_src_vdec:
		return read_clk(clk, 0x0e);
	default:
		nvkm_error(subdev, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static u32
calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
{
	u32 div = min((ref * 2) / freq, (u32)65);
	if (div < 2)
		div = 2;

	*ddiv = div - 2;
	return (ref * 2) / div;
}

static u32
calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
{
	u32 sclk;

	/* use one of the fixed frequencies if possible */
	*ddiv = 0x00000000;
	switch (freq) {
	case  27000:
	case 108000:
		*dsrc = 0x00000000;
		if (freq == 108000)
			*dsrc |= 0x00030000;
		return freq;
	case 100000:
		*dsrc = 0x00000002;
		return freq;
	default:
		*dsrc = 0x00000003;
		break;
	}

	/* otherwise, calculate the closest divider */
	sclk = read_vco(clk, 0x137160 + (idx * 4));
	if (idx < 7)
		sclk = calc_div(clk, idx, sclk, freq, ddiv);
	return sclk;
}

static u32
calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
{
	struct nvkm_subdev *subdev = &clk->base.subdev;
	struct nvkm_bios *bios = subdev->device->bios;
	struct nvbios_pll limits;
	int N, M, P, ret;

	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
	if (ret)
		return 0;

	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
	if (!limits.refclk)
		return 0;

	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
	if (ret <= 0)
		return 0;

	*coef = (P << 16) | (N << 8) | M;
	return ret;
}

static int
calc_clk(struct gk104_clk *clk,
	 struct nvkm_cstate *cstate, int idx, int dom)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	u32 freq = cstate->domain[dom];
	u32 src0, div0, div1D, div1P = 0;
	u32 clk0, clk1 = 0;

	/* invalid clock domain */
	if (!freq)
		return 0;

	/* first possible path, using only dividers */
	clk0 = calc_src(clk, idx, freq, &src0, &div0);
	clk0 = calc_div(clk, idx, clk0, freq, &div1D);

	/* see if we can get any closer using PLLs */
	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {
		if (idx <= 7)
			clk1 = calc_pll(clk, idx, freq, &info->coef);
		else
			clk1 = cstate->domain[nv_clk_src_hubk06];
		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
	}

	/* select the method which gets closest to target freq */
	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
		info->dsrc = src0;
		if (div0) {
			info->ddiv |= 0x80000000;
			info->ddiv |= div0;
		}
		if (div1D) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1D;
		}
		info->ssel = 0;
		info->freq = clk0;
	} else {
		if (div1P) {
			info->mdiv |= 0x80000000;
			info->mdiv |= div1P << 8;
		}
		info->ssel = (1 << idx);
		info->dsrc = 0x40000100;
		info->freq = clk1;
	}

	return 0;
}

static int
gk104_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
{
	struct gk104_clk *clk = gk104_clk(base);
	int ret;

	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) ||
	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static void
gk104_clk_prog_0(struct gk104_clk *clk, int idx)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (!info->ssel) {
		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
	}
}

static void
gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
	nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
			break;
	);
}

static void
gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)
{
	struct nvkm_device *device = clk->base.subdev.device;
	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);
}

static void
gk104_clk_prog_2(struct gk104_clk *clk, int idx)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	const u32 addr = 0x137000 + (idx * 0x20);
	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
	if (info->coef) {
		nvkm_wr32(device, addr + 0x04, info->coef);
		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
		nvkm_msec(device, 2000,
			if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
				break;
		);
		nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
	}
}

static void
gk104_clk_prog_3(struct gk104_clk *clk, int idx)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (info->ssel)
		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
	else
		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
}

static void
gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (info->ssel) {
		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
		nvkm_msec(device, 2000,
			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
			if (tmp == info->ssel)
				break;
		);
	}
}

static void
gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
{
	struct gk104_clk_info *info = &clk->eng[idx];
	struct nvkm_device *device = clk->base.subdev.device;
	if (info->ssel) {
		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);
		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);
	}
}

static int
gk104_clk_prog(struct nvkm_clk *base)
{
	struct gk104_clk *clk = gk104_clk(base);
	struct {
		u32 mask;
		void (*exec)(struct gk104_clk *, int);
	} stage[] = {
		{ 0x007f, gk104_clk_prog_0   }, /* div programming */
		{ 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
		{ 0xff80, gk104_clk_prog_1_1 },
		{ 0x00ff, gk104_clk_prog_2   }, /* (maybe) program pll */
		{ 0xff80, gk104_clk_prog_3   }, /* final divider */
		{ 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
		{ 0xff80, gk104_clk_prog_4_1 },
	};
	int i, j;

	for (i = 0; i < ARRAY_SIZE(stage); i++) {
		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
			if (!(stage[i].mask & (1 << j)))
				continue;
			if (!clk->eng[j].freq)
				continue;
			stage[i].exec(clk, j);
		}
	}

	return 0;
}

static void
gk104_clk_tidy(struct nvkm_clk *base)
{
	struct gk104_clk *clk = gk104_clk(base);
	memset(clk->eng, 0x00, sizeof(clk->eng));
}

static const struct nvkm_clk_func
gk104_clk = {
	.read = gk104_clk_read,
	.calc = gk104_clk_calc,
	.prog = gk104_clk_prog,
	.tidy = gk104_clk_tidy,
	.domains = {
		{ nv_clk_src_crystal, 0xff },
		{ nv_clk_src_href   , 0xff },
		{ nv_clk_src_gpc    , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
		{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
		{ nv_clk_src_rop    , 0x02, NVKM_CLK_DOM_FLAG_CORE },
		{ nv_clk_src_mem    , 0x03, 0, "memory", 500 },
		{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
		{ nv_clk_src_hubk01 , 0x05 },
		{ nv_clk_src_vdec   , 0x06 },
		{ nv_clk_src_pmu    , 0x07 },
		{ nv_clk_src_max }
	}
};

int
gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
{
	struct gk104_clk *clk;

	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
		return -ENOMEM;
	*pclk = &clk->base;

	return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base);
}
Commit	Line	Data
7c856522 BS	1	/*
	2	* Copyright 2013 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
6625f55c BS	24	#define gk104_clk(p) container_of((p), struct gk104_clk, base)
6625f55c BS	25	#include "priv.h"
7632b30e BS	26	#include "pll.h"
7632b30e BS	27
7c856522 BS	28	#include <subdev/timer.h>
	29	#include <subdev/bios.h>
	30	#include <subdev/bios/pll.h>
	31
7632b30e	32	struct gk104_clk_info {
7c856522 BS	33	u32 freq;
	34	u32 ssel;
	35	u32 mdiv;
	36	u32 dsrc;
	37	u32 ddiv;
	38	u32 coef;
	39	};
	40
3eca809b	41	struct gk104_clk {
7632b30e BS	42	struct nvkm_clk base;
7632b30e BS	43	struct gk104_clk_info eng[16];
7c856522 BS	44	};
7c856522 BS	45
3eca809b BS	46	static u32 read_div(struct gk104_clk *, int, u32, u32);
3eca809b BS	47	static u32 read_pll(struct gk104_clk *, u32);
7c856522 BS	48
7c856522 BS	49	static u32
3eca809b	50	read_vco(struct gk104_clk *clk, u32 dsrc)
7c856522	51	{
822ad79f BS	52	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	53	u32 ssrc = nvkm_rd32(device, dsrc);
7c856522	54	if (!(ssrc & 0x00000100))
3eca809b BS	55	return read_pll(clk, 0x00e800);
3eca809b BS	56	return read_pll(clk, 0x00e820);
7c856522 BS	57	}
	58
	59	static u32
3eca809b	60	read_pll(struct gk104_clk *clk, u32 pll)
7c856522	61	{
822ad79f BS	62	struct nvkm_device *device = clk->base.subdev.device;
	63	u32 ctrl = nvkm_rd32(device, pll + 0x00);
	64	u32 coef = nvkm_rd32(device, pll + 0x04);
7c856522 BS	65	u32 P = (coef & 0x003f0000) >> 16;
	66	u32 N = (coef & 0x0000ff00) >> 8;
	67	u32 M = (coef & 0x000000ff) >> 0;
	68	u32 sclk;
	69	u16 fN = 0xf000;
	70
	71	if (!(ctrl & 0x00000001))
	72	return 0;
	73
	74	switch (pll) {
	75	case 0x00e800:
	76	case 0x00e820:
822ad79f	77	sclk = device->crystal;
7c856522 BS	78	P = 1;
	79	break;
	80	case 0x132000:
3eca809b	81	sclk = read_pll(clk, 0x132020);
7c856522 BS	82	P = (coef & 0x10000000) ? 2 : 1;
	83	break;
	84	case 0x132020:
3eca809b	85	sclk = read_div(clk, 0, 0x137320, 0x137330);
822ad79f	86	fN = nvkm_rd32(device, pll + 0x10) >> 16;
7c856522 BS	87	break;
	88	case 0x137000:
	89	case 0x137020:
	90	case 0x137040:
	91	case 0x1370e0:
3eca809b	92	sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
7c856522 BS	93	break;
	94	default:
	95	return 0;
	96	}
	97
	98	if (P == 0)
	99	P = 1;
	100
	101	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
	102	return sclk / (M * P);
	103	}
	104
	105	static u32
3eca809b	106	read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl)
7c856522	107	{
822ad79f BS	108	struct nvkm_device *device = clk->base.subdev.device;
	109	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
	110	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
7c856522 BS	111
	112	switch (ssrc & 0x00000003) {
	113	case 0:
	114	if ((ssrc & 0x00030000) != 0x00030000)
822ad79f	115	return device->crystal;
7c856522 BS	116	return 108000;
	117	case 2:
	118	return 100000;
	119	case 3:
	120	if (sctl & 0x80000000) {
3eca809b	121	u32 sclk = read_vco(clk, dsrc + (doff * 4));
7c856522 BS	122	u32 sdiv = (sctl & 0x0000003f) + 2;
	123	return (sclk * 2) / sdiv;
	124	}
	125
3eca809b	126	return read_vco(clk, dsrc + (doff * 4));
7c856522 BS	127	default:
	128	return 0;
	129	}
	130	}
	131
	132	static u32
3eca809b	133	read_mem(struct gk104_clk *clk)
7c856522	134	{
822ad79f BS	135	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	136	switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) {
3eca809b BS	137	case 1: return read_pll(clk, 0x132020);
3eca809b BS	138	case 2: return read_pll(clk, 0x132000);
7c856522 BS	139	default:
	140	return 0;
	141	}
	142	}
	143
	144	static u32
3eca809b	145	read_clk(struct gk104_clk *clk, int idx)
7c856522	146	{
822ad79f BS	147	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	148	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
7c856522 BS	149	u32 sclk, sdiv;
7c856522 BS	150
3eca809b	151	if (idx < 7) {
822ad79f	152	u32 ssel = nvkm_rd32(device, 0x137100);
3eca809b BS	153	if (ssel & (1 << idx)) {
3eca809b BS	154	sclk = read_pll(clk, 0x137000 + (idx * 0x20));
7c856522 BS	155	sdiv = 1;
7c856522 BS	156	} else {
3eca809b	157	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	158	sdiv = 0;
	159	}
	160	} else {
822ad79f	161	u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04));
7c856522	162	if ((ssrc & 0x00000003) == 0x00000003) {
3eca809b	163	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	164	if (ssrc & 0x00000100) {
7c856522 BS	165	if (ssrc & 0x40000000)
3eca809b	166	sclk = read_pll(clk, 0x1370e0);
7c856522 BS	167	sdiv = 1;
	168	} else {
	169	sdiv = 0;
	170	}
	171	} else {
3eca809b	172	sclk = read_div(clk, idx, 0x137160, 0x1371d0);
7c856522 BS	173	sdiv = 0;
	174	}
	175	}
	176
	177	if (sctl & 0x80000000) {
	178	if (sdiv)
	179	sdiv = ((sctl & 0x00003f00) >> 8) + 2;
	180	else
	181	sdiv = ((sctl & 0x0000003f) >> 0) + 2;
	182	return (sclk * 2) / sdiv;
	183	}
	184
	185	return sclk;
	186	}
	187
	188	static int
6625f55c	189	gk104_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
7c856522	190	{
6625f55c	191	struct gk104_clk *clk = gk104_clk(base);
b907649e BS	192	struct nvkm_subdev *subdev = &clk->base.subdev;
b907649e BS	193	struct nvkm_device *device = subdev->device;
7c856522 BS	194
	195	switch (src) {
	196	case nv_clk_src_crystal:
	197	return device->crystal;
	198	case nv_clk_src_href:
	199	return 100000;
	200	case nv_clk_src_mem:
3eca809b	201	return read_mem(clk);
7c856522	202	case nv_clk_src_gpc:
3eca809b	203	return read_clk(clk, 0x00);
7c856522	204	case nv_clk_src_rop:
3eca809b	205	return read_clk(clk, 0x01);
7c856522	206	case nv_clk_src_hubk07:
3eca809b	207	return read_clk(clk, 0x02);
7c856522	208	case nv_clk_src_hubk06:
3eca809b	209	return read_clk(clk, 0x07);
7c856522	210	case nv_clk_src_hubk01:
3eca809b	211	return read_clk(clk, 0x08);
547dd271	212	case nv_clk_src_pmu:
3eca809b	213	return read_clk(clk, 0x0c);
7c856522	214	case nv_clk_src_vdec:
3eca809b	215	return read_clk(clk, 0x0e);
7c856522	216	default:
b907649e	217	nvkm_error(subdev, "invalid clock source %d\n", src);
7c856522 BS	218	return -EINVAL;
	219	}
	220	}
	221
	222	static u32
3eca809b	223	calc_div(struct gk104_clk clk, int idx, u32 ref, u32 freq, u32 ddiv)
7c856522 BS	224	{
	225	u32 div = min((ref * 2) / freq, (u32)65);
	226	if (div < 2)
	227	div = 2;
	228
	229	*ddiv = div - 2;
	230	return (ref * 2) / div;
	231	}
	232
	233	static u32
3eca809b	234	calc_src(struct gk104_clk clk, int idx, u32 freq, u32 dsrc, u32 *ddiv)
7c856522 BS	235	{
	236	u32 sclk;
	237
	238	/* use one of the fixed frequencies if possible */
	239	*ddiv = 0x00000000;
	240	switch (freq) {
	241	case 27000:
	242	case 108000:
	243	*dsrc = 0x00000000;
	244	if (freq == 108000)
	245	*dsrc \|= 0x00030000;
	246	return freq;
	247	case 100000:
	248	*dsrc = 0x00000002;
	249	return freq;
	250	default:
	251	*dsrc = 0x00000003;
	252	break;
	253	}
	254
	255	/* otherwise, calculate the closest divider */
3eca809b BS	256	sclk = read_vco(clk, 0x137160 + (idx * 4));
	257	if (idx < 7)
	258	sclk = calc_div(clk, idx, sclk, freq, ddiv);
7c856522 BS	259	return sclk;
	260	}
	261
	262	static u32
3eca809b	263	calc_pll(struct gk104_clk clk, int idx, u32 freq, u32 coef)
7c856522	264	{
46484438 BS	265	struct nvkm_subdev *subdev = &clk->base.subdev;
46484438 BS	266	struct nvkm_bios *bios = subdev->device->bios;
7c856522 BS	267	struct nvbios_pll limits;
	268	int N, M, P, ret;
	269
3eca809b	270	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
7c856522 BS	271	if (ret)
	272	return 0;
	273
3eca809b	274	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
7c856522 BS	275	if (!limits.refclk)
	276	return 0;
	277
46484438	278	ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
7c856522 BS	279	if (ret <= 0)
	280	return 0;
	281
	282	*coef = (P << 16) \| (N << 8) \| M;
	283	return ret;
	284	}
	285
	286	static int
3eca809b BS	287	calc_clk(struct gk104_clk *clk,
3eca809b BS	288	struct nvkm_cstate *cstate, int idx, int dom)
7c856522	289	{
3eca809b	290	struct gk104_clk_info *info = &clk->eng[idx];
7c856522 BS	291	u32 freq = cstate->domain[dom];
	292	u32 src0, div0, div1D, div1P = 0;
	293	u32 clk0, clk1 = 0;
	294
	295	/* invalid clock domain */
	296	if (!freq)
	297	return 0;
	298
	299	/* first possible path, using only dividers */
3eca809b BS	300	clk0 = calc_src(clk, idx, freq, &src0, &div0);
3eca809b BS	301	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
7c856522 BS	302
7c856522 BS	303	/* see if we can get any closer using PLLs */
3eca809b BS	304	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {
	305	if (idx <= 7)
	306	clk1 = calc_pll(clk, idx, freq, &info->coef);
7c856522 BS	307	else
7c856522 BS	308	clk1 = cstate->domain[nv_clk_src_hubk06];
3eca809b	309	clk1 = calc_div(clk, idx, clk1, freq, &div1P);
7c856522 BS	310	}
	311
	312	/* select the method which gets closest to target freq */
	313	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
	314	info->dsrc = src0;
	315	if (div0) {
	316	info->ddiv \|= 0x80000000;
7c856522 BS	317	info->ddiv \|= div0;
	318	}
	319	if (div1D) {
	320	info->mdiv \|= 0x80000000;
	321	info->mdiv \|= div1D;
	322	}
	323	info->ssel = 0;
	324	info->freq = clk0;
	325	} else {
	326	if (div1P) {
	327	info->mdiv \|= 0x80000000;
	328	info->mdiv \|= div1P << 8;
	329	}
3eca809b	330	info->ssel = (1 << idx);
7c856522 BS	331	info->dsrc = 0x40000100;
	332	info->freq = clk1;
	333	}
	334
	335	return 0;
	336	}
	337
	338	static int
6625f55c	339	gk104_clk_calc(struct nvkm_clk base, struct nvkm_cstate cstate)
7c856522	340	{
6625f55c	341	struct gk104_clk *clk = gk104_clk(base);
7c856522 BS	342	int ret;
7c856522 BS	343
3eca809b BS	344	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) \|\|
	345	(ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) \|\|
	346	(ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) \|\|
	347	(ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) \|\|
	348	(ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) \|\|
547dd271	349	(ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) \|\|
3eca809b	350	(ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
7c856522 BS	351	return ret;
	352
	353	return 0;
	354	}
	355
	356	static void
3eca809b	357	gk104_clk_prog_0(struct gk104_clk *clk, int idx)
7c856522	358	{
3eca809b	359	struct gk104_clk_info *info = &clk->eng[idx];
822ad79f	360	struct nvkm_device *device = clk->base.subdev.device;
7c856522	361	if (!info->ssel) {
822ad79f BS	362	nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
822ad79f BS	363	nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
7c856522 BS	364	}
	365	}
	366
	367	static void
3eca809b	368	gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
7c856522	369	{
822ad79f BS	370	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	371	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
6979c630 BS	372	nvkm_msec(device, 2000,
	373	if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
	374	break;
	375	);
7c856522 BS	376	}
	377
	378	static void
3eca809b	379	gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)
7c856522	380	{
822ad79f BS	381	struct nvkm_device *device = clk->base.subdev.device;
822ad79f BS	382	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);
7c856522 BS	383	}
	384
	385	static void
3eca809b	386	gk104_clk_prog_2(struct gk104_clk *clk, int idx)
7c856522	387	{
3eca809b	388	struct gk104_clk_info *info = &clk->eng[idx];
822ad79f	389	struct nvkm_device *device = clk->base.subdev.device;
3eca809b	390	const u32 addr = 0x137000 + (idx * 0x20);
822ad79f BS	391	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
822ad79f BS	392	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
7c856522	393	if (info->coef) {
822ad79f BS	394	nvkm_wr32(device, addr + 0x04, info->coef);
822ad79f BS	395	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
6979c630 BS	396	nvkm_msec(device, 2000,
	397	if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
	398	break;
	399	);
822ad79f	400	nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
7c856522 BS	401	}
	402	}
	403
	404	static void
3eca809b	405	gk104_clk_prog_3(struct gk104_clk *clk, int idx)
7c856522	406	{
3eca809b	407	struct gk104_clk_info *info = &clk->eng[idx];
822ad79f	408	struct nvkm_device *device = clk->base.subdev.device;
1968a1e9	409	if (info->ssel)
822ad79f	410	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
1968a1e9	411	else
822ad79f	412	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
7c856522 BS	413	}
	414
	415	static void
3eca809b	416	gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
7c856522	417	{
3eca809b	418	struct gk104_clk_info *info = &clk->eng[idx];
822ad79f	419	struct nvkm_device *device = clk->base.subdev.device;
7c856522	420	if (info->ssel) {
822ad79f	421	nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
6979c630 BS	422	nvkm_msec(device, 2000,
	423	u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
	424	if (tmp == info->ssel)
	425	break;
	426	);
7c856522 BS	427	}
	428	}
	429
	430	static void
3eca809b	431	gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
7c856522	432	{
3eca809b	433	struct gk104_clk_info *info = &clk->eng[idx];
822ad79f	434	struct nvkm_device *device = clk->base.subdev.device;
7c856522	435	if (info->ssel) {
822ad79f BS	436	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);
822ad79f BS	437	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);
7c856522 BS	438	}
	439	}
	440
	441	static int
6625f55c	442	gk104_clk_prog(struct nvkm_clk *base)
7c856522	443	{
6625f55c	444	struct gk104_clk *clk = gk104_clk(base);
7c856522 BS	445	struct {
7c856522 BS	446	u32 mask;
3eca809b	447	void (exec)(struct gk104_clk , int);
7c856522	448	} stage[] = {
7632b30e BS	449	{ 0x007f, gk104_clk_prog_0 }, /* div programming */
	450	{ 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
	451	{ 0xff80, gk104_clk_prog_1_1 },
	452	{ 0x00ff, gk104_clk_prog_2 }, /* (maybe) program pll */
	453	{ 0xff80, gk104_clk_prog_3 }, /* final divider */
	454	{ 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
	455	{ 0xff80, gk104_clk_prog_4_1 },
7c856522 BS	456	};
	457	int i, j;
	458
	459	for (i = 0; i < ARRAY_SIZE(stage); i++) {
3eca809b	460	for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
7c856522 BS	461	if (!(stage[i].mask & (1 << j)))
7c856522 BS	462	continue;
3eca809b	463	if (!clk->eng[j].freq)
7c856522	464	continue;
3eca809b	465	stage[i].exec(clk, j);
7c856522 BS	466	}
	467	}
	468
	469	return 0;
	470	}
	471
	472	static void
6625f55c	473	gk104_clk_tidy(struct nvkm_clk *base)
7c856522	474	{
6625f55c	475	struct gk104_clk *clk = gk104_clk(base);
3eca809b	476	memset(clk->eng, 0x00, sizeof(clk->eng));
7c856522 BS	477	}
7c856522 BS	478
6625f55c BS	479	static const struct nvkm_clk_func
	480	gk104_clk = {
	481	.read = gk104_clk_read,
	482	.calc = gk104_clk_calc,
	483	.prog = gk104_clk_prog,
	484	.tidy = gk104_clk_tidy,
	485	.domains = {
	486	{ nv_clk_src_crystal, 0xff },
	487	{ nv_clk_src_href , 0xff },
	488	{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
	489	{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
	490	{ nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE },
	491	{ nv_clk_src_mem , 0x03, 0, "memory", 500 },
	492	{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
	493	{ nv_clk_src_hubk01 , 0x05 },
	494	{ nv_clk_src_vdec , 0x06 },
547dd271	495	{ nv_clk_src_pmu , 0x07 },
6625f55c BS	496	{ nv_clk_src_max }
6625f55c BS	497	}
7c856522 BS	498	};
7c856522 BS	499
6625f55c BS	500	int
6625f55c BS	501	gk104_clk_new(struct nvkm_device device, int index, struct nvkm_clk *pclk)
7c856522	502	{
3eca809b	503	struct gk104_clk *clk;
7c856522	504
6625f55c BS	505	if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
	506	return -ENOMEM;
	507	*pclk = &clk->base;
7c856522	508
6625f55c	509	return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base);
7c856522	510	}