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8aceb7de BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
3d896d34 | 23 | * Roy Spliet |
8aceb7de | 24 | */ |
7632b30e BS |
25 | #include "gt215.h" |
26 | #include "pll.h" | |
8aceb7de | 27 | |
2fe7eaa0 | 28 | #include <engine/fifo.h> |
70790f4f BS |
29 | #include <subdev/bios.h> |
30 | #include <subdev/bios/pll.h> | |
7c856522 | 31 | #include <subdev/timer.h> |
70790f4f | 32 | |
7632b30e BS |
33 | struct gt215_clk_priv { |
34 | struct nvkm_clk base; | |
35 | struct gt215_clk_info eng[nv_clk_src_max]; | |
8aceb7de BS |
36 | }; |
37 | ||
7632b30e BS |
38 | static u32 read_clk(struct gt215_clk_priv *, int, bool); |
39 | static u32 read_pll(struct gt215_clk_priv *, int, u32); | |
7c856522 BS |
40 | |
41 | static u32 | |
7632b30e | 42 | read_vco(struct gt215_clk_priv *priv, int clk) |
7c856522 BS |
43 | { |
44 | u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); | |
3d896d34 RS |
45 | |
46 | switch (sctl & 0x00000030) { | |
47 | case 0x00000000: | |
48 | return nv_device(priv)->crystal; | |
49 | case 0x00000020: | |
7c856522 | 50 | return read_pll(priv, 0x41, 0x00e820); |
3d896d34 RS |
51 | case 0x00000030: |
52 | return read_pll(priv, 0x42, 0x00e8a0); | |
53 | default: | |
54 | return 0; | |
55 | } | |
7c856522 BS |
56 | } |
57 | ||
58 | static u32 | |
7632b30e | 59 | read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en) |
7c856522 BS |
60 | { |
61 | u32 sctl, sdiv, sclk; | |
62 | ||
63 | /* refclk for the 0xe8xx plls is a fixed frequency */ | |
64 | if (clk >= 0x40) { | |
65 | if (nv_device(priv)->chipset == 0xaf) { | |
66 | /* no joke.. seriously.. sigh.. */ | |
67 | return nv_rd32(priv, 0x00471c) * 1000; | |
68 | } | |
69 | ||
70 | return nv_device(priv)->crystal; | |
71 | } | |
72 | ||
73 | sctl = nv_rd32(priv, 0x4120 + (clk * 4)); | |
74 | if (!ignore_en && !(sctl & 0x00000100)) | |
75 | return 0; | |
76 | ||
3d896d34 RS |
77 | /* out_alt */ |
78 | if (sctl & 0x00000400) | |
79 | return 108000; | |
80 | ||
81 | /* vco_out */ | |
7c856522 BS |
82 | switch (sctl & 0x00003000) { |
83 | case 0x00000000: | |
3d896d34 RS |
84 | if (!(sctl & 0x00000200)) |
85 | return nv_device(priv)->crystal; | |
86 | return 0; | |
7c856522 BS |
87 | case 0x00002000: |
88 | if (sctl & 0x00000040) | |
89 | return 108000; | |
90 | return 100000; | |
91 | case 0x00003000: | |
3d896d34 RS |
92 | /* vco_enable */ |
93 | if (!(sctl & 0x00000001)) | |
94 | return 0; | |
95 | ||
7c856522 BS |
96 | sclk = read_vco(priv, clk); |
97 | sdiv = ((sctl & 0x003f0000) >> 16) + 2; | |
98 | return (sclk * 2) / sdiv; | |
99 | default: | |
100 | return 0; | |
101 | } | |
102 | } | |
103 | ||
104 | static u32 | |
7632b30e | 105 | read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) |
7c856522 BS |
106 | { |
107 | u32 ctrl = nv_rd32(priv, pll + 0); | |
108 | u32 sclk = 0, P = 1, N = 1, M = 1; | |
109 | ||
110 | if (!(ctrl & 0x00000008)) { | |
111 | if (ctrl & 0x00000001) { | |
112 | u32 coef = nv_rd32(priv, pll + 4); | |
113 | M = (coef & 0x000000ff) >> 0; | |
114 | N = (coef & 0x0000ff00) >> 8; | |
115 | P = (coef & 0x003f0000) >> 16; | |
116 | ||
3d896d34 RS |
117 | /* no post-divider on these.. |
118 | * XXX: it looks more like two post-"dividers" that | |
119 | * cross each other out in the default RPLL config */ | |
7c856522 BS |
120 | if ((pll & 0x00ff00) == 0x00e800) |
121 | P = 1; | |
122 | ||
123 | sclk = read_clk(priv, 0x00 + clk, false); | |
124 | } | |
125 | } else { | |
126 | sclk = read_clk(priv, 0x10 + clk, false); | |
127 | } | |
128 | ||
129 | if (M * P) | |
130 | return sclk * N / (M * P); | |
7632b30e | 131 | |
7c856522 BS |
132 | return 0; |
133 | } | |
134 | ||
135 | static int | |
7632b30e | 136 | gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) |
7c856522 | 137 | { |
7632b30e | 138 | struct gt215_clk_priv *priv = (void *)clk; |
70c7995d | 139 | u32 hsrc; |
7c856522 BS |
140 | |
141 | switch (src) { | |
142 | case nv_clk_src_crystal: | |
143 | return nv_device(priv)->crystal; | |
7c856522 | 144 | case nv_clk_src_core: |
3d40a717 | 145 | case nv_clk_src_core_intm: |
7c856522 BS |
146 | return read_pll(priv, 0x00, 0x4200); |
147 | case nv_clk_src_shader: | |
148 | return read_pll(priv, 0x01, 0x4220); | |
149 | case nv_clk_src_mem: | |
150 | return read_pll(priv, 0x02, 0x4000); | |
151 | case nv_clk_src_disp: | |
152 | return read_clk(priv, 0x20, false); | |
153 | case nv_clk_src_vdec: | |
154 | return read_clk(priv, 0x21, false); | |
155 | case nv_clk_src_daemon: | |
156 | return read_clk(priv, 0x25, false); | |
70c7995d RS |
157 | case nv_clk_src_host: |
158 | hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; | |
159 | switch (hsrc) { | |
160 | case 0: | |
161 | return read_clk(priv, 0x1d, false); | |
162 | case 2: | |
163 | case 3: | |
164 | return 277000; | |
165 | default: | |
166 | nv_error(clk, "unknown HOST clock source %d\n", hsrc); | |
167 | return -EINVAL; | |
168 | } | |
7c856522 BS |
169 | default: |
170 | nv_error(clk, "invalid clock source %d\n", src); | |
171 | return -EINVAL; | |
172 | } | |
3d896d34 RS |
173 | |
174 | return 0; | |
7c856522 BS |
175 | } |
176 | ||
d9c39056 | 177 | int |
7632b30e BS |
178 | gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz, |
179 | struct gt215_clk_info *info) | |
d9c39056 | 180 | { |
7632b30e | 181 | struct gt215_clk_priv *priv = (void *)clock; |
96945546 RS |
182 | u32 oclk, sclk, sdiv; |
183 | s32 diff; | |
7c856522 | 184 | |
7c856522 BS |
185 | info->clk = 0; |
186 | ||
187 | switch (khz) { | |
188 | case 27000: | |
189 | info->clk = 0x00000100; | |
190 | return khz; | |
191 | case 100000: | |
192 | info->clk = 0x00002100; | |
193 | return khz; | |
194 | case 108000: | |
195 | info->clk = 0x00002140; | |
196 | return khz; | |
197 | default: | |
198 | sclk = read_vco(priv, clk); | |
6a4a47cf RS |
199 | sdiv = min((sclk * 2) / khz, (u32)65); |
200 | oclk = (sclk * 2) / sdiv; | |
201 | diff = ((khz + 3000) - oclk); | |
202 | ||
203 | /* When imprecise, play it safe and aim for a clock lower than | |
204 | * desired rather than higher */ | |
205 | if (diff < 0) { | |
206 | sdiv++; | |
207 | oclk = (sclk * 2) / sdiv; | |
208 | } | |
209 | ||
210 | /* divider can go as low as 2, limited here because NVIDIA | |
7c856522 BS |
211 | * and the VBIOS on my NVA8 seem to prefer using the PLL |
212 | * for 810MHz - is there a good reason? | |
6a4a47cf | 213 | * XXX: PLLs with refclk 810MHz? */ |
7c856522 | 214 | if (sdiv > 4) { |
6a4a47cf RS |
215 | info->clk = (((sdiv - 2) << 16) | 0x00003100); |
216 | return oclk; | |
7c856522 BS |
217 | } |
218 | ||
7c856522 BS |
219 | break; |
220 | } | |
d9c39056 | 221 | |
6a4a47cf RS |
222 | return -ERANGE; |
223 | } | |
224 | ||
225 | int | |
7632b30e BS |
226 | gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz, |
227 | struct gt215_clk_info *info) | |
6a4a47cf | 228 | { |
7632b30e BS |
229 | struct nvkm_bios *bios = nvkm_bios(clock); |
230 | struct gt215_clk_priv *priv = (void *)clock; | |
6a4a47cf RS |
231 | struct nvbios_pll limits; |
232 | int P, N, M, diff; | |
233 | int ret; | |
234 | ||
235 | info->pll = 0; | |
236 | ||
237 | /* If we can get a within [-2, 3) MHz of a divider, we'll disable the | |
238 | * PLL and use the divider instead. */ | |
7632b30e | 239 | ret = gt215_clk_info(clock, clk, khz, info); |
3d40a717 | 240 | diff = khz - ret; |
6a4a47cf | 241 | if (!pll || (diff >= -2000 && diff < 3000)) { |
3d40a717 | 242 | goto out; |
6a4a47cf RS |
243 | } |
244 | ||
245 | /* Try with PLL */ | |
7c856522 BS |
246 | ret = nvbios_pll_parse(bios, pll, &limits); |
247 | if (ret) | |
248 | return ret; | |
249 | ||
7632b30e | 250 | ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info); |
3d40a717 | 251 | if (ret != limits.refclk) |
7c856522 | 252 | return -EINVAL; |
d9c39056 | 253 | |
7632b30e | 254 | ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); |
7c856522 | 255 | if (ret >= 0) { |
7c856522 | 256 | info->pll = (P << 16) | (N << 8) | M; |
d9c39056 | 257 | } |
7c856522 | 258 | |
3d40a717 RS |
259 | out: |
260 | info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); | |
7c856522 BS |
261 | return ret ? ret : -ERANGE; |
262 | } | |
263 | ||
264 | static int | |
7632b30e | 265 | calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate, |
7c856522 BS |
266 | int clk, u32 pll, int idx) |
267 | { | |
7632b30e BS |
268 | int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx], |
269 | &priv->eng[idx]); | |
7c856522 BS |
270 | if (ret >= 0) |
271 | return 0; | |
d9c39056 ML |
272 | return ret; |
273 | } | |
274 | ||
70c7995d | 275 | static int |
7632b30e | 276 | calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate) |
70c7995d RS |
277 | { |
278 | int ret = 0; | |
279 | u32 kHz = cstate->domain[nv_clk_src_host]; | |
7632b30e | 280 | struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; |
70c7995d RS |
281 | |
282 | if (kHz == 277000) { | |
283 | info->clk = 0; | |
284 | info->host_out = NVA3_HOST_277; | |
285 | return 0; | |
286 | } | |
287 | ||
288 | info->host_out = NVA3_HOST_CLK; | |
289 | ||
7632b30e | 290 | ret = gt215_clk_info(&priv->base, 0x1d, kHz, info); |
70c7995d RS |
291 | if (ret >= 0) |
292 | return 0; | |
7632b30e | 293 | |
70c7995d RS |
294 | return ret; |
295 | } | |
296 | ||
2fe7eaa0 | 297 | int |
7632b30e | 298 | gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) |
2fe7eaa0 | 299 | { |
7632b30e | 300 | struct nvkm_fifo *pfifo = nvkm_fifo(clk); |
2fe7eaa0 RS |
301 | |
302 | /* halt and idle execution engines */ | |
303 | nv_mask(clk, 0x020060, 0x00070000, 0x00000000); | |
304 | nv_mask(clk, 0x002504, 0x00000001, 0x00000001); | |
305 | /* Wait until the interrupt handler is finished */ | |
306 | if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) | |
307 | return -EBUSY; | |
308 | ||
309 | if (pfifo) | |
310 | pfifo->pause(pfifo, flags); | |
311 | ||
312 | if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) | |
313 | return -EIO; | |
314 | if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) | |
315 | return -EIO; | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | void | |
7632b30e | 321 | gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) |
2fe7eaa0 | 322 | { |
7632b30e | 323 | struct nvkm_fifo *pfifo = nvkm_fifo(clk); |
2fe7eaa0 RS |
324 | |
325 | if (pfifo && flags) | |
326 | pfifo->start(pfifo, flags); | |
327 | ||
328 | nv_mask(clk, 0x002504, 0x00000001, 0x00000000); | |
329 | nv_mask(clk, 0x020060, 0x00070000, 0x00040000); | |
330 | } | |
331 | ||
70c7995d | 332 | static void |
7632b30e | 333 | disable_clk_src(struct gt215_clk_priv *priv, u32 src) |
70c7995d RS |
334 | { |
335 | nv_mask(priv, src, 0x00000100, 0x00000000); | |
336 | nv_mask(priv, src, 0x00000001, 0x00000000); | |
337 | } | |
338 | ||
7c856522 | 339 | static void |
7632b30e | 340 | prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx) |
7c856522 | 341 | { |
7632b30e | 342 | struct gt215_clk_info *info = &priv->eng[idx]; |
7c856522 BS |
343 | const u32 src0 = 0x004120 + (clk * 4); |
344 | const u32 src1 = 0x004160 + (clk * 4); | |
345 | const u32 ctrl = pll + 0; | |
346 | const u32 coef = pll + 4; | |
a749a1fb | 347 | u32 bypass; |
7c856522 BS |
348 | |
349 | if (info->pll) { | |
a749a1fb RS |
350 | /* Always start from a non-PLL clock */ |
351 | bypass = nv_rd32(priv, ctrl) & 0x00000008; | |
352 | if (!bypass) { | |
353 | nv_mask(priv, src1, 0x00000101, 0x00000101); | |
354 | nv_mask(priv, ctrl, 0x00000008, 0x00000008); | |
355 | udelay(20); | |
356 | } | |
357 | ||
6a4a47cf | 358 | nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); |
7c856522 BS |
359 | nv_wr32(priv, coef, info->pll); |
360 | nv_mask(priv, ctrl, 0x00000015, 0x00000015); | |
361 | nv_mask(priv, ctrl, 0x00000010, 0x00000000); | |
275dd6f4 RS |
362 | if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { |
363 | nv_mask(priv, ctrl, 0x00000010, 0x00000010); | |
364 | nv_mask(priv, src0, 0x00000101, 0x00000000); | |
365 | return; | |
366 | } | |
7c856522 BS |
367 | nv_mask(priv, ctrl, 0x00000010, 0x00000010); |
368 | nv_mask(priv, ctrl, 0x00000008, 0x00000000); | |
70c7995d | 369 | disable_clk_src(priv, src1); |
7c856522 BS |
370 | } else { |
371 | nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); | |
372 | nv_mask(priv, ctrl, 0x00000018, 0x00000018); | |
373 | udelay(20); | |
374 | nv_mask(priv, ctrl, 0x00000001, 0x00000000); | |
70c7995d | 375 | disable_clk_src(priv, src0); |
7c856522 BS |
376 | } |
377 | } | |
378 | ||
379 | static void | |
7632b30e | 380 | prog_clk(struct gt215_clk_priv *priv, int clk, int idx) |
7c856522 | 381 | { |
7632b30e | 382 | struct gt215_clk_info *info = &priv->eng[idx]; |
7c856522 BS |
383 | nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); |
384 | } | |
385 | ||
70c7995d | 386 | static void |
7632b30e | 387 | prog_host(struct gt215_clk_priv *priv) |
70c7995d | 388 | { |
7632b30e | 389 | struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; |
70c7995d RS |
390 | u32 hsrc = (nv_rd32(priv, 0xc040)); |
391 | ||
392 | switch (info->host_out) { | |
393 | case NVA3_HOST_277: | |
394 | if ((hsrc & 0x30000000) == 0) { | |
395 | nv_wr32(priv, 0xc040, hsrc | 0x20000000); | |
396 | disable_clk_src(priv, 0x4194); | |
397 | } | |
398 | break; | |
399 | case NVA3_HOST_CLK: | |
400 | prog_clk(priv, 0x1d, nv_clk_src_host); | |
401 | if ((hsrc & 0x30000000) >= 0x20000000) { | |
402 | nv_wr32(priv, 0xc040, hsrc & ~0x30000000); | |
403 | } | |
404 | break; | |
405 | default: | |
406 | break; | |
407 | } | |
408 | ||
409 | /* This seems to be a clock gating factor on idle, always set to 64 */ | |
410 | nv_wr32(priv, 0xc044, 0x3e); | |
411 | } | |
412 | ||
3d40a717 | 413 | static void |
7632b30e | 414 | prog_core(struct gt215_clk_priv *priv, int idx) |
3d40a717 | 415 | { |
7632b30e | 416 | struct gt215_clk_info *info = &priv->eng[idx]; |
3d40a717 RS |
417 | u32 fb_delay = nv_rd32(priv, 0x10002c); |
418 | ||
419 | if (fb_delay < info->fb_delay) | |
420 | nv_wr32(priv, 0x10002c, info->fb_delay); | |
421 | ||
422 | prog_pll(priv, 0x00, 0x004200, idx); | |
423 | ||
424 | if (fb_delay > info->fb_delay) | |
425 | nv_wr32(priv, 0x10002c, info->fb_delay); | |
426 | } | |
427 | ||
7c856522 | 428 | static int |
7632b30e | 429 | gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) |
7c856522 | 430 | { |
7632b30e BS |
431 | struct gt215_clk_priv *priv = (void *)clk; |
432 | struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; | |
7c856522 BS |
433 | int ret; |
434 | ||
435 | if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || | |
436 | (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || | |
437 | (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || | |
70c7995d RS |
438 | (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || |
439 | (ret = calc_host(priv, cstate))) | |
7c856522 BS |
440 | return ret; |
441 | ||
3d40a717 RS |
442 | /* XXX: Should be reading the highest bit in the VBIOS clock to decide |
443 | * whether to use a PLL or not... but using a PLL defeats the purpose */ | |
444 | if (core->pll) { | |
7632b30e BS |
445 | ret = gt215_clk_info(clk, 0x10, |
446 | cstate->domain[nv_clk_src_core_intm], | |
447 | &priv->eng[nv_clk_src_core_intm]); | |
3d40a717 RS |
448 | if (ret < 0) |
449 | return ret; | |
450 | } | |
451 | ||
7c856522 BS |
452 | return 0; |
453 | } | |
454 | ||
455 | static int | |
7632b30e | 456 | gt215_clk_prog(struct nvkm_clk *clk) |
7c856522 | 457 | { |
7632b30e BS |
458 | struct gt215_clk_priv *priv = (void *)clk; |
459 | struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; | |
2fe7eaa0 RS |
460 | int ret = 0; |
461 | unsigned long flags; | |
462 | unsigned long *f = &flags; | |
463 | ||
7632b30e | 464 | ret = gt215_clk_pre(clk, f); |
2fe7eaa0 RS |
465 | if (ret) |
466 | goto out; | |
3d40a717 RS |
467 | |
468 | if (core->pll) | |
469 | prog_core(priv, nv_clk_src_core_intm); | |
470 | ||
471 | prog_core(priv, nv_clk_src_core); | |
7c856522 BS |
472 | prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); |
473 | prog_clk(priv, 0x20, nv_clk_src_disp); | |
474 | prog_clk(priv, 0x21, nv_clk_src_vdec); | |
70c7995d | 475 | prog_host(priv); |
2fe7eaa0 RS |
476 | |
477 | out: | |
478 | if (ret == -EBUSY) | |
479 | f = NULL; | |
480 | ||
7632b30e | 481 | gt215_clk_post(clk, f); |
2fe7eaa0 | 482 | return ret; |
7c856522 BS |
483 | } |
484 | ||
485 | static void | |
7632b30e | 486 | gt215_clk_tidy(struct nvkm_clk *clk) |
7c856522 BS |
487 | { |
488 | } | |
489 | ||
7632b30e BS |
490 | static struct nvkm_domain |
491 | gt215_domain[] = { | |
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492 | { nv_clk_src_crystal , 0xff }, |
493 | { nv_clk_src_core , 0x00, 0, "core", 1000 }, | |
494 | { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, | |
495 | { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, | |
496 | { nv_clk_src_vdec , 0x03 }, | |
497 | { nv_clk_src_disp , 0x04 }, | |
498 | { nv_clk_src_host , 0x05 }, | |
499 | { nv_clk_src_core_intm, 0x06 }, | |
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500 | { nv_clk_src_max } |
501 | }; | |
d9c39056 | 502 | |
8aceb7de | 503 | static int |
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504 | gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
505 | struct nvkm_oclass *oclass, void *data, u32 size, | |
506 | struct nvkm_object **pobject) | |
8aceb7de | 507 | { |
7632b30e | 508 | struct gt215_clk_priv *priv; |
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509 | int ret; |
510 | ||
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511 | ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, |
512 | NULL, 0, true, &priv); | |
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513 | *pobject = nv_object(priv); |
514 | if (ret) | |
515 | return ret; | |
516 | ||
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517 | priv->base.read = gt215_clk_read; |
518 | priv->base.calc = gt215_clk_calc; | |
519 | priv->base.prog = gt215_clk_prog; | |
520 | priv->base.tidy = gt215_clk_tidy; | |
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521 | return 0; |
522 | } | |
523 | ||
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524 | struct nvkm_oclass |
525 | gt215_clk_oclass = { | |
f3867f43 | 526 | .handle = NV_SUBDEV(CLK, 0xa3), |
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527 | .ofuncs = &(struct nvkm_ofuncs) { |
528 | .ctor = gt215_clk_ctor, | |
529 | .dtor = _nvkm_clk_dtor, | |
530 | .init = _nvkm_clk_init, | |
531 | .fini = _nvkm_clk_fini, | |
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532 | }, |
533 | }; |