[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gt215.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 *          Roy Spliet
 */
#include "gt215.h"
#include "pll.h"

#include <core/device.h>
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

struct gt215_clk_priv {
	struct nvkm_clk base;
	struct gt215_clk_info eng[nv_clk_src_max];
};

static u32 read_clk(struct gt215_clk_priv *, int, bool);
static u32 read_pll(struct gt215_clk_priv *, int, u32);

static u32
read_vco(struct gt215_clk_priv *priv, int clk)
{
	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));

	switch (sctl & 0x00000030) {
	case 0x00000000:
		return nv_device(priv)->crystal;
	case 0x00000020:
		return read_pll(priv, 0x41, 0x00e820);
	case 0x00000030:
		return read_pll(priv, 0x42, 0x00e8a0);
	default:
		return 0;
	}
}

static u32
read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en)
{
	u32 sctl, sdiv, sclk;

	/* refclk for the 0xe8xx plls is a fixed frequency */
	if (clk >= 0x40) {
		if (nv_device(priv)->chipset == 0xaf) {
			/* no joke.. seriously.. sigh.. */
			return nv_rd32(priv, 0x00471c) * 1000;
		}

		return nv_device(priv)->crystal;
	}

	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	/* out_alt */
	if (sctl & 0x00000400)
		return 108000;

	/* vco_out */
	switch (sctl & 0x00003000) {
	case 0x00000000:
		if (!(sctl & 0x00000200))
			return nv_device(priv)->crystal;
		return 0;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		/* vco_enable */
		if (!(sctl & 0x00000001))
			return 0;

		sclk = read_vco(priv, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct gt215_clk_priv *priv, int clk, u32 pll)
{
	u32 ctrl = nv_rd32(priv, pll + 0);
	u32 sclk = 0, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		if (ctrl & 0x00000001) {
			u32 coef = nv_rd32(priv, pll + 4);
			M = (coef & 0x000000ff) >> 0;
			N = (coef & 0x0000ff00) >> 8;
			P = (coef & 0x003f0000) >> 16;

			/* no post-divider on these..
			 * XXX: it looks more like two post-"dividers" that
			 * cross each other out in the default RPLL config */
			if ((pll & 0x00ff00) == 0x00e800)
				P = 1;

			sclk = read_clk(priv, 0x00 + clk, false);
		}
	} else {
		sclk = read_clk(priv, 0x10 + clk, false);
	}

	if (M * P)
		return sclk * N / (M * P);

	return 0;
}

static int
gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
	struct gt215_clk_priv *priv = (void *)clk;
	u32 hsrc;

	switch (src) {
	case nv_clk_src_crystal:
		return nv_device(priv)->crystal;
	case nv_clk_src_core:
	case nv_clk_src_core_intm:
		return read_pll(priv, 0x00, 0x4200);
	case nv_clk_src_shader:
		return read_pll(priv, 0x01, 0x4220);
	case nv_clk_src_mem:
		return read_pll(priv, 0x02, 0x4000);
	case nv_clk_src_disp:
		return read_clk(priv, 0x20, false);
	case nv_clk_src_vdec:
		return read_clk(priv, 0x21, false);
	case nv_clk_src_daemon:
		return read_clk(priv, 0x25, false);
	case nv_clk_src_host:
		hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
		switch (hsrc) {
		case 0:
			return read_clk(priv, 0x1d, false);
		case 2:
		case 3:
			return 277000;
		default:
			nv_error(clk, "unknown HOST clock source %d\n", hsrc);
			return -EINVAL;
		}
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}

	return 0;
}

int
gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz,
	       struct gt215_clk_info *info)
{
	struct gt215_clk_priv *priv = (void *)clock;
	u32 oclk, sclk, sdiv, diff;

	info->clk = 0;

	switch (khz) {
	case 27000:
		info->clk = 0x00000100;
		return khz;
	case 100000:
		info->clk = 0x00002100;
		return khz;
	case 108000:
		info->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(priv, clk);
		sdiv = min((sclk * 2) / khz, (u32)65);
		oclk = (sclk * 2) / sdiv;
		diff = ((khz + 3000) - oclk);

		/* When imprecise, play it safe and aim for a clock lower than
		 * desired rather than higher */
		if (diff < 0) {
			sdiv++;
			oclk = (sclk * 2) / sdiv;
		}

		/* divider can go as low as 2, limited here because NVIDIA
		 * and the VBIOS on my NVA8 seem to prefer using the PLL
		 * for 810MHz - is there a good reason?
		 * XXX: PLLs with refclk 810MHz?  */
		if (sdiv > 4) {
			info->clk = (((sdiv - 2) << 16) | 0x00003100);
			return oclk;
		}

		break;
	}

	return -ERANGE;
}

int
gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz,
	       struct gt215_clk_info *info)
{
	struct nvkm_bios *bios = nvkm_bios(clock);
	struct gt215_clk_priv *priv = (void *)clock;
	struct nvbios_pll limits;
	int P, N, M, diff;
	int ret;

	info->pll = 0;

	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	 * PLL and use the divider instead. */
	ret = gt215_clk_info(clock, clk, khz, info);
	diff = khz - ret;
	if (!pll || (diff >= -2000 && diff < 3000)) {
		goto out;
	}

	/* Try with PLL */
	ret = nvbios_pll_parse(bios, pll, &limits);
	if (ret)
		return ret;

	ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info);
	if (ret != limits.refclk)
		return -EINVAL;

	ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		info->pll = (P << 16) | (N << 8) | M;
	}

out:
	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
	return ret ? ret : -ERANGE;
}

static int
calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate,
	 int clk, u32 pll, int idx)
{
	int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx],
				 &priv->eng[idx]);
	if (ret >= 0)
		return 0;
	return ret;
}

static int
calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate)
{
	int ret = 0;
	u32 kHz = cstate->domain[nv_clk_src_host];
	struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];

	if (kHz == 277000) {
		info->clk = 0;
		info->host_out = NVA3_HOST_277;
		return 0;
	}

	info->host_out = NVA3_HOST_CLK;

	ret = gt215_clk_info(&priv->base, 0x1d, kHz, info);
	if (ret >= 0)
		return 0;

	return ret;
}

int
gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags)
{
	struct nvkm_fifo *pfifo = nvkm_fifo(clk);

	/* halt and idle execution engines */
	nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
	nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
	/* Wait until the interrupt handler is finished */
	if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
		return -EBUSY;

	if (pfifo)
		pfifo->pause(pfifo, flags);

	if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
		return -EIO;
	if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
		return -EIO;

	return 0;
}

void
gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags)
{
	struct nvkm_fifo *pfifo = nvkm_fifo(clk);

	if (pfifo && flags)
		pfifo->start(pfifo, flags);

	nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
	nv_mask(clk, 0x020060, 0x00070000, 0x00040000);
}

static void
disable_clk_src(struct gt215_clk_priv *priv, u32 src)
{
	nv_mask(priv, src, 0x00000100, 0x00000000);
	nv_mask(priv, src, 0x00000001, 0x00000000);
}

static void
prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx)
{
	struct gt215_clk_info *info = &priv->eng[idx];
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;
	u32 bypass;

	if (info->pll) {
		/* Always start from a non-PLL clock */
		bypass = nv_rd32(priv, ctrl)  & 0x00000008;
		if (!bypass) {
			nv_mask(priv, src1, 0x00000101, 0x00000101);
			nv_mask(priv, ctrl, 0x00000008, 0x00000008);
			udelay(20);
		}

		nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
		nv_wr32(priv, coef, info->pll);
		nv_mask(priv, ctrl, 0x00000015, 0x00000015);
		nv_mask(priv, ctrl, 0x00000010, 0x00000000);
		if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
			nv_mask(priv, ctrl, 0x00000010, 0x00000010);
			nv_mask(priv, src0, 0x00000101, 0x00000000);
			return;
		}
		nv_mask(priv, ctrl, 0x00000010, 0x00000010);
		nv_mask(priv, ctrl, 0x00000008, 0x00000000);
		disable_clk_src(priv, src1);
	} else {
		nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
		nv_mask(priv, ctrl, 0x00000018, 0x00000018);
		udelay(20);
		nv_mask(priv, ctrl, 0x00000001, 0x00000000);
		disable_clk_src(priv, src0);
	}
}

static void
prog_clk(struct gt215_clk_priv *priv, int clk, int idx)
{
	struct gt215_clk_info *info = &priv->eng[idx];
	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}

static void
prog_host(struct gt215_clk_priv *priv)
{
	struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];
	u32 hsrc = (nv_rd32(priv, 0xc040));

	switch (info->host_out) {
	case NVA3_HOST_277:
		if ((hsrc & 0x30000000) == 0) {
			nv_wr32(priv, 0xc040, hsrc | 0x20000000);
			disable_clk_src(priv, 0x4194);
		}
		break;
	case NVA3_HOST_CLK:
		prog_clk(priv, 0x1d, nv_clk_src_host);
		if ((hsrc & 0x30000000) >= 0x20000000) {
			nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
		}
		break;
	default:
		break;
	}

	/* This seems to be a clock gating factor on idle, always set to 64 */
	nv_wr32(priv, 0xc044, 0x3e);
}

static void
prog_core(struct gt215_clk_priv *priv, int idx)
{
	struct gt215_clk_info *info = &priv->eng[idx];
	u32 fb_delay = nv_rd32(priv, 0x10002c);

	if (fb_delay < info->fb_delay)
		nv_wr32(priv, 0x10002c, info->fb_delay);

	prog_pll(priv, 0x00, 0x004200, idx);

	if (fb_delay > info->fb_delay)
		nv_wr32(priv, 0x10002c, info->fb_delay);
}

static int
gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
	struct gt215_clk_priv *priv = (void *)clk;
	struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
	int ret;

	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
	    (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
	    (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
	    (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
	    (ret = calc_host(priv, cstate)))
		return ret;

	/* XXX: Should be reading the highest bit in the VBIOS clock to decide
	 * whether to use a PLL or not... but using a PLL defeats the purpose */
	if (core->pll) {
		ret = gt215_clk_info(clk, 0x10,
				     cstate->domain[nv_clk_src_core_intm],
				     &priv->eng[nv_clk_src_core_intm]);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int
gt215_clk_prog(struct nvkm_clk *clk)
{
	struct gt215_clk_priv *priv = (void *)clk;
	struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
	int ret = 0;
	unsigned long flags;
	unsigned long *f = &flags;

	ret = gt215_clk_pre(clk, f);
	if (ret)
		goto out;

	if (core->pll)
		prog_core(priv, nv_clk_src_core_intm);

	prog_core(priv,  nv_clk_src_core);
	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	prog_clk(priv, 0x20, nv_clk_src_disp);
	prog_clk(priv, 0x21, nv_clk_src_vdec);
	prog_host(priv);

out:
	if (ret == -EBUSY)
		f = NULL;

	gt215_clk_post(clk, f);
	return ret;
}

static void
gt215_clk_tidy(struct nvkm_clk *clk)
{
}

static struct nvkm_domain
gt215_domain[] = {
	{ nv_clk_src_crystal  , 0xff },
	{ nv_clk_src_core     , 0x00, 0, "core", 1000 },
	{ nv_clk_src_shader   , 0x01, 0, "shader", 1000 },
	{ nv_clk_src_mem      , 0x02, 0, "memory", 1000 },
	{ nv_clk_src_vdec     , 0x03 },
	{ nv_clk_src_disp     , 0x04 },
	{ nv_clk_src_host     , 0x05 },
	{ nv_clk_src_core_intm, 0x06 },
	{ nv_clk_src_max }
};

static int
gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	       struct nvkm_oclass *oclass, void *data, u32 size,
	       struct nvkm_object **pobject)
{
	struct gt215_clk_priv *priv;
	int ret;

	ret = nvkm_clk_create(parent, engine, oclass, gt215_domain,
			      NULL, 0, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.read = gt215_clk_read;
	priv->base.calc = gt215_clk_calc;
	priv->base.prog = gt215_clk_prog;
	priv->base.tidy = gt215_clk_tidy;
	return 0;
}

struct nvkm_oclass
gt215_clk_oclass = {
	.handle = NV_SUBDEV(CLK, 0xa3),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = gt215_clk_ctor,
		.dtor = _nvkm_clk_dtor,
		.init = _nvkm_clk_init,
		.fini = _nvkm_clk_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
3d896d34	23	* Roy Spliet
8aceb7de	24	*/
7632b30e BS	25	#include "gt215.h"
7632b30e BS	26	#include "pll.h"
8aceb7de	27
9e79a853	28	#include <core/device.h>
2fe7eaa0	29	#include <engine/fifo.h>
70790f4f BS	30	#include <subdev/bios.h>
70790f4f BS	31	#include <subdev/bios/pll.h>
7c856522	32	#include <subdev/timer.h>
70790f4f	33
7632b30e BS	34	struct gt215_clk_priv {
	35	struct nvkm_clk base;
	36	struct gt215_clk_info eng[nv_clk_src_max];
8aceb7de BS	37	};
8aceb7de BS	38
7632b30e BS	39	static u32 read_clk(struct gt215_clk_priv *, int, bool);
7632b30e BS	40	static u32 read_pll(struct gt215_clk_priv *, int, u32);
7c856522 BS	41
7c856522 BS	42	static u32
7632b30e	43	read_vco(struct gt215_clk_priv *priv, int clk)
7c856522 BS	44	{
7c856522 BS	45	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
3d896d34 RS	46
	47	switch (sctl & 0x00000030) {
	48	case 0x00000000:
	49	return nv_device(priv)->crystal;
	50	case 0x00000020:
7c856522	51	return read_pll(priv, 0x41, 0x00e820);
3d896d34 RS	52	case 0x00000030:
	53	return read_pll(priv, 0x42, 0x00e8a0);
	54	default:
	55	return 0;
	56	}
7c856522 BS	57	}
	58
	59	static u32
7632b30e	60	read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en)
7c856522 BS	61	{
	62	u32 sctl, sdiv, sclk;
	63
	64	/* refclk for the 0xe8xx plls is a fixed frequency */
	65	if (clk >= 0x40) {
	66	if (nv_device(priv)->chipset == 0xaf) {
	67	/* no joke.. seriously.. sigh.. */
	68	return nv_rd32(priv, 0x00471c) * 1000;
	69	}
	70
	71	return nv_device(priv)->crystal;
	72	}
	73
	74	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	75	if (!ignore_en && !(sctl & 0x00000100))
	76	return 0;
	77
3d896d34 RS	78	/* out_alt */
	79	if (sctl & 0x00000400)
	80	return 108000;
	81
	82	/* vco_out */
7c856522 BS	83	switch (sctl & 0x00003000) {
7c856522 BS	84	case 0x00000000:
3d896d34 RS	85	if (!(sctl & 0x00000200))
	86	return nv_device(priv)->crystal;
	87	return 0;
7c856522 BS	88	case 0x00002000:
	89	if (sctl & 0x00000040)
	90	return 108000;
	91	return 100000;
	92	case 0x00003000:
3d896d34 RS	93	/* vco_enable */
	94	if (!(sctl & 0x00000001))
	95	return 0;
	96
7c856522 BS	97	sclk = read_vco(priv, clk);
	98	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
	99	return (sclk * 2) / sdiv;
	100	default:
	101	return 0;
	102	}
	103	}
	104
	105	static u32
7632b30e	106	read_pll(struct gt215_clk_priv *priv, int clk, u32 pll)
7c856522 BS	107	{
	108	u32 ctrl = nv_rd32(priv, pll + 0);
	109	u32 sclk = 0, P = 1, N = 1, M = 1;
	110
	111	if (!(ctrl & 0x00000008)) {
	112	if (ctrl & 0x00000001) {
	113	u32 coef = nv_rd32(priv, pll + 4);
	114	M = (coef & 0x000000ff) >> 0;
	115	N = (coef & 0x0000ff00) >> 8;
	116	P = (coef & 0x003f0000) >> 16;
	117
3d896d34 RS	118	/* no post-divider on these..
	119	* XXX: it looks more like two post-"dividers" that
	120	* cross each other out in the default RPLL config */
7c856522 BS	121	if ((pll & 0x00ff00) == 0x00e800)
	122	P = 1;
	123
	124	sclk = read_clk(priv, 0x00 + clk, false);
	125	}
	126	} else {
	127	sclk = read_clk(priv, 0x10 + clk, false);
	128	}
	129
	130	if (M * P)
	131	return sclk * N / (M * P);
7632b30e	132
7c856522 BS	133	return 0;
	134	}
	135
	136	static int
7632b30e	137	gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
7c856522	138	{
7632b30e	139	struct gt215_clk_priv priv = (void )clk;
70c7995d	140	u32 hsrc;
7c856522 BS	141
	142	switch (src) {
	143	case nv_clk_src_crystal:
	144	return nv_device(priv)->crystal;
7c856522	145	case nv_clk_src_core:
3d40a717	146	case nv_clk_src_core_intm:
7c856522 BS	147	return read_pll(priv, 0x00, 0x4200);
	148	case nv_clk_src_shader:
	149	return read_pll(priv, 0x01, 0x4220);
	150	case nv_clk_src_mem:
	151	return read_pll(priv, 0x02, 0x4000);
	152	case nv_clk_src_disp:
	153	return read_clk(priv, 0x20, false);
	154	case nv_clk_src_vdec:
	155	return read_clk(priv, 0x21, false);
	156	case nv_clk_src_daemon:
	157	return read_clk(priv, 0x25, false);
70c7995d RS	158	case nv_clk_src_host:
	159	hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
	160	switch (hsrc) {
	161	case 0:
	162	return read_clk(priv, 0x1d, false);
	163	case 2:
	164	case 3:
	165	return 277000;
	166	default:
	167	nv_error(clk, "unknown HOST clock source %d\n", hsrc);
	168	return -EINVAL;
	169	}
7c856522 BS	170	default:
	171	nv_error(clk, "invalid clock source %d\n", src);
	172	return -EINVAL;
	173	}
3d896d34 RS	174
3d896d34 RS	175	return 0;
7c856522 BS	176	}
7c856522 BS	177
d9c39056	178	int
7632b30e BS	179	gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz,
7632b30e BS	180	struct gt215_clk_info *info)
d9c39056	181	{
7632b30e	182	struct gt215_clk_priv priv = (void )clock;
6a4a47cf	183	u32 oclk, sclk, sdiv, diff;
7c856522	184
7c856522 BS	185	info->clk = 0;
	186
	187	switch (khz) {
	188	case 27000:
	189	info->clk = 0x00000100;
	190	return khz;
	191	case 100000:
	192	info->clk = 0x00002100;
	193	return khz;
	194	case 108000:
	195	info->clk = 0x00002140;
	196	return khz;
	197	default:
	198	sclk = read_vco(priv, clk);
6a4a47cf RS	199	sdiv = min((sclk * 2) / khz, (u32)65);
	200	oclk = (sclk * 2) / sdiv;
	201	diff = ((khz + 3000) - oclk);
	202
	203	/* When imprecise, play it safe and aim for a clock lower than
	204	* desired rather than higher */
	205	if (diff < 0) {
	206	sdiv++;
	207	oclk = (sclk * 2) / sdiv;
	208	}
	209
	210	/* divider can go as low as 2, limited here because NVIDIA
7c856522 BS	211	* and the VBIOS on my NVA8 seem to prefer using the PLL
7c856522 BS	212	* for 810MHz - is there a good reason?
6a4a47cf	213	* XXX: PLLs with refclk 810MHz? */
7c856522	214	if (sdiv > 4) {
6a4a47cf RS	215	info->clk = (((sdiv - 2) << 16) \| 0x00003100);
6a4a47cf RS	216	return oclk;
7c856522 BS	217	}
7c856522 BS	218
7c856522 BS	219	break;
7c856522 BS	220	}
d9c39056	221
6a4a47cf RS	222	return -ERANGE;
	223	}
	224
	225	int
7632b30e BS	226	gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz,
7632b30e BS	227	struct gt215_clk_info *info)
6a4a47cf	228	{
7632b30e BS	229	struct nvkm_bios *bios = nvkm_bios(clock);
7632b30e BS	230	struct gt215_clk_priv priv = (void )clock;
6a4a47cf RS	231	struct nvbios_pll limits;
	232	int P, N, M, diff;
	233	int ret;
	234
	235	info->pll = 0;
	236
	237	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	238	* PLL and use the divider instead. */
7632b30e	239	ret = gt215_clk_info(clock, clk, khz, info);
3d40a717	240	diff = khz - ret;
6a4a47cf	241	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
3d40a717	242	goto out;
6a4a47cf RS	243	}
	244
	245	/* Try with PLL */
7c856522 BS	246	ret = nvbios_pll_parse(bios, pll, &limits);
	247	if (ret)
	248	return ret;
	249
7632b30e	250	ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info);
3d40a717	251	if (ret != limits.refclk)
7c856522	252	return -EINVAL;
d9c39056	253
7632b30e	254	ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
7c856522	255	if (ret >= 0) {
7c856522	256	info->pll = (P << 16) \| (N << 8) \| M;
d9c39056	257	}
7c856522	258
3d40a717 RS	259	out:
3d40a717 RS	260	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
7c856522 BS	261	return ret ? ret : -ERANGE;
	262	}
	263
	264	static int
7632b30e	265	calc_clk(struct gt215_clk_priv priv, struct nvkm_cstate cstate,
7c856522 BS	266	int clk, u32 pll, int idx)
7c856522 BS	267	{
7632b30e BS	268	int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx],
7632b30e BS	269	&priv->eng[idx]);
7c856522 BS	270	if (ret >= 0)
7c856522 BS	271	return 0;
d9c39056 ML	272	return ret;
	273	}
	274
70c7995d	275	static int
7632b30e	276	calc_host(struct gt215_clk_priv priv, struct nvkm_cstate cstate)
70c7995d RS	277	{
	278	int ret = 0;
	279	u32 kHz = cstate->domain[nv_clk_src_host];
7632b30e	280	struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];
70c7995d RS	281
	282	if (kHz == 277000) {
	283	info->clk = 0;
	284	info->host_out = NVA3_HOST_277;
	285	return 0;
	286	}
	287
	288	info->host_out = NVA3_HOST_CLK;
	289
7632b30e	290	ret = gt215_clk_info(&priv->base, 0x1d, kHz, info);
70c7995d RS	291	if (ret >= 0)
70c7995d RS	292	return 0;
7632b30e	293
70c7995d RS	294	return ret;
	295	}
	296
2fe7eaa0	297	int
7632b30e	298	gt215_clk_pre(struct nvkm_clk clk, unsigned long flags)
2fe7eaa0	299	{
7632b30e	300	struct nvkm_fifo *pfifo = nvkm_fifo(clk);
2fe7eaa0 RS	301
	302	/* halt and idle execution engines */
	303	nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
	304	nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
	305	/* Wait until the interrupt handler is finished */
	306	if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
	307	return -EBUSY;
	308
	309	if (pfifo)
	310	pfifo->pause(pfifo, flags);
	311
	312	if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
	313	return -EIO;
	314	if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
	315	return -EIO;
	316
	317	return 0;
	318	}
	319
	320	void
7632b30e	321	gt215_clk_post(struct nvkm_clk clk, unsigned long flags)
2fe7eaa0	322	{
7632b30e	323	struct nvkm_fifo *pfifo = nvkm_fifo(clk);
2fe7eaa0 RS	324
	325	if (pfifo && flags)
	326	pfifo->start(pfifo, flags);
	327
	328	nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
	329	nv_mask(clk, 0x020060, 0x00070000, 0x00040000);
	330	}
	331
70c7995d	332	static void
7632b30e	333	disable_clk_src(struct gt215_clk_priv *priv, u32 src)
70c7995d RS	334	{
	335	nv_mask(priv, src, 0x00000100, 0x00000000);
	336	nv_mask(priv, src, 0x00000001, 0x00000000);
	337	}
	338
7c856522	339	static void
7632b30e	340	prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx)
7c856522	341	{
7632b30e	342	struct gt215_clk_info *info = &priv->eng[idx];
7c856522 BS	343	const u32 src0 = 0x004120 + (clk * 4);
	344	const u32 src1 = 0x004160 + (clk * 4);
	345	const u32 ctrl = pll + 0;
	346	const u32 coef = pll + 4;
a749a1fb	347	u32 bypass;
7c856522 BS	348
7c856522 BS	349	if (info->pll) {
a749a1fb RS	350	/* Always start from a non-PLL clock */
	351	bypass = nv_rd32(priv, ctrl) & 0x00000008;
	352	if (!bypass) {
	353	nv_mask(priv, src1, 0x00000101, 0x00000101);
	354	nv_mask(priv, ctrl, 0x00000008, 0x00000008);
	355	udelay(20);
	356	}
	357
6a4a47cf	358	nv_mask(priv, src0, 0x003f3141, 0x00000101 \| info->clk);
7c856522 BS	359	nv_wr32(priv, coef, info->pll);
	360	nv_mask(priv, ctrl, 0x00000015, 0x00000015);
	361	nv_mask(priv, ctrl, 0x00000010, 0x00000000);
275dd6f4 RS	362	if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
	363	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
	364	nv_mask(priv, src0, 0x00000101, 0x00000000);
	365	return;
	366	}
7c856522 BS	367	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
7c856522 BS	368	nv_mask(priv, ctrl, 0x00000008, 0x00000000);
70c7995d	369	disable_clk_src(priv, src1);
7c856522 BS	370	} else {
	371	nv_mask(priv, src1, 0x003f3141, 0x00000101 \| info->clk);
	372	nv_mask(priv, ctrl, 0x00000018, 0x00000018);
	373	udelay(20);
	374	nv_mask(priv, ctrl, 0x00000001, 0x00000000);
70c7995d	375	disable_clk_src(priv, src0);
7c856522 BS	376	}
	377	}
	378
	379	static void
7632b30e	380	prog_clk(struct gt215_clk_priv *priv, int clk, int idx)
7c856522	381	{
7632b30e	382	struct gt215_clk_info *info = &priv->eng[idx];
7c856522 BS	383	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 \| info->clk);
	384	}
	385
70c7995d	386	static void
7632b30e	387	prog_host(struct gt215_clk_priv *priv)
70c7995d	388	{
7632b30e	389	struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];
70c7995d RS	390	u32 hsrc = (nv_rd32(priv, 0xc040));
	391
	392	switch (info->host_out) {
	393	case NVA3_HOST_277:
	394	if ((hsrc & 0x30000000) == 0) {
	395	nv_wr32(priv, 0xc040, hsrc \| 0x20000000);
	396	disable_clk_src(priv, 0x4194);
	397	}
	398	break;
	399	case NVA3_HOST_CLK:
	400	prog_clk(priv, 0x1d, nv_clk_src_host);
	401	if ((hsrc & 0x30000000) >= 0x20000000) {
	402	nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
	403	}
	404	break;
	405	default:
	406	break;
	407	}
	408
	409	/* This seems to be a clock gating factor on idle, always set to 64 */
	410	nv_wr32(priv, 0xc044, 0x3e);
	411	}
	412
3d40a717	413	static void
7632b30e	414	prog_core(struct gt215_clk_priv *priv, int idx)
3d40a717	415	{
7632b30e	416	struct gt215_clk_info *info = &priv->eng[idx];
3d40a717 RS	417	u32 fb_delay = nv_rd32(priv, 0x10002c);
	418
	419	if (fb_delay < info->fb_delay)
	420	nv_wr32(priv, 0x10002c, info->fb_delay);
	421
	422	prog_pll(priv, 0x00, 0x004200, idx);
	423
	424	if (fb_delay > info->fb_delay)
	425	nv_wr32(priv, 0x10002c, info->fb_delay);
	426	}
	427
7c856522	428	static int
7632b30e	429	gt215_clk_calc(struct nvkm_clk clk, struct nvkm_cstate cstate)
7c856522	430	{
7632b30e BS	431	struct gt215_clk_priv priv = (void )clk;
7632b30e BS	432	struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
7c856522 BS	433	int ret;
	434
	435	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) \|\|
	436	(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) \|\|
	437	(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) \|\|
70c7995d RS	438	(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) \|\|
70c7995d RS	439	(ret = calc_host(priv, cstate)))
7c856522 BS	440	return ret;
7c856522 BS	441
3d40a717 RS	442	/* XXX: Should be reading the highest bit in the VBIOS clock to decide
	443	* whether to use a PLL or not... but using a PLL defeats the purpose */
	444	if (core->pll) {
7632b30e BS	445	ret = gt215_clk_info(clk, 0x10,
	446	cstate->domain[nv_clk_src_core_intm],
	447	&priv->eng[nv_clk_src_core_intm]);
3d40a717 RS	448	if (ret < 0)
	449	return ret;
	450	}
	451
7c856522 BS	452	return 0;
	453	}
	454
	455	static int
7632b30e	456	gt215_clk_prog(struct nvkm_clk *clk)
7c856522	457	{
7632b30e BS	458	struct gt215_clk_priv priv = (void )clk;
7632b30e BS	459	struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
2fe7eaa0 RS	460	int ret = 0;
	461	unsigned long flags;
	462	unsigned long *f = &flags;
	463
7632b30e	464	ret = gt215_clk_pre(clk, f);
2fe7eaa0 RS	465	if (ret)
2fe7eaa0 RS	466	goto out;
3d40a717 RS	467
	468	if (core->pll)
	469	prog_core(priv, nv_clk_src_core_intm);
	470
	471	prog_core(priv, nv_clk_src_core);
7c856522 BS	472	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	473	prog_clk(priv, 0x20, nv_clk_src_disp);
	474	prog_clk(priv, 0x21, nv_clk_src_vdec);
70c7995d	475	prog_host(priv);
2fe7eaa0 RS	476
	477	out:
	478	if (ret == -EBUSY)
	479	f = NULL;
	480
7632b30e	481	gt215_clk_post(clk, f);
2fe7eaa0	482	return ret;
7c856522 BS	483	}
	484
	485	static void
7632b30e	486	gt215_clk_tidy(struct nvkm_clk *clk)
7c856522 BS	487	{
	488	}
	489
7632b30e BS	490	static struct nvkm_domain
7632b30e BS	491	gt215_domain[] = {
3d40a717 RS	492	{ nv_clk_src_crystal , 0xff },
	493	{ nv_clk_src_core , 0x00, 0, "core", 1000 },
	494	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
	495	{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
	496	{ nv_clk_src_vdec , 0x03 },
	497	{ nv_clk_src_disp , 0x04 },
	498	{ nv_clk_src_host , 0x05 },
	499	{ nv_clk_src_core_intm, 0x06 },
7c856522 BS	500	{ nv_clk_src_max }
7c856522 BS	501	};
d9c39056	502
8aceb7de	503	static int
7632b30e BS	504	gt215_clk_ctor(struct nvkm_object parent, struct nvkm_object engine,
	505	struct nvkm_oclass oclass, void data, u32 size,
	506	struct nvkm_object **pobject)
8aceb7de	507	{
7632b30e	508	struct gt215_clk_priv *priv;
8aceb7de BS	509	int ret;
8aceb7de BS	510
7632b30e BS	511	ret = nvkm_clk_create(parent, engine, oclass, gt215_domain,
7632b30e BS	512	NULL, 0, true, &priv);
8aceb7de BS	513	*pobject = nv_object(priv);
	514	if (ret)
	515	return ret;
	516
7632b30e BS	517	priv->base.read = gt215_clk_read;
	518	priv->base.calc = gt215_clk_calc;
	519	priv->base.prog = gt215_clk_prog;
	520	priv->base.tidy = gt215_clk_tidy;
8aceb7de BS	521	return 0;
	522	}
	523
7632b30e BS	524	struct nvkm_oclass
7632b30e BS	525	gt215_clk_oclass = {
f3867f43	526	.handle = NV_SUBDEV(CLK, 0xa3),
7632b30e BS	527	.ofuncs = &(struct nvkm_ofuncs) {
	528	.ctor = gt215_clk_ctor,
	529	.dtor = _nvkm_clk_dtor,
	530	.init = _nvkm_clk_init,
	531	.fini = _nvkm_clk_fini,
8aceb7de BS	532	},
8aceb7de BS	533	};