[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / nv50.h

#ifndef __NV50_CLK_H__
#define __NV50_CLK_H__
#define nv50_clk(p) container_of((p), struct nv50_clk, base)
#include "priv.h"

#include <subdev/bus/hwsq.h>

struct nv50_clk_hwsq {
	struct hwsq base;
	struct hwsq_reg r_fifo;
	struct hwsq_reg r_spll[2];
	struct hwsq_reg r_nvpll[2];
	struct hwsq_reg r_divs;
	struct hwsq_reg r_mast;
};

struct nv50_clk {
	struct nvkm_clk base;
	struct nv50_clk_hwsq hwsq;
};

int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
		  bool, struct nvkm_clk **);
int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src);
int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
int nv50_clk_prog(struct nvkm_clk *);
void nv50_clk_tidy(struct nvkm_clk *);
#endif
Commit	Line	Data
6625f55c BS	1	#ifndef __NV50_CLK_H__
	2	#define __NV50_CLK_H__
	3	#define nv50_clk(p) container_of((p), struct nv50_clk, base)
	4	#include "priv.h"
	5
7c856522	6	#include <subdev/bus/hwsq.h>
7c856522	7
f3867f43	8	struct nv50_clk_hwsq {
7c856522 BS	9	struct hwsq base;
	10	struct hwsq_reg r_fifo;
	11	struct hwsq_reg r_spll[2];
	12	struct hwsq_reg r_nvpll[2];
	13	struct hwsq_reg r_divs;
	14	struct hwsq_reg r_mast;
	15	};
	16
3eca809b	17	struct nv50_clk {
7632b30e	18	struct nvkm_clk base;
f3867f43	19	struct nv50_clk_hwsq hwsq;
7c856522 BS	20	};
7c856522 BS	21
6625f55c BS	22	int nv50_clk_new_(const struct nvkm_clk_func , struct nvkm_device , int,
	23	bool, struct nvkm_clk **);
	24	int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src);
	25	int nv50_clk_calc(struct nvkm_clk , struct nvkm_cstate );
	26	int nv50_clk_prog(struct nvkm_clk *);
	27	void nv50_clk_tidy(struct nvkm_clk *);
7c856522	28	#endif