Commit | Line | Data |
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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
2ecef246 | 26 | #include <linux/module.h> |
559d6701 | 27 | #include <linux/io.h> |
a8a35931 | 28 | #include <linux/export.h> |
559d6701 TV |
29 | #include <linux/err.h> |
30 | #include <linux/delay.h> | |
559d6701 TV |
31 | #include <linux/seq_file.h> |
32 | #include <linux/clk.h> | |
2639d6b9 | 33 | #include <linux/pinctrl/consumer.h> |
24e6289c | 34 | #include <linux/platform_device.h> |
4fbafaf3 | 35 | #include <linux/pm_runtime.h> |
185bae10 | 36 | #include <linux/gfp.h> |
33366d0e | 37 | #include <linux/sizes.h> |
be40eecf TV |
38 | #include <linux/mfd/syscon.h> |
39 | #include <linux/regmap.h> | |
2ecef246 | 40 | #include <linux/of.h> |
99767548 | 41 | #include <linux/regulator/consumer.h> |
cb17a4ae | 42 | #include <linux/suspend.h> |
736e60dd | 43 | #include <linux/component.h> |
559d6701 | 44 | |
32043da7 | 45 | #include "omapdss.h" |
559d6701 | 46 | #include "dss.h" |
6ec549e5 | 47 | #include "dss_features.h" |
559d6701 | 48 | |
559d6701 TV |
49 | #define DSS_SZ_REGS SZ_512 |
50 | ||
51 | struct dss_reg { | |
52 | u16 idx; | |
53 | }; | |
54 | ||
55 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
56 | ||
57 | #define DSS_REVISION DSS_REG(0x0000) | |
58 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
59 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
559d6701 TV |
60 | #define DSS_CONTROL DSS_REG(0x0040) |
61 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
62 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
63 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
64 | ||
65 | #define REG_GET(idx, start, end) \ | |
66 | FLD_GET(dss_read_reg(idx), start, end) | |
67 | ||
68 | #define REG_FLD_MOD(idx, val, start, end) \ | |
69 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
70 | ||
185bae10 CM |
71 | struct dss_features { |
72 | u8 fck_div_max; | |
73 | u8 dss_fck_multiplier; | |
64ad846f | 74 | const char *parent_clk_name; |
234f9a22 | 75 | const enum omap_display_type *ports; |
387ce9f2 | 76 | int num_ports; |
064c2a47 | 77 | int (*dpi_select_source)(int port, enum omap_channel channel); |
c63b1ec0 TV |
78 | int (*select_lcd_source)(enum omap_channel channel, |
79 | enum dss_clk_source clk_src); | |
185bae10 CM |
80 | }; |
81 | ||
559d6701 | 82 | static struct { |
96c401bc | 83 | struct platform_device *pdev; |
559d6701 | 84 | void __iomem *base; |
be40eecf TV |
85 | struct regmap *syscon_pll_ctrl; |
86 | u32 syscon_pll_ctrl_offset; | |
4fbafaf3 | 87 | |
64ad846f | 88 | struct clk *parent_clk; |
4fbafaf3 | 89 | struct clk *dss_clk; |
5aaee69d | 90 | unsigned long dss_clk_rate; |
559d6701 TV |
91 | |
92 | unsigned long cache_req_pck; | |
93 | unsigned long cache_prate; | |
559d6701 TV |
94 | struct dispc_clock_info cache_dispc_cinfo; |
95 | ||
dc0352d1 TV |
96 | enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
97 | enum dss_clk_source dispc_clk_source; | |
98 | enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; | |
2f18c4d8 | 99 | |
69f06054 | 100 | bool ctx_valid; |
559d6701 | 101 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
185bae10 CM |
102 | |
103 | const struct dss_features *feat; | |
99767548 TV |
104 | |
105 | struct dss_pll *video1_pll; | |
106 | struct dss_pll *video2_pll; | |
559d6701 TV |
107 | } dss; |
108 | ||
235e7dba | 109 | static const char * const dss_generic_clk_source_names[] = { |
3b63ca75 TV |
110 | [DSS_CLK_SRC_FCK] = "FCK", |
111 | [DSS_CLK_SRC_PLL1_1] = "PLL1:1", | |
112 | [DSS_CLK_SRC_PLL1_2] = "PLL1:2", | |
b5d8c757 | 113 | [DSS_CLK_SRC_PLL1_3] = "PLL1:3", |
3b63ca75 TV |
114 | [DSS_CLK_SRC_PLL2_1] = "PLL2:1", |
115 | [DSS_CLK_SRC_PLL2_2] = "PLL2:2", | |
b5d8c757 TV |
116 | [DSS_CLK_SRC_PLL2_3] = "PLL2:3", |
117 | [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", | |
067a57e4 AT |
118 | }; |
119 | ||
f99467b3 TV |
120 | static bool dss_initialized; |
121 | ||
122 | bool omapdss_is_initialized(void) | |
123 | { | |
124 | return dss_initialized; | |
125 | } | |
126 | EXPORT_SYMBOL(omapdss_is_initialized); | |
127 | ||
559d6701 TV |
128 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
129 | { | |
130 | __raw_writel(val, dss.base + idx.idx); | |
131 | } | |
132 | ||
133 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
134 | { | |
135 | return __raw_readl(dss.base + idx.idx); | |
136 | } | |
137 | ||
138 | #define SR(reg) \ | |
139 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
140 | #define RR(reg) \ | |
141 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
142 | ||
4fbafaf3 | 143 | static void dss_save_context(void) |
559d6701 | 144 | { |
4fbafaf3 | 145 | DSSDBG("dss_save_context\n"); |
559d6701 | 146 | |
559d6701 TV |
147 | SR(CONTROL); |
148 | ||
6ec549e5 TV |
149 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
150 | OMAP_DISPLAY_TYPE_SDI) { | |
151 | SR(SDI_CONTROL); | |
152 | SR(PLL_CONTROL); | |
153 | } | |
69f06054 TV |
154 | |
155 | dss.ctx_valid = true; | |
156 | ||
157 | DSSDBG("context saved\n"); | |
559d6701 TV |
158 | } |
159 | ||
4fbafaf3 | 160 | static void dss_restore_context(void) |
559d6701 | 161 | { |
4fbafaf3 | 162 | DSSDBG("dss_restore_context\n"); |
559d6701 | 163 | |
69f06054 TV |
164 | if (!dss.ctx_valid) |
165 | return; | |
166 | ||
559d6701 TV |
167 | RR(CONTROL); |
168 | ||
6ec549e5 TV |
169 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
170 | OMAP_DISPLAY_TYPE_SDI) { | |
171 | RR(SDI_CONTROL); | |
172 | RR(PLL_CONTROL); | |
173 | } | |
69f06054 TV |
174 | |
175 | DSSDBG("context restored\n"); | |
559d6701 TV |
176 | } |
177 | ||
178 | #undef SR | |
179 | #undef RR | |
180 | ||
be40eecf TV |
181 | void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) |
182 | { | |
183 | unsigned shift; | |
184 | unsigned val; | |
185 | ||
186 | if (!dss.syscon_pll_ctrl) | |
187 | return; | |
188 | ||
189 | val = !enable; | |
190 | ||
191 | switch (pll_id) { | |
192 | case DSS_PLL_VIDEO1: | |
193 | shift = 0; | |
194 | break; | |
195 | case DSS_PLL_VIDEO2: | |
196 | shift = 1; | |
197 | break; | |
198 | case DSS_PLL_HDMI: | |
199 | shift = 2; | |
200 | break; | |
201 | default: | |
202 | DSSERR("illegal DSS PLL ID %d\n", pll_id); | |
203 | return; | |
204 | } | |
205 | ||
206 | regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, | |
207 | 1 << shift, val << shift); | |
208 | } | |
209 | ||
c63b1ec0 | 210 | static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, |
be40eecf TV |
211 | enum omap_channel channel) |
212 | { | |
213 | unsigned shift, val; | |
214 | ||
215 | if (!dss.syscon_pll_ctrl) | |
c63b1ec0 | 216 | return -EINVAL; |
be40eecf TV |
217 | |
218 | switch (channel) { | |
219 | case OMAP_DSS_CHANNEL_LCD: | |
220 | shift = 3; | |
221 | ||
c63b1ec0 TV |
222 | switch (clk_src) { |
223 | case DSS_CLK_SRC_PLL1_1: | |
be40eecf | 224 | val = 0; break; |
c63b1ec0 | 225 | case DSS_CLK_SRC_HDMI_PLL: |
be40eecf TV |
226 | val = 1; break; |
227 | default: | |
228 | DSSERR("error in PLL mux config for LCD\n"); | |
c63b1ec0 | 229 | return -EINVAL; |
be40eecf TV |
230 | } |
231 | ||
232 | break; | |
233 | case OMAP_DSS_CHANNEL_LCD2: | |
234 | shift = 5; | |
235 | ||
c63b1ec0 TV |
236 | switch (clk_src) { |
237 | case DSS_CLK_SRC_PLL1_3: | |
be40eecf | 238 | val = 0; break; |
c63b1ec0 | 239 | case DSS_CLK_SRC_PLL2_3: |
be40eecf | 240 | val = 1; break; |
c63b1ec0 | 241 | case DSS_CLK_SRC_HDMI_PLL: |
be40eecf TV |
242 | val = 2; break; |
243 | default: | |
244 | DSSERR("error in PLL mux config for LCD2\n"); | |
c63b1ec0 | 245 | return -EINVAL; |
be40eecf TV |
246 | } |
247 | ||
248 | break; | |
249 | case OMAP_DSS_CHANNEL_LCD3: | |
250 | shift = 7; | |
251 | ||
c63b1ec0 TV |
252 | switch (clk_src) { |
253 | case DSS_CLK_SRC_PLL2_1: | |
be40eecf | 254 | val = 0; break; |
c63b1ec0 TV |
255 | case DSS_CLK_SRC_PLL1_3: |
256 | val = 1; break; | |
257 | case DSS_CLK_SRC_HDMI_PLL: | |
be40eecf TV |
258 | val = 2; break; |
259 | default: | |
260 | DSSERR("error in PLL mux config for LCD3\n"); | |
c63b1ec0 | 261 | return -EINVAL; |
be40eecf TV |
262 | } |
263 | ||
264 | break; | |
265 | default: | |
266 | DSSERR("error in PLL mux config\n"); | |
c63b1ec0 | 267 | return -EINVAL; |
be40eecf TV |
268 | } |
269 | ||
270 | regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, | |
271 | 0x3 << shift, val << shift); | |
c63b1ec0 TV |
272 | |
273 | return 0; | |
be40eecf TV |
274 | } |
275 | ||
889b4fd7 | 276 | void dss_sdi_init(int datapairs) |
559d6701 TV |
277 | { |
278 | u32 l; | |
279 | ||
280 | BUG_ON(datapairs > 3 || datapairs < 1); | |
281 | ||
282 | l = dss_read_reg(DSS_SDI_CONTROL); | |
283 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
284 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
285 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
286 | dss_write_reg(DSS_SDI_CONTROL, l); | |
287 | ||
288 | l = dss_read_reg(DSS_PLL_CONTROL); | |
289 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
290 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
291 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
292 | dss_write_reg(DSS_PLL_CONTROL, l); | |
293 | } | |
294 | ||
295 | int dss_sdi_enable(void) | |
296 | { | |
297 | unsigned long timeout; | |
298 | ||
299 | dispc_pck_free_enable(1); | |
300 | ||
301 | /* Reset SDI PLL */ | |
302 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
303 | udelay(1); /* wait 2x PCLK */ | |
304 | ||
305 | /* Lock SDI PLL */ | |
306 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
307 | ||
308 | /* Waiting for PLL lock request to complete */ | |
309 | timeout = jiffies + msecs_to_jiffies(500); | |
310 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
311 | if (time_after_eq(jiffies, timeout)) { | |
312 | DSSERR("PLL lock request timed out\n"); | |
313 | goto err1; | |
314 | } | |
315 | } | |
316 | ||
317 | /* Clearing PLL_GO bit */ | |
318 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
319 | ||
320 | /* Waiting for PLL to lock */ | |
321 | timeout = jiffies + msecs_to_jiffies(500); | |
322 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
323 | if (time_after_eq(jiffies, timeout)) { | |
324 | DSSERR("PLL lock timed out\n"); | |
325 | goto err1; | |
326 | } | |
327 | } | |
328 | ||
329 | dispc_lcd_enable_signal(1); | |
330 | ||
331 | /* Waiting for SDI reset to complete */ | |
332 | timeout = jiffies + msecs_to_jiffies(500); | |
333 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
334 | if (time_after_eq(jiffies, timeout)) { | |
335 | DSSERR("SDI reset timed out\n"); | |
336 | goto err2; | |
337 | } | |
338 | } | |
339 | ||
340 | return 0; | |
341 | ||
342 | err2: | |
343 | dispc_lcd_enable_signal(0); | |
344 | err1: | |
345 | /* Reset SDI PLL */ | |
346 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
347 | ||
348 | dispc_pck_free_enable(0); | |
349 | ||
350 | return -ETIMEDOUT; | |
351 | } | |
352 | ||
353 | void dss_sdi_disable(void) | |
354 | { | |
355 | dispc_lcd_enable_signal(0); | |
356 | ||
357 | dispc_pck_free_enable(0); | |
358 | ||
359 | /* Reset SDI PLL */ | |
360 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
361 | } | |
362 | ||
407bd564 | 363 | const char *dss_get_clk_source_name(enum dss_clk_source clk_src) |
067a57e4 | 364 | { |
235e7dba | 365 | return dss_generic_clk_source_names[clk_src]; |
067a57e4 AT |
366 | } |
367 | ||
559d6701 TV |
368 | void dss_dump_clocks(struct seq_file *s) |
369 | { | |
557a1544 | 370 | const char *fclk_name; |
0acf659f | 371 | unsigned long fclk_rate; |
559d6701 | 372 | |
4fbafaf3 TV |
373 | if (dss_runtime_get()) |
374 | return; | |
559d6701 | 375 | |
559d6701 TV |
376 | seq_printf(s, "- DSS -\n"); |
377 | ||
3b63ca75 | 378 | fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); |
4fbafaf3 | 379 | fclk_rate = clk_get_rate(dss.dss_clk); |
559d6701 | 380 | |
557a1544 TV |
381 | seq_printf(s, "%s = %lu\n", |
382 | fclk_name, | |
9c15d762 | 383 | fclk_rate); |
559d6701 | 384 | |
4fbafaf3 | 385 | dss_runtime_put(); |
559d6701 TV |
386 | } |
387 | ||
e40402cf | 388 | static void dss_dump_regs(struct seq_file *s) |
559d6701 TV |
389 | { |
390 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
391 | ||
4fbafaf3 TV |
392 | if (dss_runtime_get()) |
393 | return; | |
559d6701 TV |
394 | |
395 | DUMPREG(DSS_REVISION); | |
396 | DUMPREG(DSS_SYSCONFIG); | |
397 | DUMPREG(DSS_SYSSTATUS); | |
559d6701 | 398 | DUMPREG(DSS_CONTROL); |
6ec549e5 TV |
399 | |
400 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
401 | OMAP_DISPLAY_TYPE_SDI) { | |
402 | DUMPREG(DSS_SDI_CONTROL); | |
403 | DUMPREG(DSS_PLL_CONTROL); | |
404 | DUMPREG(DSS_SDI_STATUS); | |
405 | } | |
559d6701 | 406 | |
4fbafaf3 | 407 | dss_runtime_put(); |
559d6701 TV |
408 | #undef DUMPREG |
409 | } | |
410 | ||
c63b1ec0 TV |
411 | static int dss_get_channel_index(enum omap_channel channel) |
412 | { | |
413 | switch (channel) { | |
414 | case OMAP_DSS_CHANNEL_LCD: | |
415 | return 0; | |
416 | case OMAP_DSS_CHANNEL_LCD2: | |
417 | return 1; | |
418 | case OMAP_DSS_CHANNEL_LCD3: | |
419 | return 2; | |
420 | default: | |
421 | WARN_ON(1); | |
422 | return 0; | |
423 | } | |
424 | } | |
425 | ||
dc0352d1 | 426 | static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) |
2f18c4d8 TV |
427 | { |
428 | int b; | |
ea75159e | 429 | u8 start, end; |
2f18c4d8 | 430 | |
c63b1ec0 TV |
431 | /* |
432 | * We always use PRCM clock as the DISPC func clock, except on DSS3, | |
433 | * where we don't have separate DISPC and LCD clock sources. | |
434 | */ | |
435 | if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC) && | |
436 | clk_src != DSS_CLK_SRC_FCK)) | |
437 | return; | |
438 | ||
66534e8e | 439 | switch (clk_src) { |
3b63ca75 | 440 | case DSS_CLK_SRC_FCK: |
66534e8e TA |
441 | b = 0; |
442 | break; | |
3b63ca75 | 443 | case DSS_CLK_SRC_PLL1_1: |
66534e8e | 444 | b = 1; |
66534e8e | 445 | break; |
3b63ca75 | 446 | case DSS_CLK_SRC_PLL2_1: |
5a8b572d | 447 | b = 2; |
5a8b572d | 448 | break; |
66534e8e TA |
449 | default: |
450 | BUG(); | |
c6eee968 | 451 | return; |
66534e8e | 452 | } |
e406f907 | 453 | |
ea75159e TA |
454 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
455 | ||
456 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ | |
2f18c4d8 TV |
457 | |
458 | dss.dispc_clk_source = clk_src; | |
459 | } | |
460 | ||
5a8b572d | 461 | void dss_select_dsi_clk_source(int dsi_module, |
dc0352d1 | 462 | enum dss_clk_source clk_src) |
559d6701 | 463 | { |
a2e5d827 | 464 | int b, pos; |
2f18c4d8 | 465 | |
66534e8e | 466 | switch (clk_src) { |
3b63ca75 | 467 | case DSS_CLK_SRC_FCK: |
66534e8e TA |
468 | b = 0; |
469 | break; | |
3b63ca75 | 470 | case DSS_CLK_SRC_PLL1_2: |
5a8b572d | 471 | BUG_ON(dsi_module != 0); |
66534e8e | 472 | b = 1; |
66534e8e | 473 | break; |
3b63ca75 | 474 | case DSS_CLK_SRC_PLL2_2: |
5a8b572d AT |
475 | BUG_ON(dsi_module != 1); |
476 | b = 1; | |
5a8b572d | 477 | break; |
66534e8e TA |
478 | default: |
479 | BUG(); | |
c6eee968 | 480 | return; |
66534e8e | 481 | } |
e406f907 | 482 | |
a2e5d827 AT |
483 | pos = dsi_module == 0 ? 1 : 10; |
484 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ | |
2f18c4d8 | 485 | |
5a8b572d | 486 | dss.dsi_clk_source[dsi_module] = clk_src; |
559d6701 TV |
487 | } |
488 | ||
c63b1ec0 TV |
489 | static int dss_lcd_clk_mux_dra7(enum omap_channel channel, |
490 | enum dss_clk_source clk_src) | |
491 | { | |
492 | const u8 ctrl_bits[] = { | |
493 | [OMAP_DSS_CHANNEL_LCD] = 0, | |
494 | [OMAP_DSS_CHANNEL_LCD2] = 12, | |
495 | [OMAP_DSS_CHANNEL_LCD3] = 19, | |
496 | }; | |
497 | ||
498 | u8 ctrl_bit = ctrl_bits[channel]; | |
499 | int r; | |
500 | ||
501 | if (clk_src == DSS_CLK_SRC_FCK) { | |
502 | /* LCDx_CLK_SWITCH */ | |
503 | REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); | |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | r = dss_ctrl_pll_set_control_mux(clk_src, channel); | |
508 | if (r) | |
509 | return r; | |
510 | ||
511 | REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | static int dss_lcd_clk_mux_omap5(enum omap_channel channel, | |
517 | enum dss_clk_source clk_src) | |
518 | { | |
519 | const u8 ctrl_bits[] = { | |
520 | [OMAP_DSS_CHANNEL_LCD] = 0, | |
521 | [OMAP_DSS_CHANNEL_LCD2] = 12, | |
522 | [OMAP_DSS_CHANNEL_LCD3] = 19, | |
523 | }; | |
524 | const enum dss_clk_source allowed_plls[] = { | |
525 | [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, | |
526 | [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, | |
527 | [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, | |
528 | }; | |
529 | ||
530 | u8 ctrl_bit = ctrl_bits[channel]; | |
531 | ||
532 | if (clk_src == DSS_CLK_SRC_FCK) { | |
533 | /* LCDx_CLK_SWITCH */ | |
534 | REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); | |
535 | return -EINVAL; | |
536 | } | |
537 | ||
538 | if (WARN_ON(allowed_plls[channel] != clk_src)) | |
539 | return -EINVAL; | |
540 | ||
541 | REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int dss_lcd_clk_mux_omap4(enum omap_channel channel, | |
547 | enum dss_clk_source clk_src) | |
548 | { | |
549 | const u8 ctrl_bits[] = { | |
550 | [OMAP_DSS_CHANNEL_LCD] = 0, | |
551 | [OMAP_DSS_CHANNEL_LCD2] = 12, | |
552 | }; | |
553 | const enum dss_clk_source allowed_plls[] = { | |
554 | [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, | |
555 | [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, | |
556 | }; | |
557 | ||
558 | u8 ctrl_bit = ctrl_bits[channel]; | |
559 | ||
560 | if (clk_src == DSS_CLK_SRC_FCK) { | |
561 | /* LCDx_CLK_SWITCH */ | |
562 | REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); | |
563 | return 0; | |
564 | } | |
565 | ||
566 | if (WARN_ON(allowed_plls[channel] != clk_src)) | |
567 | return -EINVAL; | |
568 | ||
569 | REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
ea75159e | 574 | void dss_select_lcd_clk_source(enum omap_channel channel, |
dc0352d1 | 575 | enum dss_clk_source clk_src) |
ea75159e | 576 | { |
c63b1ec0 TV |
577 | int idx = dss_get_channel_index(channel); |
578 | int r; | |
ea75159e | 579 | |
a5b8399f TV |
580 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { |
581 | dss_select_dispc_clk_source(clk_src); | |
c63b1ec0 | 582 | dss.lcd_clk_source[idx] = clk_src; |
ea75159e | 583 | return; |
a5b8399f | 584 | } |
ea75159e | 585 | |
c63b1ec0 TV |
586 | r = dss.feat->select_lcd_source(channel, clk_src); |
587 | if (r) | |
c6eee968 | 588 | return; |
ea75159e | 589 | |
c63b1ec0 | 590 | dss.lcd_clk_source[idx] = clk_src; |
ea75159e TA |
591 | } |
592 | ||
dc0352d1 | 593 | enum dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 594 | { |
2f18c4d8 | 595 | return dss.dispc_clk_source; |
559d6701 TV |
596 | } |
597 | ||
dc0352d1 | 598 | enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
559d6701 | 599 | { |
5a8b572d | 600 | return dss.dsi_clk_source[dsi_module]; |
559d6701 TV |
601 | } |
602 | ||
dc0352d1 | 603 | enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
ea75159e | 604 | { |
89976f29 | 605 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
c63b1ec0 TV |
606 | int idx = dss_get_channel_index(channel); |
607 | return dss.lcd_clk_source[idx]; | |
89976f29 AT |
608 | } else { |
609 | /* LCD_CLK source is the same as DISPC_FCLK source for | |
610 | * OMAP2 and OMAP3 */ | |
611 | return dss.dispc_clk_source; | |
612 | } | |
ea75159e TA |
613 | } |
614 | ||
688af02d TV |
615 | bool dss_div_calc(unsigned long pck, unsigned long fck_min, |
616 | dss_div_calc_func func, void *data) | |
43417823 TV |
617 | { |
618 | int fckd, fckd_start, fckd_stop; | |
619 | unsigned long fck; | |
620 | unsigned long fck_hw_max; | |
621 | unsigned long fckd_hw_max; | |
622 | unsigned long prate; | |
648a55e1 | 623 | unsigned m; |
43417823 | 624 | |
fc1fe6e7 TV |
625 | fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
626 | ||
64ad846f | 627 | if (dss.parent_clk == NULL) { |
fc1fe6e7 TV |
628 | unsigned pckd; |
629 | ||
630 | pckd = fck_hw_max / pck; | |
631 | ||
632 | fck = pck * pckd; | |
633 | ||
634 | fck = clk_round_rate(dss.dss_clk, fck); | |
635 | ||
d0f58bd3 | 636 | return func(fck, data); |
43417823 TV |
637 | } |
638 | ||
43417823 TV |
639 | fckd_hw_max = dss.feat->fck_div_max; |
640 | ||
648a55e1 | 641 | m = dss.feat->dss_fck_multiplier; |
ada9443f | 642 | prate = clk_get_rate(dss.parent_clk); |
43417823 TV |
643 | |
644 | fck_min = fck_min ? fck_min : 1; | |
645 | ||
648a55e1 TV |
646 | fckd_start = min(prate * m / fck_min, fckd_hw_max); |
647 | fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); | |
43417823 TV |
648 | |
649 | for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { | |
d0e224f9 | 650 | fck = DIV_ROUND_UP(prate, fckd) * m; |
43417823 | 651 | |
d0f58bd3 | 652 | if (func(fck, data)) |
43417823 TV |
653 | return true; |
654 | } | |
655 | ||
656 | return false; | |
657 | } | |
658 | ||
d0f58bd3 | 659 | int dss_set_fck_rate(unsigned long rate) |
559d6701 | 660 | { |
ada9443f | 661 | int r; |
559d6701 | 662 | |
ada9443f | 663 | DSSDBG("set fck to %lu\n", rate); |
559d6701 | 664 | |
ada9443f TV |
665 | r = clk_set_rate(dss.dss_clk, rate); |
666 | if (r) | |
667 | return r; | |
559d6701 | 668 | |
5aaee69d TV |
669 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); |
670 | ||
d0f58bd3 | 671 | WARN_ONCE(dss.dss_clk_rate != rate, |
648a55e1 | 672 | "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, |
d0f58bd3 | 673 | rate); |
559d6701 TV |
674 | |
675 | return 0; | |
676 | } | |
677 | ||
5aaee69d TV |
678 | unsigned long dss_get_dispc_clk_rate(void) |
679 | { | |
680 | return dss.dss_clk_rate; | |
681 | } | |
682 | ||
13a1a2b2 TV |
683 | static int dss_setup_default_clock(void) |
684 | { | |
685 | unsigned long max_dss_fck, prate; | |
d0f58bd3 | 686 | unsigned long fck; |
13a1a2b2 | 687 | unsigned fck_div; |
13a1a2b2 TV |
688 | int r; |
689 | ||
13a1a2b2 TV |
690 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
691 | ||
fc1fe6e7 TV |
692 | if (dss.parent_clk == NULL) { |
693 | fck = clk_round_rate(dss.dss_clk, max_dss_fck); | |
694 | } else { | |
695 | prate = clk_get_rate(dss.parent_clk); | |
13a1a2b2 | 696 | |
fc1fe6e7 TV |
697 | fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, |
698 | max_dss_fck); | |
d0e224f9 | 699 | fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; |
fc1fe6e7 | 700 | } |
13a1a2b2 | 701 | |
d0f58bd3 | 702 | r = dss_set_fck_rate(fck); |
13a1a2b2 TV |
703 | if (r) |
704 | return r; | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
559d6701 TV |
709 | void dss_set_venc_output(enum omap_dss_venc_type type) |
710 | { | |
711 | int l = 0; | |
712 | ||
713 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
714 | l = 0; | |
715 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
716 | l = 1; | |
717 | else | |
718 | BUG(); | |
719 | ||
720 | /* venc out selection. 0 = comp, 1 = svideo */ | |
721 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
722 | } | |
723 | ||
724 | void dss_set_dac_pwrdn_bgz(bool enable) | |
725 | { | |
726 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
727 | } | |
728 | ||
8aa2eed1 | 729 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) |
7ed024aa | 730 | { |
8aa2eed1 RN |
731 | enum omap_display_type dp; |
732 | dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); | |
733 | ||
734 | /* Complain about invalid selections */ | |
735 | WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); | |
736 | WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); | |
737 | ||
738 | /* Select only if we have options */ | |
739 | if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) | |
740 | REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ | |
7ed024aa M |
741 | } |
742 | ||
4a61e267 TV |
743 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) |
744 | { | |
745 | enum omap_display_type displays; | |
746 | ||
747 | displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); | |
748 | if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) | |
749 | return DSS_VENC_TV_CLK; | |
750 | ||
8aa2eed1 RN |
751 | if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) |
752 | return DSS_HDMI_M_PCLK; | |
753 | ||
4a61e267 TV |
754 | return REG_GET(DSS_CONTROL, 15, 15); |
755 | } | |
756 | ||
064c2a47 | 757 | static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) |
de09e455 TV |
758 | { |
759 | if (channel != OMAP_DSS_CHANNEL_LCD) | |
760 | return -EINVAL; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
064c2a47 | 765 | static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) |
de09e455 TV |
766 | { |
767 | int val; | |
768 | ||
769 | switch (channel) { | |
770 | case OMAP_DSS_CHANNEL_LCD2: | |
771 | val = 0; | |
772 | break; | |
773 | case OMAP_DSS_CHANNEL_DIGIT: | |
774 | val = 1; | |
775 | break; | |
776 | default: | |
777 | return -EINVAL; | |
778 | } | |
779 | ||
780 | REG_FLD_MOD(DSS_CONTROL, val, 17, 17); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
064c2a47 | 785 | static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) |
de09e455 TV |
786 | { |
787 | int val; | |
788 | ||
789 | switch (channel) { | |
790 | case OMAP_DSS_CHANNEL_LCD: | |
791 | val = 1; | |
792 | break; | |
793 | case OMAP_DSS_CHANNEL_LCD2: | |
794 | val = 2; | |
795 | break; | |
796 | case OMAP_DSS_CHANNEL_LCD3: | |
797 | val = 3; | |
798 | break; | |
799 | case OMAP_DSS_CHANNEL_DIGIT: | |
800 | val = 0; | |
801 | break; | |
802 | default: | |
803 | return -EINVAL; | |
804 | } | |
805 | ||
806 | REG_FLD_MOD(DSS_CONTROL, val, 17, 16); | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
6d817880 TV |
811 | static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) |
812 | { | |
813 | switch (port) { | |
814 | case 0: | |
815 | return dss_dpi_select_source_omap5(port, channel); | |
816 | case 1: | |
817 | if (channel != OMAP_DSS_CHANNEL_LCD2) | |
818 | return -EINVAL; | |
819 | break; | |
820 | case 2: | |
821 | if (channel != OMAP_DSS_CHANNEL_LCD3) | |
822 | return -EINVAL; | |
823 | break; | |
824 | default: | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
064c2a47 | 831 | int dss_dpi_select_source(int port, enum omap_channel channel) |
de09e455 | 832 | { |
064c2a47 | 833 | return dss.feat->dpi_select_source(port, channel); |
de09e455 TV |
834 | } |
835 | ||
8b9cb3a8 SG |
836 | static int dss_get_clocks(void) |
837 | { | |
4fbafaf3 | 838 | struct clk *clk; |
8b9cb3a8 | 839 | |
b2c9c8ee | 840 | clk = devm_clk_get(&dss.pdev->dev, "fck"); |
4fbafaf3 TV |
841 | if (IS_ERR(clk)) { |
842 | DSSERR("can't get clock fck\n"); | |
b2c9c8ee | 843 | return PTR_ERR(clk); |
a1a0dcca | 844 | } |
8b9cb3a8 | 845 | |
4fbafaf3 | 846 | dss.dss_clk = clk; |
8b9cb3a8 | 847 | |
64ad846f TV |
848 | if (dss.feat->parent_clk_name) { |
849 | clk = clk_get(NULL, dss.feat->parent_clk_name); | |
8ad9375f | 850 | if (IS_ERR(clk)) { |
64ad846f | 851 | DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); |
b2c9c8ee | 852 | return PTR_ERR(clk); |
8ad9375f AK |
853 | } |
854 | } else { | |
855 | clk = NULL; | |
94c042ce TV |
856 | } |
857 | ||
64ad846f | 858 | dss.parent_clk = clk; |
94c042ce | 859 | |
8b9cb3a8 | 860 | return 0; |
8b9cb3a8 SG |
861 | } |
862 | ||
863 | static void dss_put_clocks(void) | |
864 | { | |
64ad846f TV |
865 | if (dss.parent_clk) |
866 | clk_put(dss.parent_clk); | |
8b9cb3a8 SG |
867 | } |
868 | ||
99767548 | 869 | int dss_runtime_get(void) |
8b9cb3a8 | 870 | { |
4fbafaf3 | 871 | int r; |
8b9cb3a8 | 872 | |
4fbafaf3 | 873 | DSSDBG("dss_runtime_get\n"); |
8b9cb3a8 | 874 | |
4fbafaf3 TV |
875 | r = pm_runtime_get_sync(&dss.pdev->dev); |
876 | WARN_ON(r < 0); | |
877 | return r < 0 ? r : 0; | |
8b9cb3a8 SG |
878 | } |
879 | ||
99767548 | 880 | void dss_runtime_put(void) |
8b9cb3a8 | 881 | { |
4fbafaf3 | 882 | int r; |
8b9cb3a8 | 883 | |
4fbafaf3 | 884 | DSSDBG("dss_runtime_put\n"); |
8b9cb3a8 | 885 | |
0eaf9f52 | 886 | r = pm_runtime_put_sync(&dss.pdev->dev); |
5be3aebd | 887 | WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); |
8b9cb3a8 SG |
888 | } |
889 | ||
8b9cb3a8 | 890 | /* DEBUGFS */ |
1b3bcb33 | 891 | #if defined(CONFIG_OMAP2_DSS_DEBUGFS) |
8b9cb3a8 SG |
892 | void dss_debug_dump_clocks(struct seq_file *s) |
893 | { | |
8b9cb3a8 SG |
894 | dss_dump_clocks(s); |
895 | dispc_dump_clocks(s); | |
896 | #ifdef CONFIG_OMAP2_DSS_DSI | |
897 | dsi_dump_clocks(s); | |
898 | #endif | |
899 | } | |
900 | #endif | |
901 | ||
387ce9f2 | 902 | |
234f9a22 | 903 | static const enum omap_display_type omap2plus_ports[] = { |
387ce9f2 AT |
904 | OMAP_DISPLAY_TYPE_DPI, |
905 | }; | |
906 | ||
234f9a22 | 907 | static const enum omap_display_type omap34xx_ports[] = { |
387ce9f2 AT |
908 | OMAP_DISPLAY_TYPE_DPI, |
909 | OMAP_DISPLAY_TYPE_SDI, | |
910 | }; | |
911 | ||
6d817880 TV |
912 | static const enum omap_display_type dra7xx_ports[] = { |
913 | OMAP_DISPLAY_TYPE_DPI, | |
914 | OMAP_DISPLAY_TYPE_DPI, | |
915 | OMAP_DISPLAY_TYPE_DPI, | |
916 | }; | |
917 | ||
ede92695 | 918 | static const struct dss_features omap24xx_dss_feats = { |
6e555e27 TV |
919 | /* |
920 | * fck div max is really 16, but the divider range has gaps. The range | |
921 | * from 1 to 6 has no gaps, so let's use that as a max. | |
922 | */ | |
923 | .fck_div_max = 6, | |
84273a95 | 924 | .dss_fck_multiplier = 2, |
ada9443f | 925 | .parent_clk_name = "core_ck", |
de09e455 | 926 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
927 | .ports = omap2plus_ports, |
928 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
929 | }; |
930 | ||
ede92695 | 931 | static const struct dss_features omap34xx_dss_feats = { |
84273a95 TV |
932 | .fck_div_max = 16, |
933 | .dss_fck_multiplier = 2, | |
ada9443f | 934 | .parent_clk_name = "dpll4_ck", |
de09e455 | 935 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
936 | .ports = omap34xx_ports, |
937 | .num_ports = ARRAY_SIZE(omap34xx_ports), | |
84273a95 TV |
938 | }; |
939 | ||
ede92695 | 940 | static const struct dss_features omap3630_dss_feats = { |
84273a95 TV |
941 | .fck_div_max = 32, |
942 | .dss_fck_multiplier = 1, | |
ada9443f | 943 | .parent_clk_name = "dpll4_ck", |
de09e455 | 944 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
945 | .ports = omap2plus_ports, |
946 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
947 | }; |
948 | ||
ede92695 | 949 | static const struct dss_features omap44xx_dss_feats = { |
84273a95 TV |
950 | .fck_div_max = 32, |
951 | .dss_fck_multiplier = 1, | |
ada9443f | 952 | .parent_clk_name = "dpll_per_x2_ck", |
de09e455 | 953 | .dpi_select_source = &dss_dpi_select_source_omap4, |
387ce9f2 AT |
954 | .ports = omap2plus_ports, |
955 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
c63b1ec0 | 956 | .select_lcd_source = &dss_lcd_clk_mux_omap4, |
84273a95 TV |
957 | }; |
958 | ||
ede92695 | 959 | static const struct dss_features omap54xx_dss_feats = { |
84273a95 TV |
960 | .fck_div_max = 64, |
961 | .dss_fck_multiplier = 1, | |
ada9443f | 962 | .parent_clk_name = "dpll_per_x2_ck", |
de09e455 | 963 | .dpi_select_source = &dss_dpi_select_source_omap5, |
387ce9f2 AT |
964 | .ports = omap2plus_ports, |
965 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
c63b1ec0 | 966 | .select_lcd_source = &dss_lcd_clk_mux_omap5, |
84273a95 TV |
967 | }; |
968 | ||
ede92695 | 969 | static const struct dss_features am43xx_dss_feats = { |
d6279d4a SP |
970 | .fck_div_max = 0, |
971 | .dss_fck_multiplier = 0, | |
972 | .parent_clk_name = NULL, | |
973 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, | |
387ce9f2 AT |
974 | .ports = omap2plus_ports, |
975 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
d6279d4a SP |
976 | }; |
977 | ||
ede92695 | 978 | static const struct dss_features dra7xx_dss_feats = { |
6d817880 TV |
979 | .fck_div_max = 64, |
980 | .dss_fck_multiplier = 1, | |
981 | .parent_clk_name = "dpll_per_x2_ck", | |
982 | .dpi_select_source = &dss_dpi_select_source_dra7xx, | |
983 | .ports = dra7xx_ports, | |
984 | .num_ports = ARRAY_SIZE(dra7xx_ports), | |
c63b1ec0 | 985 | .select_lcd_source = &dss_lcd_clk_mux_dra7, |
6d817880 TV |
986 | }; |
987 | ||
ede92695 | 988 | static int dss_init_features(struct platform_device *pdev) |
185bae10 CM |
989 | { |
990 | const struct dss_features *src; | |
991 | struct dss_features *dst; | |
992 | ||
bd81ed08 | 993 | dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); |
185bae10 | 994 | if (!dst) { |
bd81ed08 | 995 | dev_err(&pdev->dev, "Failed to allocate local DSS Features\n"); |
185bae10 CM |
996 | return -ENOMEM; |
997 | } | |
998 | ||
b2c7d54f | 999 | switch (omapdss_get_version()) { |
bd81ed08 | 1000 | case OMAPDSS_VER_OMAP24xx: |
185bae10 | 1001 | src = &omap24xx_dss_feats; |
bd81ed08 TV |
1002 | break; |
1003 | ||
1004 | case OMAPDSS_VER_OMAP34xx_ES1: | |
1005 | case OMAPDSS_VER_OMAP34xx_ES3: | |
1006 | case OMAPDSS_VER_AM35xx: | |
185bae10 | 1007 | src = &omap34xx_dss_feats; |
bd81ed08 TV |
1008 | break; |
1009 | ||
1010 | case OMAPDSS_VER_OMAP3630: | |
185bae10 | 1011 | src = &omap3630_dss_feats; |
bd81ed08 TV |
1012 | break; |
1013 | ||
1014 | case OMAPDSS_VER_OMAP4430_ES1: | |
1015 | case OMAPDSS_VER_OMAP4430_ES2: | |
1016 | case OMAPDSS_VER_OMAP4: | |
185bae10 | 1017 | src = &omap44xx_dss_feats; |
bd81ed08 TV |
1018 | break; |
1019 | ||
1020 | case OMAPDSS_VER_OMAP5: | |
23362832 | 1021 | src = &omap54xx_dss_feats; |
bd81ed08 TV |
1022 | break; |
1023 | ||
d6279d4a SP |
1024 | case OMAPDSS_VER_AM43xx: |
1025 | src = &am43xx_dss_feats; | |
1026 | break; | |
1027 | ||
6d817880 TV |
1028 | case OMAPDSS_VER_DRA7xx: |
1029 | src = &dra7xx_dss_feats; | |
1030 | break; | |
1031 | ||
bd81ed08 | 1032 | default: |
185bae10 | 1033 | return -ENODEV; |
bd81ed08 | 1034 | } |
185bae10 CM |
1035 | |
1036 | memcpy(dst, src, sizeof(*dst)); | |
1037 | dss.feat = dst; | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
ede92695 | 1042 | static int dss_init_ports(struct platform_device *pdev) |
2ecef246 TV |
1043 | { |
1044 | struct device_node *parent = pdev->dev.of_node; | |
1045 | struct device_node *port; | |
1046 | int r; | |
1047 | ||
1048 | if (parent == NULL) | |
1049 | return 0; | |
1050 | ||
1051 | port = omapdss_of_get_next_port(parent, NULL); | |
00592772 | 1052 | if (!port) |
2ecef246 | 1053 | return 0; |
2ecef246 | 1054 | |
387ce9f2 AT |
1055 | if (dss.feat->num_ports == 0) |
1056 | return 0; | |
1057 | ||
2ecef246 | 1058 | do { |
387ce9f2 | 1059 | enum omap_display_type port_type; |
2ecef246 TV |
1060 | u32 reg; |
1061 | ||
1062 | r = of_property_read_u32(port, "reg", ®); | |
1063 | if (r) | |
1064 | reg = 0; | |
1065 | ||
387ce9f2 AT |
1066 | if (reg >= dss.feat->num_ports) |
1067 | continue; | |
2ecef246 | 1068 | |
387ce9f2 | 1069 | port_type = dss.feat->ports[reg]; |
2ecef246 | 1070 | |
387ce9f2 AT |
1071 | switch (port_type) { |
1072 | case OMAP_DISPLAY_TYPE_DPI: | |
1073 | dpi_init_port(pdev, port); | |
1074 | break; | |
1075 | case OMAP_DISPLAY_TYPE_SDI: | |
1076 | sdi_init_port(pdev, port); | |
1077 | break; | |
1078 | default: | |
1079 | break; | |
1080 | } | |
2ecef246 TV |
1081 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
ede92695 | 1086 | static void dss_uninit_ports(struct platform_device *pdev) |
2ecef246 | 1087 | { |
80eb6751 AT |
1088 | struct device_node *parent = pdev->dev.of_node; |
1089 | struct device_node *port; | |
1090 | ||
1091 | if (parent == NULL) | |
1092 | return; | |
1093 | ||
1094 | port = omapdss_of_get_next_port(parent, NULL); | |
1095 | if (!port) | |
1096 | return; | |
1097 | ||
387ce9f2 AT |
1098 | if (dss.feat->num_ports == 0) |
1099 | return; | |
2ecef246 | 1100 | |
387ce9f2 AT |
1101 | do { |
1102 | enum omap_display_type port_type; | |
1103 | u32 reg; | |
1104 | int r; | |
1105 | ||
1106 | r = of_property_read_u32(port, "reg", ®); | |
1107 | if (r) | |
1108 | reg = 0; | |
1109 | ||
1110 | if (reg >= dss.feat->num_ports) | |
1111 | continue; | |
1112 | ||
1113 | port_type = dss.feat->ports[reg]; | |
1114 | ||
1115 | switch (port_type) { | |
1116 | case OMAP_DISPLAY_TYPE_DPI: | |
1117 | dpi_uninit_port(port); | |
1118 | break; | |
1119 | case OMAP_DISPLAY_TYPE_SDI: | |
1120 | sdi_uninit_port(port); | |
1121 | break; | |
1122 | default: | |
1123 | break; | |
1124 | } | |
1125 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); | |
2ecef246 TV |
1126 | } |
1127 | ||
7e328f5a TV |
1128 | static int dss_video_pll_probe(struct platform_device *pdev) |
1129 | { | |
1130 | struct device_node *np = pdev->dev.of_node; | |
1131 | struct regulator *pll_regulator; | |
1132 | int r; | |
1133 | ||
1134 | if (!np) | |
1135 | return 0; | |
1136 | ||
1137 | if (of_property_read_bool(np, "syscon-pll-ctrl")) { | |
1138 | dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, | |
1139 | "syscon-pll-ctrl"); | |
1140 | if (IS_ERR(dss.syscon_pll_ctrl)) { | |
1141 | dev_err(&pdev->dev, | |
1142 | "failed to get syscon-pll-ctrl regmap\n"); | |
1143 | return PTR_ERR(dss.syscon_pll_ctrl); | |
1144 | } | |
1145 | ||
1146 | if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, | |
1147 | &dss.syscon_pll_ctrl_offset)) { | |
1148 | dev_err(&pdev->dev, | |
1149 | "failed to get syscon-pll-ctrl offset\n"); | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); | |
1155 | if (IS_ERR(pll_regulator)) { | |
1156 | r = PTR_ERR(pll_regulator); | |
1157 | ||
1158 | switch (r) { | |
1159 | case -ENOENT: | |
1160 | pll_regulator = NULL; | |
1161 | break; | |
1162 | ||
1163 | case -EPROBE_DEFER: | |
1164 | return -EPROBE_DEFER; | |
1165 | ||
1166 | default: | |
1167 | DSSERR("can't get DPLL VDDA regulator\n"); | |
1168 | return r; | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | if (of_property_match_string(np, "reg-names", "pll1") >= 0) { | |
1173 | dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); | |
1174 | if (IS_ERR(dss.video1_pll)) | |
1175 | return PTR_ERR(dss.video1_pll); | |
1176 | } | |
1177 | ||
1178 | if (of_property_match_string(np, "reg-names", "pll2") >= 0) { | |
1179 | dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); | |
1180 | if (IS_ERR(dss.video2_pll)) { | |
1181 | dss_video_pll_uninit(dss.video1_pll); | |
1182 | return PTR_ERR(dss.video2_pll); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
96c401bc | 1189 | /* DSS HW IP initialisation */ |
736e60dd | 1190 | static int dss_bind(struct device *dev) |
96c401bc | 1191 | { |
736e60dd | 1192 | struct platform_device *pdev = to_platform_device(dev); |
b98482ed TV |
1193 | struct resource *dss_mem; |
1194 | u32 rev; | |
96c401bc | 1195 | int r; |
96c401bc SG |
1196 | |
1197 | dss.pdev = pdev; | |
1198 | ||
bd81ed08 | 1199 | r = dss_init_features(dss.pdev); |
185bae10 CM |
1200 | if (r) |
1201 | return r; | |
1202 | ||
b98482ed TV |
1203 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
1204 | if (!dss_mem) { | |
1205 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
cd3b3449 | 1206 | return -EINVAL; |
b98482ed | 1207 | } |
cd3b3449 | 1208 | |
6e2a14d2 JL |
1209 | dss.base = devm_ioremap(&pdev->dev, dss_mem->start, |
1210 | resource_size(dss_mem)); | |
b98482ed TV |
1211 | if (!dss.base) { |
1212 | DSSERR("can't ioremap DSS\n"); | |
cd3b3449 | 1213 | return -ENOMEM; |
b98482ed TV |
1214 | } |
1215 | ||
8b9cb3a8 SG |
1216 | r = dss_get_clocks(); |
1217 | if (r) | |
cd3b3449 | 1218 | return r; |
8b9cb3a8 | 1219 | |
13a1a2b2 TV |
1220 | r = dss_setup_default_clock(); |
1221 | if (r) | |
1222 | goto err_setup_clocks; | |
1223 | ||
7e328f5a TV |
1224 | r = dss_video_pll_probe(pdev); |
1225 | if (r) | |
1226 | goto err_pll_init; | |
1227 | ||
f5a1a1f8 TV |
1228 | r = dss_init_ports(pdev); |
1229 | if (r) | |
1230 | goto err_init_ports; | |
1231 | ||
4fbafaf3 | 1232 | pm_runtime_enable(&pdev->dev); |
b98482ed | 1233 | |
4fbafaf3 TV |
1234 | r = dss_runtime_get(); |
1235 | if (r) | |
1236 | goto err_runtime_get; | |
b98482ed | 1237 | |
5aaee69d TV |
1238 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); |
1239 | ||
b98482ed TV |
1240 | /* Select DPLL */ |
1241 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
1242 | ||
3b63ca75 | 1243 | dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); |
a5b8399f | 1244 | |
b98482ed TV |
1245 | #ifdef CONFIG_OMAP2_DSS_VENC |
1246 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
1247 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
1248 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
1249 | #endif | |
3b63ca75 TV |
1250 | dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; |
1251 | dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; | |
1252 | dss.dispc_clk_source = DSS_CLK_SRC_FCK; | |
1253 | dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; | |
1254 | dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; | |
96c401bc | 1255 | |
b98482ed TV |
1256 | rev = dss_read_reg(DSS_REVISION); |
1257 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
1258 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
1259 | ||
4fbafaf3 | 1260 | dss_runtime_put(); |
b98482ed | 1261 | |
736e60dd TV |
1262 | r = component_bind_all(&pdev->dev, NULL); |
1263 | if (r) | |
1264 | goto err_component; | |
1265 | ||
e40402cf TV |
1266 | dss_debugfs_create_file("dss", dss_dump_regs); |
1267 | ||
cb17a4ae TV |
1268 | pm_set_vt_switch(0); |
1269 | ||
f99467b3 TV |
1270 | dss_initialized = true; |
1271 | ||
8b9cb3a8 | 1272 | return 0; |
a57dd4fe | 1273 | |
736e60dd | 1274 | err_component: |
7e328f5a TV |
1275 | err_runtime_get: |
1276 | pm_runtime_disable(&pdev->dev); | |
f5a1a1f8 TV |
1277 | dss_uninit_ports(pdev); |
1278 | err_init_ports: | |
99767548 TV |
1279 | if (dss.video1_pll) |
1280 | dss_video_pll_uninit(dss.video1_pll); | |
1281 | ||
1282 | if (dss.video2_pll) | |
1283 | dss_video_pll_uninit(dss.video2_pll); | |
7e328f5a | 1284 | err_pll_init: |
13a1a2b2 | 1285 | err_setup_clocks: |
8b9cb3a8 | 1286 | dss_put_clocks(); |
96c401bc SG |
1287 | return r; |
1288 | } | |
1289 | ||
736e60dd | 1290 | static void dss_unbind(struct device *dev) |
96c401bc | 1291 | { |
736e60dd TV |
1292 | struct platform_device *pdev = to_platform_device(dev); |
1293 | ||
f99467b3 TV |
1294 | dss_initialized = false; |
1295 | ||
736e60dd TV |
1296 | component_unbind_all(&pdev->dev, NULL); |
1297 | ||
99767548 TV |
1298 | if (dss.video1_pll) |
1299 | dss_video_pll_uninit(dss.video1_pll); | |
1300 | ||
1301 | if (dss.video2_pll) | |
1302 | dss_video_pll_uninit(dss.video2_pll); | |
1303 | ||
2ac6a1aa | 1304 | dss_uninit_ports(pdev); |
2ecef246 | 1305 | |
4fbafaf3 | 1306 | pm_runtime_disable(&pdev->dev); |
8b9cb3a8 SG |
1307 | |
1308 | dss_put_clocks(); | |
736e60dd TV |
1309 | } |
1310 | ||
1311 | static const struct component_master_ops dss_component_ops = { | |
1312 | .bind = dss_bind, | |
1313 | .unbind = dss_unbind, | |
1314 | }; | |
b98482ed | 1315 | |
736e60dd TV |
1316 | static int dss_component_compare(struct device *dev, void *data) |
1317 | { | |
1318 | struct device *child = data; | |
1319 | return dev == child; | |
1320 | } | |
1321 | ||
1322 | static int dss_add_child_component(struct device *dev, void *data) | |
1323 | { | |
1324 | struct component_match **match = data; | |
1325 | ||
0438ec90 TV |
1326 | /* |
1327 | * HACK | |
1328 | * We don't have a working driver for rfbi, so skip it here always. | |
1329 | * Otherwise dss will never get probed successfully, as it will wait | |
1330 | * for rfbi to get probed. | |
1331 | */ | |
1332 | if (strstr(dev_name(dev), "rfbi")) | |
1333 | return 0; | |
1334 | ||
736e60dd TV |
1335 | component_match_add(dev->parent, match, dss_component_compare, dev); |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
1340 | static int dss_probe(struct platform_device *pdev) | |
1341 | { | |
1342 | struct component_match *match = NULL; | |
1343 | int r; | |
1344 | ||
1345 | /* add all the child devices as components */ | |
1346 | device_for_each_child(&pdev->dev, &match, dss_add_child_component); | |
1347 | ||
1348 | r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); | |
1349 | if (r) | |
1350 | return r; | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | static int dss_remove(struct platform_device *pdev) | |
1356 | { | |
1357 | component_master_del(&pdev->dev, &dss_component_ops); | |
96c401bc SG |
1358 | return 0; |
1359 | } | |
1360 | ||
4fbafaf3 TV |
1361 | static int dss_runtime_suspend(struct device *dev) |
1362 | { | |
1363 | dss_save_context(); | |
a8081d31 | 1364 | dss_set_min_bus_tput(dev, 0); |
5038bb8c DG |
1365 | |
1366 | pinctrl_pm_select_sleep_state(dev); | |
1367 | ||
4fbafaf3 TV |
1368 | return 0; |
1369 | } | |
1370 | ||
1371 | static int dss_runtime_resume(struct device *dev) | |
1372 | { | |
a8081d31 | 1373 | int r; |
5038bb8c DG |
1374 | |
1375 | pinctrl_pm_select_default_state(dev); | |
1376 | ||
a8081d31 TV |
1377 | /* |
1378 | * Set an arbitrarily high tput request to ensure OPP100. | |
1379 | * What we should really do is to make a request to stay in OPP100, | |
1380 | * without any tput requirements, but that is not currently possible | |
1381 | * via the PM layer. | |
1382 | */ | |
1383 | ||
1384 | r = dss_set_min_bus_tput(dev, 1000000000); | |
1385 | if (r) | |
1386 | return r; | |
1387 | ||
39020710 | 1388 | dss_restore_context(); |
4fbafaf3 TV |
1389 | return 0; |
1390 | } | |
1391 | ||
1392 | static const struct dev_pm_ops dss_pm_ops = { | |
1393 | .runtime_suspend = dss_runtime_suspend, | |
1394 | .runtime_resume = dss_runtime_resume, | |
1395 | }; | |
1396 | ||
2ecef246 TV |
1397 | static const struct of_device_id dss_of_match[] = { |
1398 | { .compatible = "ti,omap2-dss", }, | |
1399 | { .compatible = "ti,omap3-dss", }, | |
1400 | { .compatible = "ti,omap4-dss", }, | |
2e7e6b68 | 1401 | { .compatible = "ti,omap5-dss", }, |
6d817880 | 1402 | { .compatible = "ti,dra7-dss", }, |
2ecef246 TV |
1403 | {}, |
1404 | }; | |
1405 | ||
1406 | MODULE_DEVICE_TABLE(of, dss_of_match); | |
1407 | ||
96c401bc | 1408 | static struct platform_driver omap_dsshw_driver = { |
736e60dd TV |
1409 | .probe = dss_probe, |
1410 | .remove = dss_remove, | |
96c401bc SG |
1411 | .driver = { |
1412 | .name = "omapdss_dss", | |
4fbafaf3 | 1413 | .pm = &dss_pm_ops, |
2ecef246 | 1414 | .of_match_table = dss_of_match, |
422ccbd5 | 1415 | .suppress_bind_attrs = true, |
96c401bc SG |
1416 | }, |
1417 | }; | |
1418 | ||
6e7e8f06 | 1419 | int __init dss_init_platform_driver(void) |
96c401bc | 1420 | { |
736e60dd | 1421 | return platform_driver_register(&omap_dsshw_driver); |
96c401bc SG |
1422 | } |
1423 | ||
1424 | void dss_uninit_platform_driver(void) | |
1425 | { | |
04c742c3 | 1426 | platform_driver_unregister(&omap_dsshw_driver); |
96c401bc | 1427 | } |