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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / dss_features.c
CommitLineData
e1ef4d23
AT		 1/*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
eda34273 21#include <linux/module.h>
e1ef4d23
AT		 22#include <linux/types.h>
23#include <linux/err.h>
24#include <linux/slab.h>
25
32043da7 26#include "omapdss.h"
067a57e4 27#include "dss.h"
e1ef4d23
AT		 28#include "dss_features.h"
29
30/* Defines a generic omap register field */
31struct dss_reg_field {
e1ef4d23
AT		 32 u8 start, end;
33};
34
31ef8237
TA		 35struct dss_param_range {
36 int min, max;
37};
38
e1ef4d23
AT		 39struct omap_dss_features {
40 const struct dss_reg_field *reg_fields;
41 const int num_reg_fields;
42
c124f23d
AT		 43 const enum dss_feat_id *features;
44 const int num_features;
e1ef4d23
AT		 45
46 const int num_mgrs;
47 const int num_ovls;
48 const enum omap_display_type *supported_displays;
97f01b3a 49 const enum omap_dss_output_id *supported_outputs;
e1ef4d23 50 const enum omap_color_mode *supported_color_modes;
67019db8 51 const enum omap_overlay_caps *overlay_caps;
31ef8237 52 const struct dss_param_range *dss_params;
5ed8cf5b 53
65e006ff
CM		 54 const enum omap_dss_rotation_type supported_rotation_types;
55
5ed8cf5b
TV		 56 const u32 buffer_size_unit;
57 const u32 burst_size_unit;
e1ef4d23
AT		 58};
59
60/* This struct is assigned to one of the below during initialization */
ea290333 61static const struct omap_dss_features *omap_current_dss_features;
e1ef4d23
AT		 62
63static const struct dss_reg_field omap2_dss_reg_fields[] = {
49641116
TA		 64 [FEAT_REG_FIRHINC] = { 11, 0 },
65 [FEAT_REG_FIRVINC] = { 27, 16 },
66 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
67 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
68 [FEAT_REG_FIFOSIZE] = { 8, 0 },
69 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
70 [FEAT_REG_VERTICALACCU] = { 25, 16 },
71 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
e1ef4d23
AT		 72};
73
74static const struct dss_reg_field omap3_dss_reg_fields[] = {
49641116
TA		 75 [FEAT_REG_FIRHINC] = { 12, 0 },
76 [FEAT_REG_FIRVINC] = { 28, 16 },
77 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
78 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
79 [FEAT_REG_FIFOSIZE] = { 10, 0 },
80 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
81 [FEAT_REG_VERTICALACCU] = { 25, 16 },
82 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
87a7484b
AT		 83};
84
d6279d4a
SP		 85static const struct dss_reg_field am43xx_dss_reg_fields[] = {
86 [FEAT_REG_FIRHINC] = { 12, 0 },
87 [FEAT_REG_FIRVINC] = { 28, 16 },
88 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
89 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
90 [FEAT_REG_FIFOSIZE] = { 10, 0 },
91 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
92 [FEAT_REG_VERTICALACCU] = { 25, 16 },
93 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
94};
95
87a7484b 96static const struct dss_reg_field omap4_dss_reg_fields[] = {
49641116
TA		 97 [FEAT_REG_FIRHINC] = { 12, 0 },
98 [FEAT_REG_FIRVINC] = { 28, 16 },
99 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
100 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
101 [FEAT_REG_FIFOSIZE] = { 15, 0 },
102 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
103 [FEAT_REG_VERTICALACCU] = { 26, 16 },
104 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
e1ef4d23
AT		 105};
106
23362832
AT		 107static const struct dss_reg_field omap5_dss_reg_fields[] = {
108 [FEAT_REG_FIRHINC] = { 12, 0 },
109 [FEAT_REG_FIRVINC] = { 28, 16 },
110 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
111 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
112 [FEAT_REG_FIFOSIZE] = { 15, 0 },
113 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
114 [FEAT_REG_VERTICALACCU] = { 26, 16 },
115 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
23362832
AT		 116};
117
e1ef4d23
AT		 118static const enum omap_display_type omap2_dss_supported_displays[] = {
119 /* OMAP_DSS_CHANNEL_LCD */
f8df01f1 120 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
e1ef4d23
AT		 121
122 /* OMAP_DSS_CHANNEL_DIGIT */
123 OMAP_DISPLAY_TYPE_VENC,
124};
125
4e777dd7 126static const enum omap_display_type omap3430_dss_supported_displays[] = {
e1ef4d23
AT		 127 /* OMAP_DSS_CHANNEL_LCD */
128 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
129 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
130
131 /* OMAP_DSS_CHANNEL_DIGIT */
132 OMAP_DISPLAY_TYPE_VENC,
133};
134
4e777dd7
TV		 135static const enum omap_display_type omap3630_dss_supported_displays[] = {
136 /* OMAP_DSS_CHANNEL_LCD */
137 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
138 OMAP_DISPLAY_TYPE_DSI,
139
140 /* OMAP_DSS_CHANNEL_DIGIT */
141 OMAP_DISPLAY_TYPE_VENC,
142};
143
d6279d4a
SP		 144static const enum omap_display_type am43xx_dss_supported_displays[] = {
145 /* OMAP_DSS_CHANNEL_LCD */
146 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
147};
148
d50cd037
AT		 149static const enum omap_display_type omap4_dss_supported_displays[] = {
150 /* OMAP_DSS_CHANNEL_LCD */
151 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
152
153 /* OMAP_DSS_CHANNEL_DIGIT */
b119601d 154 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
d50cd037
AT		 155
156 /* OMAP_DSS_CHANNEL_LCD2 */
157 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
158 OMAP_DISPLAY_TYPE_DSI,
159};
160
23362832
AT		 161static const enum omap_display_type omap5_dss_supported_displays[] = {
162 /* OMAP_DSS_CHANNEL_LCD */
163 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
164 OMAP_DISPLAY_TYPE_DSI,
165
166 /* OMAP_DSS_CHANNEL_DIGIT */
167 OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
168
169 /* OMAP_DSS_CHANNEL_LCD2 */
170 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
171 OMAP_DISPLAY_TYPE_DSI,
172};
173
97f01b3a
AT		 174static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
175 /* OMAP_DSS_CHANNEL_LCD */
176 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
177
178 /* OMAP_DSS_CHANNEL_DIGIT */
179 OMAP_DSS_OUTPUT_VENC,
180};
181
182static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
183 /* OMAP_DSS_CHANNEL_LCD */
184 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
185 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
186
187 /* OMAP_DSS_CHANNEL_DIGIT */
188 OMAP_DSS_OUTPUT_VENC,
189};
190
191static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
192 /* OMAP_DSS_CHANNEL_LCD */
193 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
194 OMAP_DSS_OUTPUT_DSI1,
195
196 /* OMAP_DSS_CHANNEL_DIGIT */
197 OMAP_DSS_OUTPUT_VENC,
198};
199
d6279d4a
SP		 200static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
201 /* OMAP_DSS_CHANNEL_LCD */
202 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
203};
204
97f01b3a
AT		 205static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
206 /* OMAP_DSS_CHANNEL_LCD */
ff588d83 207 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
97f01b3a
AT		 208
209 /* OMAP_DSS_CHANNEL_DIGIT */
ff588d83 210 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
97f01b3a
AT		 211
212 /* OMAP_DSS_CHANNEL_LCD2 */
213 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
214 OMAP_DSS_OUTPUT_DSI2,
215};
216
217static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
218 /* OMAP_DSS_CHANNEL_LCD */
219 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
220 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
221
222 /* OMAP_DSS_CHANNEL_DIGIT */
fa0c52ab 223 OMAP_DSS_OUTPUT_HDMI,
97f01b3a
AT		 224
225 /* OMAP_DSS_CHANNEL_LCD2 */
226 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
227 OMAP_DSS_OUTPUT_DSI1,
228
229 /* OMAP_DSS_CHANNEL_LCD3 */
230 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
231 OMAP_DSS_OUTPUT_DSI2,
232};
233
e1ef4d23
AT		 234static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
235 /* OMAP_DSS_GFX */
236 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
237 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
238 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
239 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
240
241 /* OMAP_DSS_VIDEO1 */
242 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
243 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
244 OMAP_DSS_COLOR_UYVY,
245
246 /* OMAP_DSS_VIDEO2 */
247 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
248 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
249 OMAP_DSS_COLOR_UYVY,
250};
251
252static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
253 /* OMAP_DSS_GFX */
254 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
255 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
256 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
257 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
258 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
259 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
260
261 /* OMAP_DSS_VIDEO1 */
262 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
263 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
264 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
265
266 /* OMAP_DSS_VIDEO2 */
267 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
268 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
269 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
270 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
271 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
272};
273
f20e4220
AJ		 274static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
275 /* OMAP_DSS_GFX */
276 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
277 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
278 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
279 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
280 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
281 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
08f3267e
LM		 282 OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
283 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
f20e4220
AJ		 284
285 /* OMAP_DSS_VIDEO1 */
286 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
287 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
288 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
289 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
290 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
291 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
292 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
293 OMAP_DSS_COLOR_RGBX32,
294
295 /* OMAP_DSS_VIDEO2 */
296 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
297 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
298 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
299 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
300 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
301 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
302 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
303 OMAP_DSS_COLOR_RGBX32,
b8c095b4
AT		 304
305 /* OMAP_DSS_VIDEO3 */
306 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
307 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
308 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
309 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
310 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
311 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
312 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
313 OMAP_DSS_COLOR_RGBX32,
7a155be3
AT		 314
315 /* OMAP_DSS_WB */
316 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
317 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
318 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
319 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
320 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
321 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
322 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
323 OMAP_DSS_COLOR_RGBX32,
f20e4220
AJ		 324};
325
67019db8
TV		 326static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
327 /* OMAP_DSS_GFX */
d79db853 328 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 329
330 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 331 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
332 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 333
334 /* OMAP_DSS_VIDEO2 */
d79db853
AT		 335 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
336 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 337};
338
339static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
340 /* OMAP_DSS_GFX */
d79db853
AT		 341 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
342 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 343
344 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 345 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
346 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 347
348 /* OMAP_DSS_VIDEO2 */
d79db853
AT		 349 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
350 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 351};
352
353static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
354 /* OMAP_DSS_GFX */
d79db853
AT		 355 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
356 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 357
358 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 359 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
360 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 361
362 /* OMAP_DSS_VIDEO2 */
f6dc8150 363 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 364 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
365 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 366};
367
368static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
369 /* OMAP_DSS_GFX */
11354dd5 370 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
d79db853
AT		 371 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
372 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 373
374 /* OMAP_DSS_VIDEO1 */
f6dc8150 375 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 376 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
377 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 378
379 /* OMAP_DSS_VIDEO2 */
f6dc8150 380 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 381 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
382 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
b8c095b4
AT		 383
384 /* OMAP_DSS_VIDEO3 */
385 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 386 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
387 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 388};
389
31ef8237 390static const struct dss_param_range omap2_dss_param_range[] = {
3729a70b 391 [FEAT_PARAM_DSS_FCK] = { 0, 133000000 },
9eaaf207 392 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
0373cac6 393 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
7282f1b7
CM		 394 /*
395 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
396 * scaler cannot scale a image with width more than 768.
397 */
398 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
31ef8237
TA		 399};
400
401static const struct dss_param_range omap3_dss_param_range[] = {
49641116 402 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
9eaaf207 403 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
49641116 404 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
bc63f304 405 [FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
0373cac6 406 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
7282f1b7 407 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
31ef8237
TA		 408};
409
d6279d4a
SP		 410static const struct dss_param_range am43xx_dss_param_range[] = {
411 [FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
1511c75b 412 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
d6279d4a
SP		 413 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
414 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
415};
416
31ef8237 417static const struct dss_param_range omap4_dss_param_range[] = {
49641116 418 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
9eaaf207 419 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
49641116 420 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
bc63f304 421 [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
0373cac6 422 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
7282f1b7 423 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
31ef8237
TA		 424};
425
23362832 426static const struct dss_param_range omap5_dss_param_range[] = {
3729a70b 427 [FEAT_PARAM_DSS_FCK] = { 0, 209250000 },
23362832 428 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
23362832 429 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
3729a70b 430 [FEAT_PARAM_DSI_FCK] = { 0, 209250000 },
23362832
AT		 431 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
432 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
23362832
AT		 433};
434
c124f23d
AT		 435static const enum dss_feat_id omap2_dss_feat_list[] = {
436 FEAT_LCDENABLEPOL,
437 FEAT_LCDENABLESIGNAL,
438 FEAT_PCKFREEENABLE,
439 FEAT_FUNCGATED,
440 FEAT_ROWREPEATENABLE,
441 FEAT_RESIZECONF,
442};
443
444static const enum dss_feat_id omap3430_dss_feat_list[] = {
445 FEAT_LCDENABLEPOL,
446 FEAT_LCDENABLESIGNAL,
447 FEAT_PCKFREEENABLE,
448 FEAT_FUNCGATED,
449 FEAT_LINEBUFFERSPLIT,
450 FEAT_ROWREPEATENABLE,
451 FEAT_RESIZECONF,
c124f23d
AT		 452 FEAT_DSI_REVERSE_TXCLKESC,
453 FEAT_VENC_REQUIRES_TV_DAC_CLK,
454 FEAT_CPR,
455 FEAT_PRELOAD,
456 FEAT_FIR_COEF_V,
457 FEAT_ALPHA_FIXED_ZORDER,
458 FEAT_FIFO_MERGE,
459 FEAT_OMAP3_DSI_FIFO_BUG,
195e672a 460 FEAT_DPI_USES_VDDS_DSI,
c124f23d
AT		 461};
462
524d9f48
RA		 463static const enum dss_feat_id am35xx_dss_feat_list[] = {
464 FEAT_LCDENABLEPOL,
465 FEAT_LCDENABLESIGNAL,
466 FEAT_PCKFREEENABLE,
467 FEAT_FUNCGATED,
468 FEAT_LINEBUFFERSPLIT,
469 FEAT_ROWREPEATENABLE,
470 FEAT_RESIZECONF,
524d9f48
RA		 471 FEAT_DSI_REVERSE_TXCLKESC,
472 FEAT_VENC_REQUIRES_TV_DAC_CLK,
473 FEAT_CPR,
474 FEAT_PRELOAD,
475 FEAT_FIR_COEF_V,
476 FEAT_ALPHA_FIXED_ZORDER,
477 FEAT_FIFO_MERGE,
478 FEAT_OMAP3_DSI_FIFO_BUG,
479};
480
d6279d4a
SP		 481static const enum dss_feat_id am43xx_dss_feat_list[] = {
482 FEAT_LCDENABLEPOL,
483 FEAT_LCDENABLESIGNAL,
484 FEAT_PCKFREEENABLE,
485 FEAT_FUNCGATED,
486 FEAT_LINEBUFFERSPLIT,
487 FEAT_ROWREPEATENABLE,
488 FEAT_RESIZECONF,
489 FEAT_CPR,
490 FEAT_PRELOAD,
491 FEAT_FIR_COEF_V,
492 FEAT_ALPHA_FIXED_ZORDER,
493 FEAT_FIFO_MERGE,
494};
495
c124f23d
AT		 496static const enum dss_feat_id omap3630_dss_feat_list[] = {
497 FEAT_LCDENABLEPOL,
498 FEAT_LCDENABLESIGNAL,
499 FEAT_PCKFREEENABLE,
500 FEAT_FUNCGATED,
501 FEAT_LINEBUFFERSPLIT,
502 FEAT_ROWREPEATENABLE,
503 FEAT_RESIZECONF,
504 FEAT_DSI_PLL_PWR_BUG,
c124f23d
AT		 505 FEAT_CPR,
506 FEAT_PRELOAD,
507 FEAT_FIR_COEF_V,
508 FEAT_ALPHA_FIXED_ZORDER,
509 FEAT_FIFO_MERGE,
510 FEAT_OMAP3_DSI_FIFO_BUG,
eb91e79b 511 FEAT_DPI_USES_VDDS_DSI,
c124f23d
AT		 512};
513
514static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
515 FEAT_MGR_LCD2,
516 FEAT_CORE_CLK_DIV,
517 FEAT_LCD_CLK_SRC,
518 FEAT_DSI_DCS_CMD_CONFIG_VC,
519 FEAT_DSI_VC_OCP_WIDTH,
520 FEAT_DSI_GNQ,
521 FEAT_HANDLE_UV_SEPARATE,
522 FEAT_ATTR2,
523 FEAT_CPR,
524 FEAT_PRELOAD,
525 FEAT_FIR_COEF_V,
526 FEAT_ALPHA_FREE_ZORDER,
527 FEAT_FIFO_MERGE,
65e006ff 528 FEAT_BURST_2D,
c124f23d
AT		 529};
530
70988194
RN		 531static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
532 FEAT_MGR_LCD2,
533 FEAT_CORE_CLK_DIV,
534 FEAT_LCD_CLK_SRC,
535 FEAT_DSI_DCS_CMD_CONFIG_VC,
536 FEAT_DSI_VC_OCP_WIDTH,
537 FEAT_DSI_GNQ,
538 FEAT_HDMI_CTS_SWMODE,
539 FEAT_HANDLE_UV_SEPARATE,
540 FEAT_ATTR2,
541 FEAT_CPR,
542 FEAT_PRELOAD,
543 FEAT_FIR_COEF_V,
544 FEAT_ALPHA_FREE_ZORDER,
545 FEAT_FIFO_MERGE,
65e006ff 546 FEAT_BURST_2D,
70988194
RN		 547};
548
c124f23d
AT		 549static const enum dss_feat_id omap4_dss_feat_list[] = {
550 FEAT_MGR_LCD2,
551 FEAT_CORE_CLK_DIV,
552 FEAT_LCD_CLK_SRC,
553 FEAT_DSI_DCS_CMD_CONFIG_VC,
554 FEAT_DSI_VC_OCP_WIDTH,
555 FEAT_DSI_GNQ,
556 FEAT_HDMI_CTS_SWMODE,
70988194 557 FEAT_HDMI_AUDIO_USE_MCLK,
c124f23d
AT		 558 FEAT_HANDLE_UV_SEPARATE,
559 FEAT_ATTR2,
560 FEAT_CPR,
561 FEAT_PRELOAD,
562 FEAT_FIR_COEF_V,
563 FEAT_ALPHA_FREE_ZORDER,
564 FEAT_FIFO_MERGE,
65e006ff 565 FEAT_BURST_2D,
c124f23d
AT		 566};
567
23362832
AT		 568static const enum dss_feat_id omap5_dss_feat_list[] = {
569 FEAT_MGR_LCD2,
5b3075ce 570 FEAT_MGR_LCD3,
23362832
AT		 571 FEAT_CORE_CLK_DIV,
572 FEAT_LCD_CLK_SRC,
573 FEAT_DSI_DCS_CMD_CONFIG_VC,
574 FEAT_DSI_VC_OCP_WIDTH,
575 FEAT_DSI_GNQ,
576 FEAT_HDMI_CTS_SWMODE,
577 FEAT_HDMI_AUDIO_USE_MCLK,
578 FEAT_HANDLE_UV_SEPARATE,
579 FEAT_ATTR2,
580 FEAT_CPR,
581 FEAT_PRELOAD,
582 FEAT_FIR_COEF_V,
583 FEAT_ALPHA_FREE_ZORDER,
584 FEAT_FIFO_MERGE,
585 FEAT_BURST_2D,
77ccbfbb 586 FEAT_DSI_PHY_DCC,
29fceeeb 587 FEAT_MFLAG,
23362832
AT		 588};
589
e1ef4d23 590/* OMAP2 DSS Features */
ea290333 591static const struct omap_dss_features omap2_dss_features = {
e1ef4d23
AT		 592 .reg_fields = omap2_dss_reg_fields,
593 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
594
c124f23d
AT		 595 .features = omap2_dss_feat_list,
596 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
d50cd037 597
e1ef4d23
AT		 598 .num_mgrs = 2,
599 .num_ovls = 3,
600 .supported_displays = omap2_dss_supported_displays,
97f01b3a 601 .supported_outputs = omap2_dss_supported_outputs,
e1ef4d23 602 .supported_color_modes = omap2_dss_supported_color_modes,
67019db8 603 .overlay_caps = omap2_dss_overlay_caps,
31ef8237 604 .dss_params = omap2_dss_param_range,
65e006ff 605 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 606 .buffer_size_unit = 1,
607 .burst_size_unit = 8,
e1ef4d23
AT		 608};
609
610/* OMAP3 DSS Features */
ea290333 611static const struct omap_dss_features omap3430_dss_features = {
e1ef4d23
AT		 612 .reg_fields = omap3_dss_reg_fields,
613 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
614
c124f23d
AT		 615 .features = omap3430_dss_feat_list,
616 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
e1ef4d23
AT		 617
618 .num_mgrs = 2,
619 .num_ovls = 3,
4e777dd7 620 .supported_displays = omap3430_dss_supported_displays,
97f01b3a 621 .supported_outputs = omap3430_dss_supported_outputs,
e1ef4d23 622 .supported_color_modes = omap3_dss_supported_color_modes,
67019db8 623 .overlay_caps = omap3430_dss_overlay_caps,
31ef8237 624 .dss_params = omap3_dss_param_range,
65e006ff 625 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 626 .buffer_size_unit = 1,
627 .burst_size_unit = 8,
e1ef4d23
AT		 628};
629
524d9f48
RA		 630/*
631 * AM35xx DSS Features. This is basically OMAP3 DSS Features without the
632 * vdds_dsi regulator.
633 */
634static const struct omap_dss_features am35xx_dss_features = {
635 .reg_fields = omap3_dss_reg_fields,
636 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
637
638 .features = am35xx_dss_feat_list,
639 .num_features = ARRAY_SIZE(am35xx_dss_feat_list),
640
641 .num_mgrs = 2,
642 .num_ovls = 3,
643 .supported_displays = omap3430_dss_supported_displays,
97f01b3a 644 .supported_outputs = omap3430_dss_supported_outputs,
524d9f48
RA		 645 .supported_color_modes = omap3_dss_supported_color_modes,
646 .overlay_caps = omap3430_dss_overlay_caps,
524d9f48
RA		 647 .dss_params = omap3_dss_param_range,
648 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
649 .buffer_size_unit = 1,
650 .burst_size_unit = 8,
651};
652
d6279d4a
SP		 653static const struct omap_dss_features am43xx_dss_features = {
654 .reg_fields = am43xx_dss_reg_fields,
655 .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),
656
657 .features = am43xx_dss_feat_list,
658 .num_features = ARRAY_SIZE(am43xx_dss_feat_list),
659
660 .num_mgrs = 1,
661 .num_ovls = 3,
662 .supported_displays = am43xx_dss_supported_displays,
663 .supported_outputs = am43xx_dss_supported_outputs,
664 .supported_color_modes = omap3_dss_supported_color_modes,
665 .overlay_caps = omap3430_dss_overlay_caps,
d6279d4a
SP		 666 .dss_params = am43xx_dss_param_range,
667 .supported_rotation_types = OMAP_DSS_ROT_DMA,
668 .buffer_size_unit = 1,
669 .burst_size_unit = 8,
670};
671
ea290333 672static const struct omap_dss_features omap3630_dss_features = {
8fbde10a
S		 673 .reg_fields = omap3_dss_reg_fields,
674 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
675
c124f23d
AT		 676 .features = omap3630_dss_feat_list,
677 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
8fbde10a
S		 678
679 .num_mgrs = 2,
680 .num_ovls = 3,
4e777dd7 681 .supported_displays = omap3630_dss_supported_displays,
97f01b3a 682 .supported_outputs = omap3630_dss_supported_outputs,
8fbde10a 683 .supported_color_modes = omap3_dss_supported_color_modes,
67019db8 684 .overlay_caps = omap3630_dss_overlay_caps,
31ef8237 685 .dss_params = omap3_dss_param_range,
65e006ff 686 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 687 .buffer_size_unit = 1,
688 .burst_size_unit = 8,
8fbde10a
S		 689};
690
d50cd037 691/* OMAP4 DSS Features */
6ff7084e
RN		 692/* For OMAP4430 ES 1.0 revision */
693static const struct omap_dss_features omap4430_es1_0_dss_features = {
694 .reg_fields = omap4_dss_reg_fields,
695 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
696
c124f23d
AT		 697 .features = omap4430_es1_0_dss_feat_list,
698 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
6ff7084e
RN		 699
700 .num_mgrs = 3,
b8c095b4 701 .num_ovls = 4,
6ff7084e 702 .supported_displays = omap4_dss_supported_displays,
97f01b3a 703 .supported_outputs = omap4_dss_supported_outputs,
f20e4220 704 .supported_color_modes = omap4_dss_supported_color_modes,
67019db8 705 .overlay_caps = omap4_dss_overlay_caps,
6ff7084e 706 .dss_params = omap4_dss_param_range,
65e006ff 707 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
5ed8cf5b
TV		 708 .buffer_size_unit = 16,
709 .burst_size_unit = 16,
6ff7084e
RN		 710};
711
70988194
RN		 712/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
713static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
714 .reg_fields = omap4_dss_reg_fields,
715 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
716
717 .features = omap4430_es2_0_1_2_dss_feat_list,
718 .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
719
720 .num_mgrs = 3,
721 .num_ovls = 4,
722 .supported_displays = omap4_dss_supported_displays,
97f01b3a 723 .supported_outputs = omap4_dss_supported_outputs,
70988194
RN		 724 .supported_color_modes = omap4_dss_supported_color_modes,
725 .overlay_caps = omap4_dss_overlay_caps,
70988194 726 .dss_params = omap4_dss_param_range,
65e006ff 727 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
70988194
RN		 728 .buffer_size_unit = 16,
729 .burst_size_unit = 16,
730};
731
6ff7084e 732/* For all the other OMAP4 versions */
ea290333 733static const struct omap_dss_features omap4_dss_features = {
87a7484b
AT		 734 .reg_fields = omap4_dss_reg_fields,
735 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
d50cd037 736
c124f23d
AT		 737 .features = omap4_dss_feat_list,
738 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
d50cd037
AT		 739
740 .num_mgrs = 3,
b8c095b4 741 .num_ovls = 4,
d50cd037 742 .supported_displays = omap4_dss_supported_displays,
97f01b3a 743 .supported_outputs = omap4_dss_supported_outputs,
f20e4220 744 .supported_color_modes = omap4_dss_supported_color_modes,
67019db8 745 .overlay_caps = omap4_dss_overlay_caps,
31ef8237 746 .dss_params = omap4_dss_param_range,
65e006ff 747 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
5ed8cf5b
TV		 748 .buffer_size_unit = 16,
749 .burst_size_unit = 16,
d50cd037
AT		 750};
751
23362832
AT		 752/* OMAP5 DSS Features */
753static const struct omap_dss_features omap5_dss_features = {
754 .reg_fields = omap5_dss_reg_fields,
755 .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
756
757 .features = omap5_dss_feat_list,
758 .num_features = ARRAY_SIZE(omap5_dss_feat_list),
759
5b3075ce 760 .num_mgrs = 4,
23362832
AT		 761 .num_ovls = 4,
762 .supported_displays = omap5_dss_supported_displays,
97f01b3a 763 .supported_outputs = omap5_dss_supported_outputs,
23362832
AT		 764 .supported_color_modes = omap4_dss_supported_color_modes,
765 .overlay_caps = omap4_dss_overlay_caps,
23362832
AT		 766 .dss_params = omap5_dss_param_range,
767 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
768 .buffer_size_unit = 16,
769 .burst_size_unit = 16,
770};
771
e1ef4d23
AT		 772/* Functions returning values related to a DSS feature */
773int dss_feat_get_num_mgrs(void)
774{
775 return omap_current_dss_features->num_mgrs;
776}
eda34273 777EXPORT_SYMBOL(dss_feat_get_num_mgrs);
e1ef4d23
AT		 778
779int dss_feat_get_num_ovls(void)
780{
781 return omap_current_dss_features->num_ovls;
782}
eda34273 783EXPORT_SYMBOL(dss_feat_get_num_ovls);
e1ef4d23 784
31ef8237
TA		 785unsigned long dss_feat_get_param_min(enum dss_range_param param)
786{
787 return omap_current_dss_features->dss_params[param].min;
788}
789
790unsigned long dss_feat_get_param_max(enum dss_range_param param)
819d807c 791{
31ef8237 792 return omap_current_dss_features->dss_params[param].max;
819d807c
AT		 793}
794
e1ef4d23
AT		 795enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
796{
797 return omap_current_dss_features->supported_displays[channel];
798}
799
97f01b3a
AT		 800enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
801{
802 return omap_current_dss_features->supported_outputs[channel];
803}
804
e1ef4d23
AT		 805enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
806{
807 return omap_current_dss_features->supported_color_modes[plane];
808}
eda34273 809EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
e1ef4d23 810
67019db8
TV		 811enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
812{
813 return omap_current_dss_features->overlay_caps[plane];
814}
815
8dad2ab6
AT		 816bool dss_feat_color_mode_supported(enum omap_plane plane,
817 enum omap_color_mode color_mode)
818{
819 return omap_current_dss_features->supported_color_modes[plane] &
820 color_mode;
821}
822
5ed8cf5b
TV		 823u32 dss_feat_get_buffer_size_unit(void)
824{
825 return omap_current_dss_features->buffer_size_unit;
826}
827
828u32 dss_feat_get_burst_size_unit(void)
829{
830 return omap_current_dss_features->burst_size_unit;
831}
832
e1ef4d23
AT		 833/* DSS has_feature check */
834bool dss_has_feature(enum dss_feat_id id)
835{
c124f23d
AT		 836 int i;
837 const enum dss_feat_id *features = omap_current_dss_features->features;
838 const int num_features = omap_current_dss_features->num_features;
839
840 for (i = 0; i < num_features; i++) {
841 if (features[i] == id)
842 return true;
843 }
844
845 return false;
e1ef4d23
AT		 846}
847
848void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
849{
850 if (id >= omap_current_dss_features->num_reg_fields)
851 BUG();
852
853 *start = omap_current_dss_features->reg_fields[id].start;
854 *end = omap_current_dss_features->reg_fields[id].end;
855}
856
65e006ff
CM		 857bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
858{
859 return omap_current_dss_features->supported_rotation_types & rot_type;
860}
861
649514c6 862void dss_features_init(enum omapdss_version version)
e1ef4d23 863{
649514c6
TV		 864 switch (version) {
865 case OMAPDSS_VER_OMAP24xx:
e1ef4d23 866 omap_current_dss_features = &omap2_dss_features;
649514c6
TV		 867 break;
868
869 case OMAPDSS_VER_OMAP34xx_ES1:
870 case OMAPDSS_VER_OMAP34xx_ES3:
871 omap_current_dss_features = &omap3430_dss_features;
872 break;
873
874 case OMAPDSS_VER_OMAP3630:
8fbde10a 875 omap_current_dss_features = &omap3630_dss_features;
649514c6
TV		 876 break;
877
878 case OMAPDSS_VER_OMAP4430_ES1:
6ff7084e 879 omap_current_dss_features = &omap4430_es1_0_dss_features;
649514c6
TV		 880 break;
881
882 case OMAPDSS_VER_OMAP4430_ES2:
70988194 883 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
649514c6
TV		 884 break;
885
886 case OMAPDSS_VER_OMAP4:
d50cd037 887 omap_current_dss_features = &omap4_dss_features;
649514c6
TV		 888 break;
889
890 case OMAPDSS_VER_OMAP5:
6d817880 891 case OMAPDSS_VER_DRA7xx:
23362832 892 omap_current_dss_features = &omap5_dss_features;
649514c6
TV		 893 break;
894
895 case OMAPDSS_VER_AM35xx:
896 omap_current_dss_features = &am35xx_dss_features;
897 break;
898
d6279d4a
SP		 899 case OMAPDSS_VER_AM43xx:
900 omap_current_dss_features = &am43xx_dss_features;
901 break;
902
649514c6 903 default:
6ff7084e 904 DSSWARN("Unsupported OMAP version");
649514c6
TV		 905 break;
906 }
e1ef4d23 907}
Linux kernel - Deliverables
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