drm/omap: HDMI5: remove uses of omap_overlay_manager
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / hdmi4.c
CommitLineData
c3198a5e 1/*
ef26958a 2 * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
c3198a5e
M
3 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
4 * Authors: Yong Zhi
5 * Mythri pk <mythripk@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "HDMI"
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/mutex.h>
28#include <linux/delay.h>
29#include <linux/string.h>
24e6289c 30#include <linux/platform_device.h>
4fbafaf3
TV
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
cca35017 33#include <linux/gpio.h>
17486943 34#include <linux/regulator/consumer.h>
736e60dd 35#include <linux/component.h>
a0b38cc4 36#include <video/omapdss.h>
4d594dff 37#include <sound/omap-hdmi-audio.h>
c3198a5e 38
ef26958a 39#include "hdmi4_core.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
945514b5 42#include "hdmi.h"
c3198a5e 43
945514b5 44static struct omap_hdmi hdmi;
c3198a5e 45
4fbafaf3
TV
46static int hdmi_runtime_get(void)
47{
48 int r;
49
50 DSSDBG("hdmi_runtime_get\n");
51
52 r = pm_runtime_get_sync(&hdmi.pdev->dev);
53 WARN_ON(r < 0);
a247ce78 54 if (r < 0)
852f0838 55 return r;
a247ce78
AT
56
57 return 0;
4fbafaf3
TV
58}
59
60static void hdmi_runtime_put(void)
61{
62 int r;
63
64 DSSDBG("hdmi_runtime_put\n");
65
0eaf9f52 66 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 67 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV
68}
69
dcf5f729
TV
70static irqreturn_t hdmi_irq_handler(int irq, void *data)
71{
72 struct hdmi_wp_data *wp = data;
73 u32 irqstatus;
74
75 irqstatus = hdmi_wp_get_irqstatus(wp);
76 hdmi_wp_set_irqstatus(wp, irqstatus);
77
78 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
79 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
80 /*
81 * If we get both connect and disconnect interrupts at the same
82 * time, turn off the PHY, clear interrupts, and restart, which
83 * raises connect interrupt if a cable is connected, or nothing
84 * if cable is not connected.
85 */
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
87
88 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
89 HDMI_IRQ_LINK_DISCONNECT);
90
91 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
92 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
94 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
95 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
96 }
97
98 return IRQ_HANDLED;
99}
100
e25001d8
TV
101static int hdmi_init_regulator(void)
102{
818a053c 103 int r;
e25001d8
TV
104 struct regulator *reg;
105
945514b5 106 if (hdmi.vdda_reg != NULL)
e25001d8
TV
107 return 0;
108
931d4bd6 109 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
e25001d8
TV
110
111 if (IS_ERR(reg)) {
40359a9b 112 if (PTR_ERR(reg) != -EPROBE_DEFER)
931d4bd6 113 DSSERR("can't get VDDA regulator\n");
e25001d8
TV
114 return PTR_ERR(reg);
115 }
116
818a053c
TV
117 if (regulator_can_change_voltage(reg)) {
118 r = regulator_set_voltage(reg, 1800000, 1800000);
119 if (r) {
120 devm_regulator_put(reg);
121 DSSWARN("can't set the regulator voltage\n");
122 return r;
123 }
124 }
125
945514b5 126 hdmi.vdda_reg = reg;
e25001d8
TV
127
128 return 0;
129}
130
bb426fc9 131static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 132{
46095b2d 133 int r;
c3198a5e 134
945514b5 135 r = regulator_enable(hdmi.vdda_reg);
17486943 136 if (r)
164ebdd1 137 return r;
17486943 138
4fbafaf3
TV
139 r = hdmi_runtime_get();
140 if (r)
cca35017 141 goto err_runtime_get;
c3198a5e 142
bb426fc9
TV
143 /* Make selection of HDMI in DSS */
144 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
145
0b450c31
TV
146 hdmi.core_enabled = true;
147
bb426fc9
TV
148 return 0;
149
150err_runtime_get:
945514b5 151 regulator_disable(hdmi.vdda_reg);
164ebdd1 152
bb426fc9
TV
153 return r;
154}
155
156static void hdmi_power_off_core(struct omap_dss_device *dssdev)
157{
0b450c31
TV
158 hdmi.core_enabled = false;
159
bb426fc9 160 hdmi_runtime_put();
945514b5 161 regulator_disable(hdmi.vdda_reg);
bb426fc9
TV
162}
163
164static int hdmi_power_on_full(struct omap_dss_device *dssdev)
165{
166 int r;
167 struct omap_video_timings *p;
7ae9a71e 168 struct omap_overlay_manager *mgr = hdmi.output.manager;
dcf5f729 169 struct hdmi_wp_data *wp = &hdmi.wp;
c84c3a5b 170 struct dss_pll_clock_info hdmi_cinfo = { 0 };
67d8ffdd 171 unsigned pc;
bb426fc9
TV
172
173 r = hdmi_power_on_core(dssdev);
174 if (r)
175 return r;
176
dcf5f729
TV
177 /* disable and clear irqs */
178 hdmi_wp_clear_irqenable(wp, 0xffffffff);
179 hdmi_wp_set_irqstatus(wp, 0xffffffff);
180
275cfa1a 181 p = &hdmi.cfg.timings;
c3198a5e 182
7849398f 183 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 184
67d8ffdd
TV
185 pc = p->pixelclock;
186 if (p->double_pixel)
187 pc *= 2;
188
189 hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
c3198a5e 190
c84c3a5b 191 r = dss_pll_enable(&hdmi.pll.pll);
c3198a5e 192 if (r) {
c2fbd061 193 DSSERR("Failed to enable PLL\n");
cca35017 194 goto err_pll_enable;
c3198a5e
M
195 }
196
c84c3a5b 197 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
c2fbd061
TV
198 if (r) {
199 DSSERR("Failed to configure PLL\n");
200 goto err_pll_cfg;
201 }
202
c84c3a5b
TV
203 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
204 hdmi_cinfo.clkout[0]);
c3198a5e 205 if (r) {
dcf5f729
TV
206 DSSDBG("Failed to configure PHY\n");
207 goto err_phy_cfg;
c3198a5e
M
208 }
209
dcf5f729
TV
210 r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
211 if (r)
212 goto err_phy_pwr;
213
275cfa1a 214 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
c3198a5e 215
c3198a5e
M
216 /* bypass TV gamma table */
217 dispc_enable_gamma_table(0);
218
219 /* tv size */
5c6ff3cd 220 dss_mgr_set_timings(mgr->id, p);
c3198a5e 221
85a8c622 222 r = dss_mgr_enable(mgr->id);
33ca237f
TV
223 if (r)
224 goto err_mgr_enable;
3870c909 225
4e4b53ce
TV
226 r = hdmi_wp_video_start(&hdmi.wp);
227 if (r)
228 goto err_vid_enable;
229
dcf5f729
TV
230 hdmi_wp_set_irqenable(wp,
231 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
232
c3198a5e 233 return 0;
33ca237f 234
c0456be3 235err_vid_enable:
705fd454 236 dss_mgr_disable(mgr->id);
4e4b53ce 237err_mgr_enable:
dcf5f729
TV
238 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
239err_phy_pwr:
9bba13f0 240err_phy_cfg:
c2fbd061 241err_pll_cfg:
c84c3a5b 242 dss_pll_disable(&hdmi.pll.pll);
cca35017 243err_pll_enable:
bb426fc9 244 hdmi_power_off_core(dssdev);
c3198a5e
M
245 return -EIO;
246}
247
bb426fc9 248static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 249{
7ae9a71e 250 struct omap_overlay_manager *mgr = hdmi.output.manager;
cea87b92 251
dcf5f729
TV
252 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
253
275cfa1a 254 hdmi_wp_video_stop(&hdmi.wp);
dcf5f729 255
705fd454 256 dss_mgr_disable(mgr->id);
4e4b53ce 257
dcf5f729
TV
258 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
259
c84c3a5b 260 dss_pll_disable(&hdmi.pll.pll);
17486943 261
bb426fc9 262 hdmi_power_off_core(dssdev);
c3198a5e
M
263}
264
164ebdd1 265static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
c3198a5e
M
266 struct omap_video_timings *timings)
267{
1e676248 268 struct omap_dss_device *out = &hdmi.output;
c3198a5e 269
1e676248 270 if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
c3198a5e 271 return -EINVAL;
c3198a5e
M
272
273 return 0;
c3198a5e
M
274}
275
164ebdd1 276static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
7849398f 277 struct omap_video_timings *timings)
c3198a5e 278{
ed1aa900
AT
279 mutex_lock(&hdmi.lock);
280
ab0aee95 281 hdmi.cfg.timings = *timings;
5391e87d 282
ab0aee95 283 dispc_set_tv_pclk(timings->pixelclock);
1e676248 284
ed1aa900 285 mutex_unlock(&hdmi.lock);
c3198a5e
M
286}
287
164ebdd1 288static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
0b450c31
TV
289 struct omap_video_timings *timings)
290{
ab0aee95 291 *timings = hdmi.cfg.timings;
0b450c31
TV
292}
293
e40402cf 294static void hdmi_dump_regs(struct seq_file *s)
162874d5
M
295{
296 mutex_lock(&hdmi.lock);
297
f8fb7d7b
WY
298 if (hdmi_runtime_get()) {
299 mutex_unlock(&hdmi.lock);
162874d5 300 return;
f8fb7d7b 301 }
162874d5 302
275cfa1a
AT
303 hdmi_wp_dump(&hdmi.wp, s);
304 hdmi_pll_dump(&hdmi.pll, s);
305 hdmi_phy_dump(&hdmi.phy, s);
306 hdmi4_core_dump(&hdmi.core, s);
162874d5
M
307
308 hdmi_runtime_put();
309 mutex_unlock(&hdmi.lock);
310}
311
164ebdd1 312static int read_edid(u8 *buf, int len)
47024565
TV
313{
314 int r;
315
316 mutex_lock(&hdmi.lock);
317
318 r = hdmi_runtime_get();
319 BUG_ON(r);
320
275cfa1a 321 r = hdmi4_read_edid(&hdmi.core, buf, len);
47024565
TV
322
323 hdmi_runtime_put();
324 mutex_unlock(&hdmi.lock);
325
326 return r;
327}
328
8a9d4626
JS
329static void hdmi_start_audio_stream(struct omap_hdmi *hd)
330{
331 hdmi_wp_audio_enable(&hd->wp, true);
332 hdmi4_audio_start(&hd->core, &hd->wp);
333}
334
335static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
336{
337 hdmi4_audio_stop(&hd->core, &hd->wp);
338 hdmi_wp_audio_enable(&hd->wp, false);
339}
340
164ebdd1 341static int hdmi_display_enable(struct omap_dss_device *dssdev)
c3198a5e 342{
1f68d9c4 343 struct omap_dss_device *out = &hdmi.output;
8a9d4626 344 unsigned long flags;
c3198a5e
M
345 int r = 0;
346
347 DSSDBG("ENTER hdmi_display_enable\n");
348
349 mutex_lock(&hdmi.lock);
350
f1504ad0 351 if (!out->dispc_channel_connected) {
cea87b92 352 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV
353 r = -ENODEV;
354 goto err0;
355 }
356
bb426fc9 357 r = hdmi_power_on_full(dssdev);
c3198a5e
M
358 if (r) {
359 DSSERR("failed to power on device\n");
d3923933 360 goto err0;
c3198a5e
M
361 }
362
8a9d4626
JS
363 if (hdmi.audio_configured) {
364 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
365 hdmi.cfg.timings.pixelclock);
366 if (r) {
367 DSSERR("Error restoring audio configuration: %d", r);
368 hdmi.audio_abort_cb(&hdmi.pdev->dev);
369 hdmi.audio_configured = false;
370 }
371 }
372
373 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
374 if (hdmi.audio_configured && hdmi.audio_playing)
375 hdmi_start_audio_stream(&hdmi);
4d594dff 376 hdmi.display_enabled = true;
8a9d4626 377 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
4d594dff 378
c3198a5e
M
379 mutex_unlock(&hdmi.lock);
380 return 0;
381
c3198a5e
M
382err0:
383 mutex_unlock(&hdmi.lock);
384 return r;
385}
386
164ebdd1 387static void hdmi_display_disable(struct omap_dss_device *dssdev)
c3198a5e 388{
8a9d4626
JS
389 unsigned long flags;
390
c3198a5e
M
391 DSSDBG("Enter hdmi_display_disable\n");
392
393 mutex_lock(&hdmi.lock);
394
8a9d4626
JS
395 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
396 hdmi_stop_audio_stream(&hdmi);
397 hdmi.display_enabled = false;
398 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
4d594dff 399
bb426fc9 400 hdmi_power_off_full(dssdev);
c3198a5e 401
c3198a5e
M
402 mutex_unlock(&hdmi.lock);
403}
404
164ebdd1 405static int hdmi_core_enable(struct omap_dss_device *dssdev)
4489823c
TV
406{
407 int r = 0;
408
409 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
410
411 mutex_lock(&hdmi.lock);
412
4489823c
TV
413 r = hdmi_power_on_core(dssdev);
414 if (r) {
415 DSSERR("failed to power on device\n");
416 goto err0;
417 }
418
419 mutex_unlock(&hdmi.lock);
420 return 0;
421
422err0:
423 mutex_unlock(&hdmi.lock);
424 return r;
425}
426
164ebdd1 427static void hdmi_core_disable(struct omap_dss_device *dssdev)
4489823c
TV
428{
429 DSSDBG("Enter omapdss_hdmi_core_disable\n");
430
431 mutex_lock(&hdmi.lock);
432
433 hdmi_power_off_core(dssdev);
434
435 mutex_unlock(&hdmi.lock);
436}
437
0b450c31
TV
438static int hdmi_connect(struct omap_dss_device *dssdev,
439 struct omap_dss_device *dst)
440{
441 struct omap_overlay_manager *mgr;
442 int r;
443
0b450c31
TV
444 r = hdmi_init_regulator();
445 if (r)
446 return r;
447
448 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
449 if (!mgr)
450 return -ENODEV;
451
1b07b066 452 r = dss_mgr_connect(mgr->id, dssdev);
0b450c31
TV
453 if (r)
454 return r;
455
456 r = omapdss_output_set_device(dssdev, dst);
457 if (r) {
458 DSSERR("failed to connect output to new device: %s\n",
459 dst->name);
bdac3bb9 460 dss_mgr_disconnect(mgr->id, dssdev);
0b450c31
TV
461 return r;
462 }
463
464 return 0;
465}
466
467static void hdmi_disconnect(struct omap_dss_device *dssdev,
468 struct omap_dss_device *dst)
469{
9560dc10 470 WARN_ON(dst != dssdev->dst);
0b450c31 471
9560dc10 472 if (dst != dssdev->dst)
0b450c31
TV
473 return;
474
475 omapdss_output_unset_device(dssdev);
476
a0e53bfe 477 dss_mgr_disconnect(dssdev->manager->id, dssdev);
0b450c31
TV
478}
479
480static int hdmi_read_edid(struct omap_dss_device *dssdev,
481 u8 *edid, int len)
482{
483 bool need_enable;
484 int r;
485
486 need_enable = hdmi.core_enabled == false;
487
488 if (need_enable) {
164ebdd1 489 r = hdmi_core_enable(dssdev);
0b450c31
TV
490 if (r)
491 return r;
492 }
493
164ebdd1 494 r = read_edid(edid, len);
0b450c31
TV
495
496 if (need_enable)
164ebdd1 497 hdmi_core_disable(dssdev);
0b450c31
TV
498
499 return r;
500}
501
ab0aee95
TV
502static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
503 const struct hdmi_avi_infoframe *avi)
504{
505 hdmi.cfg.infoframe = *avi;
506 return 0;
507}
508
509static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
510 bool hdmi_mode)
511{
512 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
513 return 0;
514}
515
0b450c31
TV
516static const struct omapdss_hdmi_ops hdmi_ops = {
517 .connect = hdmi_connect,
518 .disconnect = hdmi_disconnect,
519
164ebdd1
TV
520 .enable = hdmi_display_enable,
521 .disable = hdmi_display_disable,
0b450c31 522
164ebdd1
TV
523 .check_timings = hdmi_display_check_timing,
524 .set_timings = hdmi_display_set_timing,
525 .get_timings = hdmi_display_get_timings,
0b450c31
TV
526
527 .read_edid = hdmi_read_edid,
ab0aee95
TV
528 .set_infoframe = hdmi_set_infoframe,
529 .set_hdmi_mode = hdmi_set_hdmi_mode,
0b450c31
TV
530};
531
17ae4e8c 532static void hdmi_init_output(struct platform_device *pdev)
81b87f51 533{
1f68d9c4 534 struct omap_dss_device *out = &hdmi.output;
81b87f51 535
1f68d9c4 536 out->dev = &pdev->dev;
81b87f51 537 out->id = OMAP_DSS_OUTPUT_HDMI;
1f68d9c4 538 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
7286a08f 539 out->name = "hdmi.0";
2eea5ae6 540 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
0b450c31 541 out->ops.hdmi = &hdmi_ops;
b7328e14 542 out->owner = THIS_MODULE;
81b87f51 543
5d47dbc8 544 omapdss_register_output(out);
81b87f51
AT
545}
546
39c1b7bf 547static void hdmi_uninit_output(struct platform_device *pdev)
81b87f51 548{
1f68d9c4 549 struct omap_dss_device *out = &hdmi.output;
81b87f51 550
5d47dbc8 551 omapdss_unregister_output(out);
81b87f51
AT
552}
553
2f5dc676
TV
554static int hdmi_probe_of(struct platform_device *pdev)
555{
556 struct device_node *node = pdev->dev.of_node;
557 struct device_node *ep;
558 int r;
559
560 ep = omapdss_of_get_first_endpoint(node);
561 if (!ep)
562 return 0;
563
564 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
565 if (r)
566 goto err;
567
568 of_node_put(ep);
569 return 0;
570
571err:
572 of_node_put(ep);
573 return r;
574}
575
4d594dff
JS
576/* Audio callbacks */
577static int hdmi_audio_startup(struct device *dev,
578 void (*abort_cb)(struct device *dev))
579{
580 struct omap_hdmi *hd = dev_get_drvdata(dev);
581 int ret = 0;
582
583 mutex_lock(&hd->lock);
584
585 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
586 ret = -EPERM;
587 goto out;
588 }
589
590 hd->audio_abort_cb = abort_cb;
591
592out:
593 mutex_unlock(&hd->lock);
594
595 return ret;
596}
597
598static int hdmi_audio_shutdown(struct device *dev)
599{
600 struct omap_hdmi *hd = dev_get_drvdata(dev);
601
602 mutex_lock(&hd->lock);
603 hd->audio_abort_cb = NULL;
8a9d4626
JS
604 hd->audio_configured = false;
605 hd->audio_playing = false;
4d594dff
JS
606 mutex_unlock(&hd->lock);
607
608 return 0;
609}
610
611static int hdmi_audio_start(struct device *dev)
612{
613 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 614 unsigned long flags;
4d594dff
JS
615
616 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
4d594dff 617
8a9d4626
JS
618 spin_lock_irqsave(&hd->audio_playing_lock, flags);
619
620 if (hd->display_enabled)
621 hdmi_start_audio_stream(hd);
622 hd->audio_playing = true;
4d594dff 623
8a9d4626 624 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
625 return 0;
626}
627
628static void hdmi_audio_stop(struct device *dev)
629{
630 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 631 unsigned long flags;
4d594dff
JS
632
633 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
4d594dff 634
8a9d4626
JS
635 spin_lock_irqsave(&hd->audio_playing_lock, flags);
636
637 if (hd->display_enabled)
638 hdmi_stop_audio_stream(hd);
639 hd->audio_playing = false;
640
641 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
642}
643
644static int hdmi_audio_config(struct device *dev,
645 struct omap_dss_audio *dss_audio)
646{
647 struct omap_hdmi *hd = dev_get_drvdata(dev);
648 int ret;
649
650 mutex_lock(&hd->lock);
651
652 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
653 ret = -EPERM;
654 goto out;
655 }
656
657 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
658 hd->cfg.timings.pixelclock);
8a9d4626
JS
659 if (!ret) {
660 hd->audio_configured = true;
661 hd->audio_config = *dss_audio;
662 }
4d594dff
JS
663out:
664 mutex_unlock(&hd->lock);
665
666 return ret;
667}
668
669static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
670 .audio_startup = hdmi_audio_startup,
671 .audio_shutdown = hdmi_audio_shutdown,
672 .audio_start = hdmi_audio_start,
673 .audio_stop = hdmi_audio_stop,
674 .audio_config = hdmi_audio_config,
675};
676
677static int hdmi_audio_register(struct device *dev)
678{
679 struct omap_hdmi_audio_pdata pdata = {
680 .dev = dev,
681 .dss_version = omapdss_get_version(),
682 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
683 .ops = &hdmi_audio_ops,
684 };
685
686 hdmi.audio_pdev = platform_device_register_data(
687 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
688 &pdata, sizeof(pdata));
689
690 if (IS_ERR(hdmi.audio_pdev))
691 return PTR_ERR(hdmi.audio_pdev);
692
693 return 0;
694}
695
c3198a5e 696/* HDMI HW IP initialisation */
736e60dd 697static int hdmi4_bind(struct device *dev, struct device *master, void *data)
c3198a5e 698{
736e60dd 699 struct platform_device *pdev = to_platform_device(dev);
38f3daf6 700 int r;
dcf5f729 701 int irq;
c3198a5e 702
c3198a5e 703 hdmi.pdev = pdev;
945514b5 704 dev_set_drvdata(&pdev->dev, &hdmi);
c3198a5e
M
705
706 mutex_init(&hdmi.lock);
8a9d4626 707 spin_lock_init(&hdmi.audio_playing_lock);
c3198a5e 708
2f5dc676
TV
709 if (pdev->dev.of_node) {
710 r = hdmi_probe_of(pdev);
711 if (r)
712 return r;
713 }
714
275cfa1a 715 r = hdmi_wp_init(pdev, &hdmi.wp);
f382d9eb
AT
716 if (r)
717 return r;
c3198a5e 718
03aafa2c 719 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
c1577c1e
AT
720 if (r)
721 return r;
722
275cfa1a 723 r = hdmi_phy_init(pdev, &hdmi.phy);
5cac5aee 724 if (r)
c84c3a5b 725 goto err;
ddb1d5ca 726
275cfa1a 727 r = hdmi4_core_init(pdev, &hdmi.core);
425f02fd 728 if (r)
c84c3a5b 729 goto err;
4fbafaf3 730
dcf5f729
TV
731 irq = platform_get_irq(pdev, 0);
732 if (irq < 0) {
733 DSSERR("platform_get_irq failed\n");
c84c3a5b
TV
734 r = -ENODEV;
735 goto err;
dcf5f729
TV
736 }
737
738 r = devm_request_threaded_irq(&pdev->dev, irq,
739 NULL, hdmi_irq_handler,
740 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
741 if (r) {
742 DSSERR("HDMI IRQ request failed\n");
c84c3a5b 743 goto err;
dcf5f729
TV
744 }
745
4fbafaf3
TV
746 pm_runtime_enable(&pdev->dev);
747
002d368d
TV
748 hdmi_init_output(pdev);
749
4d594dff
JS
750 r = hdmi_audio_register(&pdev->dev);
751 if (r) {
752 DSSERR("Registering HDMI audio failed\n");
753 hdmi_uninit_output(pdev);
754 pm_runtime_disable(&pdev->dev);
755 return r;
756 }
757
e40402cf
TV
758 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
759
cca35017 760 return 0;
c84c3a5b
TV
761err:
762 hdmi_pll_uninit(&hdmi.pll);
763 return r;
cca35017
TV
764}
765
736e60dd 766static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
c3198a5e 767{
736e60dd
TV
768 struct platform_device *pdev = to_platform_device(dev);
769
4d594dff
JS
770 if (hdmi.audio_pdev)
771 platform_device_unregister(hdmi.audio_pdev);
772
81b87f51
AT
773 hdmi_uninit_output(pdev);
774
c84c3a5b
TV
775 hdmi_pll_uninit(&hdmi.pll);
776
4fbafaf3 777 pm_runtime_disable(&pdev->dev);
736e60dd
TV
778}
779
780static const struct component_ops hdmi4_component_ops = {
781 .bind = hdmi4_bind,
782 .unbind = hdmi4_unbind,
783};
4fbafaf3 784
736e60dd
TV
785static int hdmi4_probe(struct platform_device *pdev)
786{
787 return component_add(&pdev->dev, &hdmi4_component_ops);
788}
789
790static int hdmi4_remove(struct platform_device *pdev)
791{
792 component_del(&pdev->dev, &hdmi4_component_ops);
c3198a5e
M
793 return 0;
794}
795
4fbafaf3
TV
796static int hdmi_runtime_suspend(struct device *dev)
797{
4fbafaf3 798 dispc_runtime_put();
4fbafaf3
TV
799
800 return 0;
801}
802
803static int hdmi_runtime_resume(struct device *dev)
804{
805 int r;
806
4fbafaf3
TV
807 r = dispc_runtime_get();
808 if (r < 0)
852f0838 809 return r;
4fbafaf3 810
4fbafaf3 811 return 0;
4fbafaf3
TV
812}
813
814static const struct dev_pm_ops hdmi_pm_ops = {
815 .runtime_suspend = hdmi_runtime_suspend,
816 .runtime_resume = hdmi_runtime_resume,
817};
818
0465616d
TV
819static const struct of_device_id hdmi_of_match[] = {
820 { .compatible = "ti,omap4-hdmi", },
821 {},
822};
823
c3198a5e 824static struct platform_driver omapdss_hdmihw_driver = {
736e60dd
TV
825 .probe = hdmi4_probe,
826 .remove = hdmi4_remove,
c3198a5e
M
827 .driver = {
828 .name = "omapdss_hdmi",
4fbafaf3 829 .pm = &hdmi_pm_ops,
0465616d 830 .of_match_table = hdmi_of_match,
422ccbd5 831 .suppress_bind_attrs = true,
c3198a5e
M
832 },
833};
834
ef26958a 835int __init hdmi4_init_platform_driver(void)
c3198a5e 836{
17ae4e8c 837 return platform_driver_register(&omapdss_hdmihw_driver);
c3198a5e
M
838}
839
ede92695 840void hdmi4_uninit_platform_driver(void)
c3198a5e 841{
04c742c3 842 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 843}
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