[deliverable/linux.git] / drivers / gpu / drm / omapdrm / omap_crtc.c

/*
 * drivers/gpu/drm/omapdrm/omap_crtc.c
 *
 * Copyright (C) 2011 Texas Instruments
 * Author: Rob Clark <rob@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "omap_drv.h"

#include <drm/drm_mode.h>
#include "drm_crtc.h"
#include "drm_crtc_helper.h"

#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)

struct omap_crtc {
	struct drm_crtc base;
	struct drm_plane *plane;

	const char *name;
	int pipe;
	enum omap_channel channel;
	struct omap_overlay_manager_info info;

	/*
	 * Temporary: eventually this will go away, but it is needed
	 * for now to keep the output's happy.  (They only need
	 * mgr->id.)  Eventually this will be replaced w/ something
	 * more common-panel-framework-y
	 */
	struct omap_overlay_manager mgr;

	struct omap_video_timings timings;
	bool enabled;
	bool full_update;

	struct omap_drm_apply apply;

	struct omap_drm_irq apply_irq;
	struct omap_drm_irq error_irq;

	/* list of in-progress apply's: */
	struct list_head pending_applies;

	/* list of queued apply's: */
	struct list_head queued_applies;

	/* for handling queued and in-progress applies: */
	struct work_struct apply_work;

	/* if there is a pending flip, these will be non-null: */
	struct drm_pending_vblank_event *event;
	struct drm_framebuffer *old_fb;

	/* for handling page flips without caring about what
	 * the callback is called from.  Possibly we should just
	 * make omap_gem always call the cb from the worker so
	 * we don't have to care about this..
	 *
	 * XXX maybe fold into apply_work??
	 */
	struct work_struct page_flip_work;
};

uint32_t pipe2vbl(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	return dispc_mgr_get_vsync_irq(omap_crtc->channel);
}

/*
 * Manager-ops, callbacks from output when they need to configure
 * the upstream part of the video pipe.
 *
 * Most of these we can ignore until we add support for command-mode
 * panels.. for video-mode the crtc-helpers already do an adequate
 * job of sequencing the setup of the video pipe in the proper order
 */

/* we can probably ignore these until we support command-mode panels: */
static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
{
}

static int omap_crtc_enable(struct omap_overlay_manager *mgr)
{
	return 0;
}

static void omap_crtc_disable(struct omap_overlay_manager *mgr)
{
}

static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
		const struct omap_video_timings *timings)
{
	struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr);
	DBG("%s", omap_crtc->name);
	omap_crtc->timings = *timings;
	omap_crtc->full_update = true;
}

static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
		const struct dss_lcd_mgr_config *config)
{
	struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr);
	DBG("%s", omap_crtc->name);
	dispc_mgr_set_lcd_config(omap_crtc->channel, config);
}

static int omap_crtc_register_framedone_handler(
		struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data)
{
	return 0;
}

static void omap_crtc_unregister_framedone_handler(
		struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data)
{
}

static const struct dss_mgr_ops mgr_ops = {
		.start_update = omap_crtc_start_update,
		.enable = omap_crtc_enable,
		.disable = omap_crtc_disable,
		.set_timings = omap_crtc_set_timings,
		.set_lcd_config = omap_crtc_set_lcd_config,
		.register_framedone_handler = omap_crtc_register_framedone_handler,
		.unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
};

/*
 * CRTC funcs:
 */

static void omap_crtc_destroy(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	DBG("%s", omap_crtc->name);

	WARN_ON(omap_crtc->apply_irq.registered);
	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);

	omap_crtc->plane->funcs->destroy(omap_crtc->plane);
	drm_crtc_cleanup(crtc);

	kfree(omap_crtc);
}

static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct omap_drm_private *priv = crtc->dev->dev_private;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	bool enabled = (mode == DRM_MODE_DPMS_ON);
	int i;

	DBG("%s: %d", omap_crtc->name, mode);

	if (enabled != omap_crtc->enabled) {
		omap_crtc->enabled = enabled;
		omap_crtc->full_update = true;
		omap_crtc_apply(crtc, &omap_crtc->apply);

		/* also enable our private plane: */
		WARN_ON(omap_plane_dpms(omap_crtc->plane, mode));

		/* and any attached overlay planes: */
		for (i = 0; i < priv->num_planes; i++) {
			struct drm_plane *plane = priv->planes[i];
			if (plane->crtc == crtc)
				WARN_ON(omap_plane_dpms(plane, mode));
		}
	}
}

static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
		const struct drm_display_mode *mode,
		struct drm_display_mode *adjusted_mode)
{
	return true;
}

static int omap_crtc_mode_set(struct drm_crtc *crtc,
		struct drm_display_mode *mode,
		struct drm_display_mode *adjusted_mode,
		int x, int y,
		struct drm_framebuffer *old_fb)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	mode = adjusted_mode;

	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
			omap_crtc->name, mode->base.id, mode->name,
			mode->vrefresh, mode->clock,
			mode->hdisplay, mode->hsync_start,
			mode->hsync_end, mode->htotal,
			mode->vdisplay, mode->vsync_start,
			mode->vsync_end, mode->vtotal,
			mode->type, mode->flags);

	copy_timings_drm_to_omap(&omap_crtc->timings, mode);
	omap_crtc->full_update = true;

	return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
			0, 0, mode->hdisplay, mode->vdisplay,
			x << 16, y << 16,
			mode->hdisplay << 16, mode->vdisplay << 16,
			NULL, NULL);
}

static void omap_crtc_prepare(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	DBG("%s", omap_crtc->name);
	omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
}

static void omap_crtc_commit(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	DBG("%s", omap_crtc->name);
	omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
}

static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
		struct drm_framebuffer *old_fb)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	struct drm_plane *plane = omap_crtc->plane;
	struct drm_display_mode *mode = &crtc->mode;

	return omap_plane_mode_set(plane, crtc, crtc->fb,
			0, 0, mode->hdisplay, mode->vdisplay,
			x << 16, y << 16,
			mode->hdisplay << 16, mode->vdisplay << 16,
			NULL, NULL);
}

static void omap_crtc_load_lut(struct drm_crtc *crtc)
{
}

static void vblank_cb(void *arg)
{
	struct drm_crtc *crtc = arg;
	struct drm_device *dev = crtc->dev;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);

	/* wakeup userspace */
	if (omap_crtc->event)
		drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);

	omap_crtc->event = NULL;
	omap_crtc->old_fb = NULL;

	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static void page_flip_worker(struct work_struct *work)
{
	struct omap_crtc *omap_crtc =
			container_of(work, struct omap_crtc, page_flip_work);
	struct drm_crtc *crtc = &omap_crtc->base;
	struct drm_display_mode *mode = &crtc->mode;
	struct drm_gem_object *bo;

	mutex_lock(&crtc->mutex);
	omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
			0, 0, mode->hdisplay, mode->vdisplay,
			crtc->x << 16, crtc->y << 16,
			mode->hdisplay << 16, mode->vdisplay << 16,
			vblank_cb, crtc);
	mutex_unlock(&crtc->mutex);

	bo = omap_framebuffer_bo(crtc->fb, 0);
	drm_gem_object_unreference_unlocked(bo);
}

static void page_flip_cb(void *arg)
{
	struct drm_crtc *crtc = arg;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	struct omap_drm_private *priv = crtc->dev->dev_private;

	/* avoid assumptions about what ctxt we are called from: */
	queue_work(priv->wq, &omap_crtc->page_flip_work);
}

static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
		 struct drm_framebuffer *fb,
		 struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	struct drm_gem_object *bo;

	DBG("%d -> %d (event=%p)", crtc->fb ? crtc->fb->base.id : -1,
			fb->base.id, event);

	if (omap_crtc->old_fb) {
		dev_err(dev->dev, "already a pending flip\n");
		return -EINVAL;
	}

	omap_crtc->event = event;
	crtc->fb = fb;

	/*
	 * Hold a reference temporarily until the crtc is updated
	 * and takes the reference to the bo.  This avoids it
	 * getting freed from under us:
	 */
	bo = omap_framebuffer_bo(fb, 0);
	drm_gem_object_reference(bo);

	omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);

	return 0;
}

static int omap_crtc_set_property(struct drm_crtc *crtc,
		struct drm_property *property, uint64_t val)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	struct omap_drm_private *priv = crtc->dev->dev_private;

	if (property == priv->rotation_prop) {
		crtc->invert_dimensions =
				!!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270)));
	}

	return omap_plane_set_property(omap_crtc->plane, property, val);
}

static const struct drm_crtc_funcs omap_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = omap_crtc_destroy,
	.page_flip = omap_crtc_page_flip_locked,
	.set_property = omap_crtc_set_property,
};

static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
	.dpms = omap_crtc_dpms,
	.mode_fixup = omap_crtc_mode_fixup,
	.mode_set = omap_crtc_mode_set,
	.prepare = omap_crtc_prepare,
	.commit = omap_crtc_commit,
	.mode_set_base = omap_crtc_mode_set_base,
	.load_lut = omap_crtc_load_lut,
};

const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	return &omap_crtc->timings;
}

enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	return omap_crtc->channel;
}

static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
	struct omap_crtc *omap_crtc =
			container_of(irq, struct omap_crtc, error_irq);
	struct drm_crtc *crtc = &omap_crtc->base;
	DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
	/* avoid getting in a flood, unregister the irq until next vblank */
	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
}

static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
	struct omap_crtc *omap_crtc =
			container_of(irq, struct omap_crtc, apply_irq);
	struct drm_crtc *crtc = &omap_crtc->base;

	if (!omap_crtc->error_irq.registered)
		omap_irq_register(crtc->dev, &omap_crtc->error_irq);

	if (!dispc_mgr_go_busy(omap_crtc->channel)) {
		struct omap_drm_private *priv =
				crtc->dev->dev_private;
		DBG("%s: apply done", omap_crtc->name);
		omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
		queue_work(priv->wq, &omap_crtc->apply_work);
	}
}

static void apply_worker(struct work_struct *work)
{
	struct omap_crtc *omap_crtc =
			container_of(work, struct omap_crtc, apply_work);
	struct drm_crtc *crtc = &omap_crtc->base;
	struct drm_device *dev = crtc->dev;
	struct omap_drm_apply *apply, *n;
	bool need_apply;

	/*
	 * Synchronize everything on mode_config.mutex, to keep
	 * the callbacks and list modification all serialized
	 * with respect to modesetting ioctls from userspace.
	 */
	mutex_lock(&crtc->mutex);
	dispc_runtime_get();

	/*
	 * If we are still pending a previous update, wait.. when the
	 * pending update completes, we get kicked again.
	 */
	if (omap_crtc->apply_irq.registered)
		goto out;

	/* finish up previous apply's: */
	list_for_each_entry_safe(apply, n,
			&omap_crtc->pending_applies, pending_node) {
		apply->post_apply(apply);
		list_del(&apply->pending_node);
	}

	need_apply = !list_empty(&omap_crtc->queued_applies);

	/* then handle the next round of of queued apply's: */
	list_for_each_entry_safe(apply, n,
			&omap_crtc->queued_applies, queued_node) {
		apply->pre_apply(apply);
		list_del(&apply->queued_node);
		apply->queued = false;
		list_add_tail(&apply->pending_node,
				&omap_crtc->pending_applies);
	}

	if (need_apply) {
		enum omap_channel channel = omap_crtc->channel;

		DBG("%s: GO", omap_crtc->name);

		if (dispc_mgr_is_enabled(channel)) {
			omap_irq_register(dev, &omap_crtc->apply_irq);
			dispc_mgr_go(channel);
		} else {
			struct omap_drm_private *priv = dev->dev_private;
			queue_work(priv->wq, &omap_crtc->apply_work);
		}
	}

out:
	dispc_runtime_put();
	mutex_unlock(&crtc->mutex);
}

int omap_crtc_apply(struct drm_crtc *crtc,
		struct omap_drm_apply *apply)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	WARN_ON(!mutex_is_locked(&crtc->mutex));

	/* no need to queue it again if it is already queued: */
	if (apply->queued)
		return 0;

	apply->queued = true;
	list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);

	/*
	 * If there are no currently pending updates, then go ahead and
	 * kick the worker immediately, otherwise it will run again when
	 * the current update finishes.
	 */
	if (list_empty(&omap_crtc->pending_applies)) {
		struct omap_drm_private *priv = crtc->dev->dev_private;
		queue_work(priv->wq, &omap_crtc->apply_work);
	}

	return 0;
}

/* called only from apply */
static void set_enabled(struct drm_crtc *crtc, bool enable)
{
	struct drm_device *dev = crtc->dev;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	enum omap_channel channel = omap_crtc->channel;
	struct omap_irq_wait *wait = NULL;

	if (dispc_mgr_is_enabled(channel) == enable)
		return;

	/* ignore sync-lost irqs during enable/disable */
	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);

	if (dispc_mgr_get_framedone_irq(channel)) {
		if (!enable) {
			wait = omap_irq_wait_init(dev,
					dispc_mgr_get_framedone_irq(channel), 1);
		}
	} else {
		/*
		 * When we disable digit output, we need to wait until fields
		 * are done.  Otherwise the DSS is still working, and turning
		 * off the clocks prevents DSS from going to OFF mode. And when
		 * enabling, we need to wait for the extra sync losts
		 */
		wait = omap_irq_wait_init(dev,
				dispc_mgr_get_vsync_irq(channel), 2);
	}

	dispc_mgr_enable(channel, enable);

	if (wait) {
		int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
		if (ret) {
			dev_err(dev->dev, "%s: timeout waiting for %s\n",
					omap_crtc->name, enable ? "enable" : "disable");
		}
	}

	omap_irq_register(crtc->dev, &omap_crtc->error_irq);
}

static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
{
	struct omap_crtc *omap_crtc =
			container_of(apply, struct omap_crtc, apply);
	struct drm_crtc *crtc = &omap_crtc->base;
	struct drm_encoder *encoder = NULL;

	DBG("%s: enabled=%d, full=%d", omap_crtc->name,
			omap_crtc->enabled, omap_crtc->full_update);

	if (omap_crtc->full_update) {
		struct omap_drm_private *priv = crtc->dev->dev_private;
		int i;
		for (i = 0; i < priv->num_encoders; i++) {
			if (priv->encoders[i]->crtc == crtc) {
				encoder = priv->encoders[i];
				break;
			}
		}
	}

	if (!omap_crtc->enabled) {
		set_enabled(&omap_crtc->base, false);
		if (encoder)
			omap_encoder_set_enabled(encoder, false);
	} else {
		if (encoder) {
			omap_encoder_set_enabled(encoder, false);
			omap_encoder_update(encoder, &omap_crtc->mgr,
					&omap_crtc->timings);
			omap_encoder_set_enabled(encoder, true);
			omap_crtc->full_update = false;
		}

		dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
		dispc_mgr_set_timings(omap_crtc->channel,
				&omap_crtc->timings);
		set_enabled(&omap_crtc->base, true);
	}

	omap_crtc->full_update = false;
}

static void omap_crtc_post_apply(struct omap_drm_apply *apply)
{
	/* nothing needed for post-apply */
}

static const char *channel_names[] = {
		[OMAP_DSS_CHANNEL_LCD] = "lcd",
		[OMAP_DSS_CHANNEL_DIGIT] = "tv",
		[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
};

/* initialize crtc */
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
		struct drm_plane *plane, enum omap_channel channel, int id)
{
	struct drm_crtc *crtc = NULL;
	struct omap_crtc *omap_crtc;
	struct omap_overlay_manager_info *info;

	DBG("%s", channel_names[channel]);

	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
	if (!omap_crtc)
		goto fail;

	crtc = &omap_crtc->base;

	INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
	INIT_WORK(&omap_crtc->apply_work, apply_worker);

	INIT_LIST_HEAD(&omap_crtc->pending_applies);
	INIT_LIST_HEAD(&omap_crtc->queued_applies);

	omap_crtc->apply.pre_apply  = omap_crtc_pre_apply;
	omap_crtc->apply.post_apply = omap_crtc_post_apply;

	omap_crtc->channel = channel;
	omap_crtc->plane = plane;
	omap_crtc->plane->crtc = crtc;
	omap_crtc->name = channel_names[channel];
	omap_crtc->pipe = id;

	omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
	omap_crtc->apply_irq.irq = omap_crtc_apply_irq;

	omap_crtc->error_irq.irqmask =
			dispc_mgr_get_sync_lost_irq(channel);
	omap_crtc->error_irq.irq = omap_crtc_error_irq;
	omap_irq_register(dev, &omap_crtc->error_irq);

	/* temporary: */
	omap_crtc->mgr.id = channel;

	dss_install_mgr_ops(&mgr_ops);

	/* TODO: fix hard-coded setup.. add properties! */
	info = &omap_crtc->info;
	info->default_color = 0x00000000;
	info->trans_key = 0x00000000;
	info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
	info->trans_enabled = false;

	drm_crtc_init(dev, crtc, &omap_crtc_funcs);
	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);

	omap_plane_install_properties(omap_crtc->plane, &crtc->base);

	return crtc;

fail:
	if (crtc)
		omap_crtc_destroy(crtc);

	return NULL;
}
Commit	Line	Data
cd5351f4	1	/*
8bb0daff	2	* drivers/gpu/drm/omapdrm/omap_crtc.c
cd5351f4 RC	3	*
	4	* Copyright (C) 2011 Texas Instruments
	5	* Author: Rob Clark <rob@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "omap_drv.h"
	21
b9ed9f0e	22	#include <drm/drm_mode.h>
cd5351f4 RC	23	#include "drm_crtc.h"
	24	#include "drm_crtc_helper.h"
	25
	26	#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
	27
	28	struct omap_crtc {
	29	struct drm_crtc base;
bb5c2d9a	30	struct drm_plane *plane;
f5f9454c	31
bb5c2d9a	32	const char *name;
f5f9454c RC	33	int pipe;
	34	enum omap_channel channel;
	35	struct omap_overlay_manager_info info;
	36
	37	/*
	38	* Temporary: eventually this will go away, but it is needed
	39	* for now to keep the output's happy. (They only need
	40	* mgr->id.) Eventually this will be replaced w/ something
	41	* more common-panel-framework-y
	42	*/
	43	struct omap_overlay_manager mgr;
	44
	45	struct omap_video_timings timings;
	46	bool enabled;
	47	bool full_update;
	48
	49	struct omap_drm_apply apply;
	50
	51	struct omap_drm_irq apply_irq;
	52	struct omap_drm_irq error_irq;
	53
	54	/* list of in-progress apply's: */
	55	struct list_head pending_applies;
	56
	57	/* list of queued apply's: */
	58	struct list_head queued_applies;
	59
	60	/* for handling queued and in-progress applies: */
	61	struct work_struct apply_work;
cd5351f4	62
bb5c2d9a	63	/* if there is a pending flip, these will be non-null: */
cd5351f4	64	struct drm_pending_vblank_event *event;
bb5c2d9a	65	struct drm_framebuffer *old_fb;
f5f9454c RC	66
	67	/* for handling page flips without caring about what
	68	* the callback is called from. Possibly we should just
	69	* make omap_gem always call the cb from the worker so
	70	* we don't have to care about this..
	71	*
	72	* XXX maybe fold into apply_work??
	73	*/
	74	struct work_struct page_flip_work;
	75	};
	76
0d8f371f AT	77	uint32_t pipe2vbl(struct drm_crtc *crtc)
	78	{
	79	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	80
	81	return dispc_mgr_get_vsync_irq(omap_crtc->channel);
	82	}
	83
f5f9454c RC	84	/*
	85	* Manager-ops, callbacks from output when they need to configure
	86	* the upstream part of the video pipe.
	87	*
	88	* Most of these we can ignore until we add support for command-mode
	89	* panels.. for video-mode the crtc-helpers already do an adequate
	90	* job of sequencing the setup of the video pipe in the proper order
	91	*/
	92
	93	/* we can probably ignore these until we support command-mode panels: */
	94	static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
	95	{
	96	}
	97
	98	static int omap_crtc_enable(struct omap_overlay_manager *mgr)
	99	{
	100	return 0;
	101	}
	102
	103	static void omap_crtc_disable(struct omap_overlay_manager *mgr)
	104	{
	105	}
	106
	107	static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
	108	const struct omap_video_timings *timings)
	109	{
	110	struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr);
	111	DBG("%s", omap_crtc->name);
	112	omap_crtc->timings = *timings;
	113	omap_crtc->full_update = true;
	114	}
	115
	116	static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
	117	const struct dss_lcd_mgr_config *config)
	118	{
	119	struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr);
	120	DBG("%s", omap_crtc->name);
	121	dispc_mgr_set_lcd_config(omap_crtc->channel, config);
	122	}
	123
	124	static int omap_crtc_register_framedone_handler(
	125	struct omap_overlay_manager *mgr,
	126	void (handler)(void ), void *data)
	127	{
	128	return 0;
	129	}
	130
	131	static void omap_crtc_unregister_framedone_handler(
	132	struct omap_overlay_manager *mgr,
	133	void (handler)(void ), void *data)
	134	{
	135	}
	136
	137	static const struct dss_mgr_ops mgr_ops = {
	138	.start_update = omap_crtc_start_update,
	139	.enable = omap_crtc_enable,
	140	.disable = omap_crtc_disable,
	141	.set_timings = omap_crtc_set_timings,
	142	.set_lcd_config = omap_crtc_set_lcd_config,
	143	.register_framedone_handler = omap_crtc_register_framedone_handler,
	144	.unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
cd5351f4 RC	145	};
cd5351f4 RC	146
f5f9454c RC	147	/*
	148	* CRTC funcs:
	149	*/
	150
cd5351f4 RC	151	static void omap_crtc_destroy(struct drm_crtc *crtc)
	152	{
	153	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f5f9454c RC	154
	155	DBG("%s", omap_crtc->name);
	156
	157	WARN_ON(omap_crtc->apply_irq.registered);
	158	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
	159
bb5c2d9a	160	omap_crtc->plane->funcs->destroy(omap_crtc->plane);
cd5351f4	161	drm_crtc_cleanup(crtc);
f5f9454c	162
cd5351f4 RC	163	kfree(omap_crtc);
	164	}
	165
	166	static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
	167	{
bb5c2d9a	168	struct omap_drm_private *priv = crtc->dev->dev_private;
cd5351f4	169	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f5f9454c	170	bool enabled = (mode == DRM_MODE_DPMS_ON);
bb5c2d9a	171	int i;
cd5351f4	172
f5f9454c RC	173	DBG("%s: %d", omap_crtc->name, mode);
	174
	175	if (enabled != omap_crtc->enabled) {
	176	omap_crtc->enabled = enabled;
	177	omap_crtc->full_update = true;
	178	omap_crtc_apply(crtc, &omap_crtc->apply);
cd5351f4	179
f5f9454c RC	180	/* also enable our private plane: */
	181	WARN_ON(omap_plane_dpms(omap_crtc->plane, mode));
	182
	183	/* and any attached overlay planes: */
	184	for (i = 0; i < priv->num_planes; i++) {
	185	struct drm_plane *plane = priv->planes[i];
	186	if (plane->crtc == crtc)
	187	WARN_ON(omap_plane_dpms(plane, mode));
	188	}
cd5351f4	189	}
cd5351f4 RC	190	}
	191
	192	static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae	193	const struct drm_display_mode *mode,
bb5c2d9a	194	struct drm_display_mode *adjusted_mode)
cd5351f4	195	{
cd5351f4 RC	196	return true;
	197	}
	198
	199	static int omap_crtc_mode_set(struct drm_crtc *crtc,
bb5c2d9a RC	200	struct drm_display_mode *mode,
	201	struct drm_display_mode *adjusted_mode,
	202	int x, int y,
	203	struct drm_framebuffer *old_fb)
cd5351f4 RC	204	{
	205	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	206
f5f9454c RC	207	mode = adjusted_mode;
	208
	209	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
	210	omap_crtc->name, mode->base.id, mode->name,
	211	mode->vrefresh, mode->clock,
	212	mode->hdisplay, mode->hsync_start,
	213	mode->hsync_end, mode->htotal,
	214	mode->vdisplay, mode->vsync_start,
	215	mode->vsync_end, mode->vtotal,
	216	mode->type, mode->flags);
	217
	218	copy_timings_drm_to_omap(&omap_crtc->timings, mode);
	219	omap_crtc->full_update = true;
	220
	221	return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
bb5c2d9a RC	222	0, 0, mode->hdisplay, mode->vdisplay,
bb5c2d9a RC	223	x << 16, y << 16,
f5f9454c RC	224	mode->hdisplay << 16, mode->vdisplay << 16,
f5f9454c RC	225	NULL, NULL);
cd5351f4 RC	226	}
	227
	228	static void omap_crtc_prepare(struct drm_crtc *crtc)
	229	{
	230	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
bb5c2d9a	231	DBG("%s", omap_crtc->name);
cd5351f4 RC	232	omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
	233	}
	234
	235	static void omap_crtc_commit(struct drm_crtc *crtc)
	236	{
	237	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
bb5c2d9a	238	DBG("%s", omap_crtc->name);
cd5351f4 RC	239	omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
	240	}
	241
	242	static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
bb5c2d9a	243	struct drm_framebuffer *old_fb)
cd5351f4 RC	244	{
cd5351f4 RC	245	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
bb5c2d9a RC	246	struct drm_plane *plane = omap_crtc->plane;
bb5c2d9a RC	247	struct drm_display_mode *mode = &crtc->mode;
cd5351f4	248
f5f9454c	249	return omap_plane_mode_set(plane, crtc, crtc->fb,
bb5c2d9a RC	250	0, 0, mode->hdisplay, mode->vdisplay,
bb5c2d9a RC	251	x << 16, y << 16,
f5f9454c RC	252	mode->hdisplay << 16, mode->vdisplay << 16,
f5f9454c RC	253	NULL, NULL);
cd5351f4 RC	254	}
	255
	256	static void omap_crtc_load_lut(struct drm_crtc *crtc)
	257	{
cd5351f4 RC	258	}
cd5351f4 RC	259
72d0c336	260	static void vblank_cb(void *arg)
cd5351f4 RC	261	{
	262	struct drm_crtc *crtc = arg;
	263	struct drm_device *dev = crtc->dev;
	264	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
cd5351f4 RC	265	unsigned long flags;
cd5351f4 RC	266
f5f9454c RC	267	spin_lock_irqsave(&dev->event_lock, flags);
	268
	269	/* wakeup userspace */
	270	if (omap_crtc->event)
	271	drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);
cd5351f4 RC	272
cd5351f4 RC	273	omap_crtc->event = NULL;
f5f9454c	274	omap_crtc->old_fb = NULL;
cd5351f4	275
f5f9454c	276	spin_unlock_irqrestore(&dev->event_lock, flags);
cd5351f4 RC	277	}
cd5351f4 RC	278
f5f9454c	279	static void page_flip_worker(struct work_struct *work)
72d0c336	280	{
f5f9454c RC	281	struct omap_crtc *omap_crtc =
	282	container_of(work, struct omap_crtc, page_flip_work);
	283	struct drm_crtc *crtc = &omap_crtc->base;
f5f9454c	284	struct drm_display_mode *mode = &crtc->mode;
119c0814	285	struct drm_gem_object *bo;
72d0c336	286
16ef3dfe	287	mutex_lock(&crtc->mutex);
f5f9454c RC	288	omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb,
	289	0, 0, mode->hdisplay, mode->vdisplay,
	290	crtc->x << 16, crtc->y << 16,
	291	mode->hdisplay << 16, mode->vdisplay << 16,
	292	vblank_cb, crtc);
16ef3dfe	293	mutex_unlock(&crtc->mutex);
119c0814 RC	294
	295	bo = omap_framebuffer_bo(crtc->fb, 0);
	296	drm_gem_object_unreference_unlocked(bo);
72d0c336 RC	297	}
72d0c336 RC	298
f5f9454c RC	299	static void page_flip_cb(void *arg)
	300	{
	301	struct drm_crtc *crtc = arg;
	302	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	303	struct omap_drm_private *priv = crtc->dev->dev_private;
	304
	305	/* avoid assumptions about what ctxt we are called from: */
	306	queue_work(priv->wq, &omap_crtc->page_flip_work);
	307	}
	308
cd5351f4 RC	309	static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
	310	struct drm_framebuffer *fb,
	311	struct drm_pending_vblank_event *event)
	312	{
	313	struct drm_device *dev = crtc->dev;
	314	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
119c0814	315	struct drm_gem_object *bo;
cd5351f4	316
f5f9454c RC	317	DBG("%d -> %d (event=%p)", crtc->fb ? crtc->fb->base.id : -1,
f5f9454c RC	318	fb->base.id, event);
cd5351f4	319
f5f9454c	320	if (omap_crtc->old_fb) {
cd5351f4 RC	321	dev_err(dev->dev, "already a pending flip\n");
	322	return -EINVAL;
	323	}
	324
cd5351f4	325	omap_crtc->event = event;
bb5c2d9a	326	crtc->fb = fb;
cd5351f4	327
119c0814 RC	328	/*
	329	* Hold a reference temporarily until the crtc is updated
	330	* and takes the reference to the bo. This avoids it
	331	* getting freed from under us:
	332	*/
	333	bo = omap_framebuffer_bo(fb, 0);
	334	drm_gem_object_reference(bo);
	335
	336	omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);
cd5351f4 RC	337
	338	return 0;
	339	}
	340
3c810c61 RC	341	static int omap_crtc_set_property(struct drm_crtc *crtc,
	342	struct drm_property *property, uint64_t val)
	343	{
	344	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
1e0fdfc2 RC	345	struct omap_drm_private *priv = crtc->dev->dev_private;
	346
	347	if (property == priv->rotation_prop) {
	348	crtc->invert_dimensions =
	349	!!(val & ((1LL << DRM_ROTATE_90) \| (1LL << DRM_ROTATE_270)));
	350	}
	351
3c810c61 RC	352	return omap_plane_set_property(omap_crtc->plane, property, val);
	353	}
	354
cd5351f4	355	static const struct drm_crtc_funcs omap_crtc_funcs = {
cd5351f4 RC	356	.set_config = drm_crtc_helper_set_config,
	357	.destroy = omap_crtc_destroy,
	358	.page_flip = omap_crtc_page_flip_locked,
3c810c61	359	.set_property = omap_crtc_set_property,
cd5351f4 RC	360	};
	361
	362	static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
	363	.dpms = omap_crtc_dpms,
	364	.mode_fixup = omap_crtc_mode_fixup,
	365	.mode_set = omap_crtc_mode_set,
	366	.prepare = omap_crtc_prepare,
	367	.commit = omap_crtc_commit,
	368	.mode_set_base = omap_crtc_mode_set_base,
	369	.load_lut = omap_crtc_load_lut,
	370	};
	371
f5f9454c RC	372	const struct omap_video_timings omap_crtc_timings(struct drm_crtc crtc)
	373	{
	374	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	375	return &omap_crtc->timings;
	376	}
	377
	378	enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
	379	{
	380	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	381	return omap_crtc->channel;
	382	}
	383
	384	static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
	385	{
	386	struct omap_crtc *omap_crtc =
	387	container_of(irq, struct omap_crtc, error_irq);
	388	struct drm_crtc *crtc = &omap_crtc->base;
	389	DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
	390	/* avoid getting in a flood, unregister the irq until next vblank */
	391	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
	392	}
	393
	394	static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
	395	{
	396	struct omap_crtc *omap_crtc =
	397	container_of(irq, struct omap_crtc, apply_irq);
	398	struct drm_crtc *crtc = &omap_crtc->base;
	399
	400	if (!omap_crtc->error_irq.registered)
	401	omap_irq_register(crtc->dev, &omap_crtc->error_irq);
	402
	403	if (!dispc_mgr_go_busy(omap_crtc->channel)) {
	404	struct omap_drm_private *priv =
	405	crtc->dev->dev_private;
	406	DBG("%s: apply done", omap_crtc->name);
	407	omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
	408	queue_work(priv->wq, &omap_crtc->apply_work);
	409	}
	410	}
	411
	412	static void apply_worker(struct work_struct *work)
	413	{
	414	struct omap_crtc *omap_crtc =
	415	container_of(work, struct omap_crtc, apply_work);
	416	struct drm_crtc *crtc = &omap_crtc->base;
	417	struct drm_device *dev = crtc->dev;
	418	struct omap_drm_apply apply, n;
	419	bool need_apply;
	420
	421	/*
	422	* Synchronize everything on mode_config.mutex, to keep
	423	* the callbacks and list modification all serialized
	424	* with respect to modesetting ioctls from userspace.
	425	*/
16ef3dfe	426	mutex_lock(&crtc->mutex);
f5f9454c RC	427	dispc_runtime_get();
	428
	429	/*
	430	* If we are still pending a previous update, wait.. when the
	431	* pending update completes, we get kicked again.
	432	*/
	433	if (omap_crtc->apply_irq.registered)
	434	goto out;
	435
	436	/* finish up previous apply's: */
	437	list_for_each_entry_safe(apply, n,
	438	&omap_crtc->pending_applies, pending_node) {
	439	apply->post_apply(apply);
	440	list_del(&apply->pending_node);
	441	}
	442
	443	need_apply = !list_empty(&omap_crtc->queued_applies);
	444
	445	/* then handle the next round of of queued apply's: */
	446	list_for_each_entry_safe(apply, n,
	447	&omap_crtc->queued_applies, queued_node) {
	448	apply->pre_apply(apply);
	449	list_del(&apply->queued_node);
	450	apply->queued = false;
	451	list_add_tail(&apply->pending_node,
	452	&omap_crtc->pending_applies);
	453	}
	454
	455	if (need_apply) {
	456	enum omap_channel channel = omap_crtc->channel;
	457
	458	DBG("%s: GO", omap_crtc->name);
	459
	460	if (dispc_mgr_is_enabled(channel)) {
	461	omap_irq_register(dev, &omap_crtc->apply_irq);
	462	dispc_mgr_go(channel);
	463	} else {
	464	struct omap_drm_private *priv = dev->dev_private;
	465	queue_work(priv->wq, &omap_crtc->apply_work);
	466	}
	467	}
	468
	469	out:
	470	dispc_runtime_put();
16ef3dfe	471	mutex_unlock(&crtc->mutex);
f5f9454c RC	472	}
	473
	474	int omap_crtc_apply(struct drm_crtc *crtc,
	475	struct omap_drm_apply *apply)
	476	{
	477	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f5f9454c	478
16ef3dfe	479	WARN_ON(!mutex_is_locked(&crtc->mutex));
f5f9454c RC	480
	481	/* no need to queue it again if it is already queued: */
	482	if (apply->queued)
	483	return 0;
	484
	485	apply->queued = true;
	486	list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);
	487
	488	/*
	489	* If there are no currently pending updates, then go ahead and
	490	* kick the worker immediately, otherwise it will run again when
	491	* the current update finishes.
	492	*/
	493	if (list_empty(&omap_crtc->pending_applies)) {
	494	struct omap_drm_private *priv = crtc->dev->dev_private;
	495	queue_work(priv->wq, &omap_crtc->apply_work);
	496	}
	497
	498	return 0;
	499	}
	500
	501	/* called only from apply */
	502	static void set_enabled(struct drm_crtc *crtc, bool enable)
	503	{
	504	struct drm_device *dev = crtc->dev;
	505	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	506	enum omap_channel channel = omap_crtc->channel;
	507	struct omap_irq_wait *wait = NULL;
	508
	509	if (dispc_mgr_is_enabled(channel) == enable)
	510	return;
	511
	512	/* ignore sync-lost irqs during enable/disable */
	513	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
	514
	515	if (dispc_mgr_get_framedone_irq(channel)) {
	516	if (!enable) {
	517	wait = omap_irq_wait_init(dev,
	518	dispc_mgr_get_framedone_irq(channel), 1);
	519	}
	520	} else {
	521	/*
	522	* When we disable digit output, we need to wait until fields
	523	* are done. Otherwise the DSS is still working, and turning
	524	* off the clocks prevents DSS from going to OFF mode. And when
	525	* enabling, we need to wait for the extra sync losts
	526	*/
	527	wait = omap_irq_wait_init(dev,
	528	dispc_mgr_get_vsync_irq(channel), 2);
	529	}
	530
	531	dispc_mgr_enable(channel, enable);
	532
	533	if (wait) {
	534	int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
	535	if (ret) {
	536	dev_err(dev->dev, "%s: timeout waiting for %s\n",
	537	omap_crtc->name, enable ? "enable" : "disable");
	538	}
	539	}
	540
	541	omap_irq_register(crtc->dev, &omap_crtc->error_irq);
	542	}
	543
544	static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
545	{
546	struct omap_crtc *omap_crtc =
547	container_of(apply, struct omap_crtc, apply);
548	struct drm_crtc *crtc = &omap_crtc->base;
549	struct drm_encoder *encoder = NULL;
550
551	DBG("%s: enabled=%d, full=%d", omap_crtc->name,
552	omap_crtc->enabled, omap_crtc->full_update);
553
554	if (omap_crtc->full_update) {
555	struct omap_drm_private *priv = crtc->dev->dev_private;
556	int i;
557	for (i = 0; i < priv->num_encoders; i++) {
558	if (priv->encoders[i]->crtc == crtc) {
559	encoder = priv->encoders[i];
560	break;
561	}
562	}
563	}
564
565	if (!omap_crtc->enabled) {
566	set_enabled(&omap_crtc->base, false);
567	if (encoder)
568	omap_encoder_set_enabled(encoder, false);
569	} else {
570	if (encoder) {
571	omap_encoder_set_enabled(encoder, false);
572	omap_encoder_update(encoder, &omap_crtc->mgr,
573	&omap_crtc->timings);
574	omap_encoder_set_enabled(encoder, true);
575	omap_crtc->full_update = false;
576	}
577
578	dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
579	dispc_mgr_set_timings(omap_crtc->channel,
580	&omap_crtc->timings);
581	set_enabled(&omap_crtc->base, true);
582	}
583
584	omap_crtc->full_update = false;
585	}
586
587	static void omap_crtc_post_apply(struct omap_drm_apply *apply)
588	{
589	/* nothing needed for post-apply */
590	}
591
592	static const char *channel_names[] = {
593	[OMAP_DSS_CHANNEL_LCD] = "lcd",
594	[OMAP_DSS_CHANNEL_DIGIT] = "tv",
595	[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
596	};
597
cd5351f4 RC	598	/* initialize crtc */
cd5351f4 RC	599	struct drm_crtc omap_crtc_init(struct drm_device dev,
f5f9454c	600	struct drm_plane *plane, enum omap_channel channel, int id)
cd5351f4 RC	601	{
cd5351f4 RC	602	struct drm_crtc *crtc = NULL;
f5f9454c RC	603	struct omap_crtc *omap_crtc;
	604	struct omap_overlay_manager_info *info;
	605
	606	DBG("%s", channel_names[channel]);
cd5351f4	607
f5f9454c	608	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
78110bb8	609	if (!omap_crtc)
cd5351f4	610	goto fail;
cd5351f4	611
cd5351f4	612	crtc = &omap_crtc->base;
bb5c2d9a	613
f5f9454c RC	614	INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
	615	INIT_WORK(&omap_crtc->apply_work, apply_worker);
	616
	617	INIT_LIST_HEAD(&omap_crtc->pending_applies);
	618	INIT_LIST_HEAD(&omap_crtc->queued_applies);
	619
	620	omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
	621	omap_crtc->apply.post_apply = omap_crtc_post_apply;
	622
0d8f371f AT	623	omap_crtc->channel = channel;
	624	omap_crtc->plane = plane;
	625	omap_crtc->plane->crtc = crtc;
	626	omap_crtc->name = channel_names[channel];
	627	omap_crtc->pipe = id;
	628
	629	omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
f5f9454c RC	630	omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
	631
	632	omap_crtc->error_irq.irqmask =
	633	dispc_mgr_get_sync_lost_irq(channel);
	634	omap_crtc->error_irq.irq = omap_crtc_error_irq;
	635	omap_irq_register(dev, &omap_crtc->error_irq);
	636
f5f9454c RC	637	/* temporary: */
	638	omap_crtc->mgr.id = channel;
	639
	640	dss_install_mgr_ops(&mgr_ops);
	641
	642	/* TODO: fix hard-coded setup.. add properties! */
	643	info = &omap_crtc->info;
	644	info->default_color = 0x00000000;
	645	info->trans_key = 0x00000000;
	646	info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
	647	info->trans_enabled = false;
bb5c2d9a	648
cd5351f4 RC	649	drm_crtc_init(dev, crtc, &omap_crtc_funcs);
	650	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
	651
3c810c61 RC	652	omap_plane_install_properties(omap_crtc->plane, &crtc->base);
3c810c61 RC	653
cd5351f4 RC	654	return crtc;
	655
	656	fail:
d21a9d3b	657	if (crtc)
65b0bd06	658	omap_crtc_destroy(crtc);
d21a9d3b	659
cd5351f4 RC	660	return NULL;
cd5351f4 RC	661	}