Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
b9ed9f0e | 22 | #include <drm/drm_mode.h> |
cd5351f4 RC |
23 | #include "drm_crtc.h" |
24 | #include "drm_crtc_helper.h" | |
25 | ||
26 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
27 | ||
28 | struct omap_crtc { | |
29 | struct drm_crtc base; | |
bb5c2d9a | 30 | struct drm_plane *plane; |
f5f9454c | 31 | |
bb5c2d9a | 32 | const char *name; |
f5f9454c RC |
33 | int pipe; |
34 | enum omap_channel channel; | |
35 | struct omap_overlay_manager_info info; | |
36 | ||
37 | /* | |
38 | * Temporary: eventually this will go away, but it is needed | |
39 | * for now to keep the output's happy. (They only need | |
40 | * mgr->id.) Eventually this will be replaced w/ something | |
41 | * more common-panel-framework-y | |
42 | */ | |
43 | struct omap_overlay_manager mgr; | |
44 | ||
45 | struct omap_video_timings timings; | |
46 | bool enabled; | |
47 | bool full_update; | |
48 | ||
49 | struct omap_drm_apply apply; | |
50 | ||
51 | struct omap_drm_irq apply_irq; | |
52 | struct omap_drm_irq error_irq; | |
53 | ||
54 | /* list of in-progress apply's: */ | |
55 | struct list_head pending_applies; | |
56 | ||
57 | /* list of queued apply's: */ | |
58 | struct list_head queued_applies; | |
59 | ||
60 | /* for handling queued and in-progress applies: */ | |
61 | struct work_struct apply_work; | |
cd5351f4 | 62 | |
bb5c2d9a | 63 | /* if there is a pending flip, these will be non-null: */ |
cd5351f4 | 64 | struct drm_pending_vblank_event *event; |
bb5c2d9a | 65 | struct drm_framebuffer *old_fb; |
f5f9454c RC |
66 | |
67 | /* for handling page flips without caring about what | |
68 | * the callback is called from. Possibly we should just | |
69 | * make omap_gem always call the cb from the worker so | |
70 | * we don't have to care about this.. | |
71 | * | |
72 | * XXX maybe fold into apply_work?? | |
73 | */ | |
74 | struct work_struct page_flip_work; | |
75 | }; | |
76 | ||
0d8f371f AT |
77 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
78 | { | |
79 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
80 | ||
81 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
82 | } | |
83 | ||
f5f9454c RC |
84 | /* |
85 | * Manager-ops, callbacks from output when they need to configure | |
86 | * the upstream part of the video pipe. | |
87 | * | |
88 | * Most of these we can ignore until we add support for command-mode | |
89 | * panels.. for video-mode the crtc-helpers already do an adequate | |
90 | * job of sequencing the setup of the video pipe in the proper order | |
91 | */ | |
92 | ||
93 | /* we can probably ignore these until we support command-mode panels: */ | |
94 | static void omap_crtc_start_update(struct omap_overlay_manager *mgr) | |
95 | { | |
96 | } | |
97 | ||
98 | static int omap_crtc_enable(struct omap_overlay_manager *mgr) | |
99 | { | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static void omap_crtc_disable(struct omap_overlay_manager *mgr) | |
104 | { | |
105 | } | |
106 | ||
107 | static void omap_crtc_set_timings(struct omap_overlay_manager *mgr, | |
108 | const struct omap_video_timings *timings) | |
109 | { | |
110 | struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr); | |
111 | DBG("%s", omap_crtc->name); | |
112 | omap_crtc->timings = *timings; | |
113 | omap_crtc->full_update = true; | |
114 | } | |
115 | ||
116 | static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr, | |
117 | const struct dss_lcd_mgr_config *config) | |
118 | { | |
119 | struct omap_crtc *omap_crtc = container_of(mgr, struct omap_crtc, mgr); | |
120 | DBG("%s", omap_crtc->name); | |
121 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
122 | } | |
123 | ||
124 | static int omap_crtc_register_framedone_handler( | |
125 | struct omap_overlay_manager *mgr, | |
126 | void (*handler)(void *), void *data) | |
127 | { | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static void omap_crtc_unregister_framedone_handler( | |
132 | struct omap_overlay_manager *mgr, | |
133 | void (*handler)(void *), void *data) | |
134 | { | |
135 | } | |
136 | ||
137 | static const struct dss_mgr_ops mgr_ops = { | |
138 | .start_update = omap_crtc_start_update, | |
139 | .enable = omap_crtc_enable, | |
140 | .disable = omap_crtc_disable, | |
141 | .set_timings = omap_crtc_set_timings, | |
142 | .set_lcd_config = omap_crtc_set_lcd_config, | |
143 | .register_framedone_handler = omap_crtc_register_framedone_handler, | |
144 | .unregister_framedone_handler = omap_crtc_unregister_framedone_handler, | |
cd5351f4 RC |
145 | }; |
146 | ||
f5f9454c RC |
147 | /* |
148 | * CRTC funcs: | |
149 | */ | |
150 | ||
cd5351f4 RC |
151 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
152 | { | |
153 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
154 | |
155 | DBG("%s", omap_crtc->name); | |
156 | ||
157 | WARN_ON(omap_crtc->apply_irq.registered); | |
158 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); | |
159 | ||
bb5c2d9a | 160 | omap_crtc->plane->funcs->destroy(omap_crtc->plane); |
cd5351f4 | 161 | drm_crtc_cleanup(crtc); |
f5f9454c | 162 | |
cd5351f4 RC |
163 | kfree(omap_crtc); |
164 | } | |
165 | ||
166 | static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) | |
167 | { | |
bb5c2d9a | 168 | struct omap_drm_private *priv = crtc->dev->dev_private; |
cd5351f4 | 169 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f5f9454c | 170 | bool enabled = (mode == DRM_MODE_DPMS_ON); |
bb5c2d9a | 171 | int i; |
cd5351f4 | 172 | |
f5f9454c RC |
173 | DBG("%s: %d", omap_crtc->name, mode); |
174 | ||
175 | if (enabled != omap_crtc->enabled) { | |
176 | omap_crtc->enabled = enabled; | |
177 | omap_crtc->full_update = true; | |
178 | omap_crtc_apply(crtc, &omap_crtc->apply); | |
cd5351f4 | 179 | |
f5f9454c RC |
180 | /* also enable our private plane: */ |
181 | WARN_ON(omap_plane_dpms(omap_crtc->plane, mode)); | |
182 | ||
183 | /* and any attached overlay planes: */ | |
184 | for (i = 0; i < priv->num_planes; i++) { | |
185 | struct drm_plane *plane = priv->planes[i]; | |
186 | if (plane->crtc == crtc) | |
187 | WARN_ON(omap_plane_dpms(plane, mode)); | |
188 | } | |
cd5351f4 | 189 | } |
cd5351f4 RC |
190 | } |
191 | ||
192 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 193 | const struct drm_display_mode *mode, |
bb5c2d9a | 194 | struct drm_display_mode *adjusted_mode) |
cd5351f4 | 195 | { |
cd5351f4 RC |
196 | return true; |
197 | } | |
198 | ||
199 | static int omap_crtc_mode_set(struct drm_crtc *crtc, | |
bb5c2d9a RC |
200 | struct drm_display_mode *mode, |
201 | struct drm_display_mode *adjusted_mode, | |
202 | int x, int y, | |
203 | struct drm_framebuffer *old_fb) | |
cd5351f4 RC |
204 | { |
205 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
206 | ||
f5f9454c RC |
207 | mode = adjusted_mode; |
208 | ||
209 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
210 | omap_crtc->name, mode->base.id, mode->name, | |
211 | mode->vrefresh, mode->clock, | |
212 | mode->hdisplay, mode->hsync_start, | |
213 | mode->hsync_end, mode->htotal, | |
214 | mode->vdisplay, mode->vsync_start, | |
215 | mode->vsync_end, mode->vtotal, | |
216 | mode->type, mode->flags); | |
217 | ||
218 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
219 | omap_crtc->full_update = true; | |
220 | ||
221 | return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb, | |
bb5c2d9a RC |
222 | 0, 0, mode->hdisplay, mode->vdisplay, |
223 | x << 16, y << 16, | |
f5f9454c RC |
224 | mode->hdisplay << 16, mode->vdisplay << 16, |
225 | NULL, NULL); | |
cd5351f4 RC |
226 | } |
227 | ||
228 | static void omap_crtc_prepare(struct drm_crtc *crtc) | |
229 | { | |
230 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 231 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
232 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
233 | } | |
234 | ||
235 | static void omap_crtc_commit(struct drm_crtc *crtc) | |
236 | { | |
237 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 238 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
239 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
240 | } | |
241 | ||
242 | static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
bb5c2d9a | 243 | struct drm_framebuffer *old_fb) |
cd5351f4 RC |
244 | { |
245 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a RC |
246 | struct drm_plane *plane = omap_crtc->plane; |
247 | struct drm_display_mode *mode = &crtc->mode; | |
cd5351f4 | 248 | |
f5f9454c | 249 | return omap_plane_mode_set(plane, crtc, crtc->fb, |
bb5c2d9a RC |
250 | 0, 0, mode->hdisplay, mode->vdisplay, |
251 | x << 16, y << 16, | |
f5f9454c RC |
252 | mode->hdisplay << 16, mode->vdisplay << 16, |
253 | NULL, NULL); | |
cd5351f4 RC |
254 | } |
255 | ||
72d0c336 | 256 | static void vblank_cb(void *arg) |
cd5351f4 RC |
257 | { |
258 | struct drm_crtc *crtc = arg; | |
259 | struct drm_device *dev = crtc->dev; | |
260 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
cd5351f4 RC |
261 | unsigned long flags; |
262 | ||
f5f9454c RC |
263 | spin_lock_irqsave(&dev->event_lock, flags); |
264 | ||
265 | /* wakeup userspace */ | |
266 | if (omap_crtc->event) | |
267 | drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); | |
cd5351f4 RC |
268 | |
269 | omap_crtc->event = NULL; | |
f5f9454c | 270 | omap_crtc->old_fb = NULL; |
cd5351f4 | 271 | |
f5f9454c | 272 | spin_unlock_irqrestore(&dev->event_lock, flags); |
cd5351f4 RC |
273 | } |
274 | ||
f5f9454c | 275 | static void page_flip_worker(struct work_struct *work) |
72d0c336 | 276 | { |
f5f9454c RC |
277 | struct omap_crtc *omap_crtc = |
278 | container_of(work, struct omap_crtc, page_flip_work); | |
279 | struct drm_crtc *crtc = &omap_crtc->base; | |
f5f9454c | 280 | struct drm_display_mode *mode = &crtc->mode; |
119c0814 | 281 | struct drm_gem_object *bo; |
72d0c336 | 282 | |
16ef3dfe | 283 | mutex_lock(&crtc->mutex); |
f5f9454c RC |
284 | omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb, |
285 | 0, 0, mode->hdisplay, mode->vdisplay, | |
286 | crtc->x << 16, crtc->y << 16, | |
287 | mode->hdisplay << 16, mode->vdisplay << 16, | |
288 | vblank_cb, crtc); | |
16ef3dfe | 289 | mutex_unlock(&crtc->mutex); |
119c0814 RC |
290 | |
291 | bo = omap_framebuffer_bo(crtc->fb, 0); | |
292 | drm_gem_object_unreference_unlocked(bo); | |
72d0c336 RC |
293 | } |
294 | ||
f5f9454c RC |
295 | static void page_flip_cb(void *arg) |
296 | { | |
297 | struct drm_crtc *crtc = arg; | |
298 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
299 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
300 | ||
301 | /* avoid assumptions about what ctxt we are called from: */ | |
302 | queue_work(priv->wq, &omap_crtc->page_flip_work); | |
303 | } | |
304 | ||
cd5351f4 RC |
305 | static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, |
306 | struct drm_framebuffer *fb, | |
307 | struct drm_pending_vblank_event *event) | |
308 | { | |
309 | struct drm_device *dev = crtc->dev; | |
310 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
119c0814 | 311 | struct drm_gem_object *bo; |
cd5351f4 | 312 | |
f5f9454c RC |
313 | DBG("%d -> %d (event=%p)", crtc->fb ? crtc->fb->base.id : -1, |
314 | fb->base.id, event); | |
cd5351f4 | 315 | |
f5f9454c | 316 | if (omap_crtc->old_fb) { |
cd5351f4 RC |
317 | dev_err(dev->dev, "already a pending flip\n"); |
318 | return -EINVAL; | |
319 | } | |
320 | ||
cd5351f4 | 321 | omap_crtc->event = event; |
bb5c2d9a | 322 | crtc->fb = fb; |
cd5351f4 | 323 | |
119c0814 RC |
324 | /* |
325 | * Hold a reference temporarily until the crtc is updated | |
326 | * and takes the reference to the bo. This avoids it | |
327 | * getting freed from under us: | |
328 | */ | |
329 | bo = omap_framebuffer_bo(fb, 0); | |
330 | drm_gem_object_reference(bo); | |
331 | ||
332 | omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc); | |
cd5351f4 RC |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
3c810c61 RC |
337 | static int omap_crtc_set_property(struct drm_crtc *crtc, |
338 | struct drm_property *property, uint64_t val) | |
339 | { | |
340 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
1e0fdfc2 RC |
341 | struct omap_drm_private *priv = crtc->dev->dev_private; |
342 | ||
343 | if (property == priv->rotation_prop) { | |
344 | crtc->invert_dimensions = | |
345 | !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270))); | |
346 | } | |
347 | ||
3c810c61 RC |
348 | return omap_plane_set_property(omap_crtc->plane, property, val); |
349 | } | |
350 | ||
cd5351f4 | 351 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
cd5351f4 RC |
352 | .set_config = drm_crtc_helper_set_config, |
353 | .destroy = omap_crtc_destroy, | |
354 | .page_flip = omap_crtc_page_flip_locked, | |
3c810c61 | 355 | .set_property = omap_crtc_set_property, |
cd5351f4 RC |
356 | }; |
357 | ||
358 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
359 | .dpms = omap_crtc_dpms, | |
360 | .mode_fixup = omap_crtc_mode_fixup, | |
361 | .mode_set = omap_crtc_mode_set, | |
362 | .prepare = omap_crtc_prepare, | |
363 | .commit = omap_crtc_commit, | |
364 | .mode_set_base = omap_crtc_mode_set_base, | |
cd5351f4 RC |
365 | }; |
366 | ||
f5f9454c RC |
367 | const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
368 | { | |
369 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
370 | return &omap_crtc->timings; | |
371 | } | |
372 | ||
373 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
374 | { | |
375 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
376 | return omap_crtc->channel; | |
377 | } | |
378 | ||
379 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
380 | { | |
381 | struct omap_crtc *omap_crtc = | |
382 | container_of(irq, struct omap_crtc, error_irq); | |
383 | struct drm_crtc *crtc = &omap_crtc->base; | |
384 | DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus); | |
385 | /* avoid getting in a flood, unregister the irq until next vblank */ | |
386 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); | |
387 | } | |
388 | ||
389 | static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
390 | { | |
391 | struct omap_crtc *omap_crtc = | |
392 | container_of(irq, struct omap_crtc, apply_irq); | |
393 | struct drm_crtc *crtc = &omap_crtc->base; | |
394 | ||
395 | if (!omap_crtc->error_irq.registered) | |
396 | omap_irq_register(crtc->dev, &omap_crtc->error_irq); | |
397 | ||
398 | if (!dispc_mgr_go_busy(omap_crtc->channel)) { | |
399 | struct omap_drm_private *priv = | |
400 | crtc->dev->dev_private; | |
401 | DBG("%s: apply done", omap_crtc->name); | |
402 | omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq); | |
403 | queue_work(priv->wq, &omap_crtc->apply_work); | |
404 | } | |
405 | } | |
406 | ||
407 | static void apply_worker(struct work_struct *work) | |
408 | { | |
409 | struct omap_crtc *omap_crtc = | |
410 | container_of(work, struct omap_crtc, apply_work); | |
411 | struct drm_crtc *crtc = &omap_crtc->base; | |
412 | struct drm_device *dev = crtc->dev; | |
413 | struct omap_drm_apply *apply, *n; | |
414 | bool need_apply; | |
415 | ||
416 | /* | |
417 | * Synchronize everything on mode_config.mutex, to keep | |
418 | * the callbacks and list modification all serialized | |
419 | * with respect to modesetting ioctls from userspace. | |
420 | */ | |
16ef3dfe | 421 | mutex_lock(&crtc->mutex); |
f5f9454c RC |
422 | dispc_runtime_get(); |
423 | ||
424 | /* | |
425 | * If we are still pending a previous update, wait.. when the | |
426 | * pending update completes, we get kicked again. | |
427 | */ | |
428 | if (omap_crtc->apply_irq.registered) | |
429 | goto out; | |
430 | ||
431 | /* finish up previous apply's: */ | |
432 | list_for_each_entry_safe(apply, n, | |
433 | &omap_crtc->pending_applies, pending_node) { | |
434 | apply->post_apply(apply); | |
435 | list_del(&apply->pending_node); | |
436 | } | |
437 | ||
438 | need_apply = !list_empty(&omap_crtc->queued_applies); | |
439 | ||
440 | /* then handle the next round of of queued apply's: */ | |
441 | list_for_each_entry_safe(apply, n, | |
442 | &omap_crtc->queued_applies, queued_node) { | |
443 | apply->pre_apply(apply); | |
444 | list_del(&apply->queued_node); | |
445 | apply->queued = false; | |
446 | list_add_tail(&apply->pending_node, | |
447 | &omap_crtc->pending_applies); | |
448 | } | |
449 | ||
450 | if (need_apply) { | |
451 | enum omap_channel channel = omap_crtc->channel; | |
452 | ||
453 | DBG("%s: GO", omap_crtc->name); | |
454 | ||
455 | if (dispc_mgr_is_enabled(channel)) { | |
456 | omap_irq_register(dev, &omap_crtc->apply_irq); | |
457 | dispc_mgr_go(channel); | |
458 | } else { | |
459 | struct omap_drm_private *priv = dev->dev_private; | |
460 | queue_work(priv->wq, &omap_crtc->apply_work); | |
461 | } | |
462 | } | |
463 | ||
464 | out: | |
465 | dispc_runtime_put(); | |
16ef3dfe | 466 | mutex_unlock(&crtc->mutex); |
f5f9454c RC |
467 | } |
468 | ||
469 | int omap_crtc_apply(struct drm_crtc *crtc, | |
470 | struct omap_drm_apply *apply) | |
471 | { | |
472 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c | 473 | |
16ef3dfe | 474 | WARN_ON(!mutex_is_locked(&crtc->mutex)); |
f5f9454c RC |
475 | |
476 | /* no need to queue it again if it is already queued: */ | |
477 | if (apply->queued) | |
478 | return 0; | |
479 | ||
480 | apply->queued = true; | |
481 | list_add_tail(&apply->queued_node, &omap_crtc->queued_applies); | |
482 | ||
483 | /* | |
484 | * If there are no currently pending updates, then go ahead and | |
485 | * kick the worker immediately, otherwise it will run again when | |
486 | * the current update finishes. | |
487 | */ | |
488 | if (list_empty(&omap_crtc->pending_applies)) { | |
489 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
490 | queue_work(priv->wq, &omap_crtc->apply_work); | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
496 | /* called only from apply */ | |
497 | static void set_enabled(struct drm_crtc *crtc, bool enable) | |
498 | { | |
499 | struct drm_device *dev = crtc->dev; | |
500 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
501 | enum omap_channel channel = omap_crtc->channel; | |
502 | struct omap_irq_wait *wait = NULL; | |
503 | ||
504 | if (dispc_mgr_is_enabled(channel) == enable) | |
505 | return; | |
506 | ||
507 | /* ignore sync-lost irqs during enable/disable */ | |
508 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); | |
509 | ||
510 | if (dispc_mgr_get_framedone_irq(channel)) { | |
511 | if (!enable) { | |
512 | wait = omap_irq_wait_init(dev, | |
513 | dispc_mgr_get_framedone_irq(channel), 1); | |
514 | } | |
515 | } else { | |
516 | /* | |
517 | * When we disable digit output, we need to wait until fields | |
518 | * are done. Otherwise the DSS is still working, and turning | |
519 | * off the clocks prevents DSS from going to OFF mode. And when | |
520 | * enabling, we need to wait for the extra sync losts | |
521 | */ | |
522 | wait = omap_irq_wait_init(dev, | |
523 | dispc_mgr_get_vsync_irq(channel), 2); | |
524 | } | |
525 | ||
526 | dispc_mgr_enable(channel, enable); | |
527 | ||
528 | if (wait) { | |
529 | int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
530 | if (ret) { | |
531 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
532 | omap_crtc->name, enable ? "enable" : "disable"); | |
533 | } | |
534 | } | |
535 | ||
536 | omap_irq_register(crtc->dev, &omap_crtc->error_irq); | |
537 | } | |
538 | ||
539 | static void omap_crtc_pre_apply(struct omap_drm_apply *apply) | |
540 | { | |
541 | struct omap_crtc *omap_crtc = | |
542 | container_of(apply, struct omap_crtc, apply); | |
543 | struct drm_crtc *crtc = &omap_crtc->base; | |
544 | struct drm_encoder *encoder = NULL; | |
545 | ||
546 | DBG("%s: enabled=%d, full=%d", omap_crtc->name, | |
547 | omap_crtc->enabled, omap_crtc->full_update); | |
548 | ||
549 | if (omap_crtc->full_update) { | |
550 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
551 | int i; | |
552 | for (i = 0; i < priv->num_encoders; i++) { | |
553 | if (priv->encoders[i]->crtc == crtc) { | |
554 | encoder = priv->encoders[i]; | |
555 | break; | |
556 | } | |
557 | } | |
558 | } | |
559 | ||
560 | if (!omap_crtc->enabled) { | |
561 | set_enabled(&omap_crtc->base, false); | |
562 | if (encoder) | |
563 | omap_encoder_set_enabled(encoder, false); | |
564 | } else { | |
565 | if (encoder) { | |
566 | omap_encoder_set_enabled(encoder, false); | |
567 | omap_encoder_update(encoder, &omap_crtc->mgr, | |
568 | &omap_crtc->timings); | |
569 | omap_encoder_set_enabled(encoder, true); | |
570 | omap_crtc->full_update = false; | |
571 | } | |
572 | ||
573 | dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info); | |
574 | dispc_mgr_set_timings(omap_crtc->channel, | |
575 | &omap_crtc->timings); | |
576 | set_enabled(&omap_crtc->base, true); | |
577 | } | |
578 | ||
579 | omap_crtc->full_update = false; | |
580 | } | |
581 | ||
582 | static void omap_crtc_post_apply(struct omap_drm_apply *apply) | |
583 | { | |
584 | /* nothing needed for post-apply */ | |
585 | } | |
586 | ||
587 | static const char *channel_names[] = { | |
588 | [OMAP_DSS_CHANNEL_LCD] = "lcd", | |
589 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
590 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
591 | }; | |
592 | ||
cd5351f4 RC |
593 | /* initialize crtc */ |
594 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 595 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
596 | { |
597 | struct drm_crtc *crtc = NULL; | |
f5f9454c RC |
598 | struct omap_crtc *omap_crtc; |
599 | struct omap_overlay_manager_info *info; | |
600 | ||
601 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 602 | |
f5f9454c | 603 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 604 | if (!omap_crtc) |
cd5351f4 | 605 | goto fail; |
cd5351f4 | 606 | |
cd5351f4 | 607 | crtc = &omap_crtc->base; |
bb5c2d9a | 608 | |
f5f9454c RC |
609 | INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); |
610 | INIT_WORK(&omap_crtc->apply_work, apply_worker); | |
611 | ||
612 | INIT_LIST_HEAD(&omap_crtc->pending_applies); | |
613 | INIT_LIST_HEAD(&omap_crtc->queued_applies); | |
614 | ||
615 | omap_crtc->apply.pre_apply = omap_crtc_pre_apply; | |
616 | omap_crtc->apply.post_apply = omap_crtc_post_apply; | |
617 | ||
0d8f371f AT |
618 | omap_crtc->channel = channel; |
619 | omap_crtc->plane = plane; | |
620 | omap_crtc->plane->crtc = crtc; | |
621 | omap_crtc->name = channel_names[channel]; | |
622 | omap_crtc->pipe = id; | |
623 | ||
624 | omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); | |
f5f9454c RC |
625 | omap_crtc->apply_irq.irq = omap_crtc_apply_irq; |
626 | ||
627 | omap_crtc->error_irq.irqmask = | |
628 | dispc_mgr_get_sync_lost_irq(channel); | |
629 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
630 | omap_irq_register(dev, &omap_crtc->error_irq); | |
631 | ||
f5f9454c RC |
632 | /* temporary: */ |
633 | omap_crtc->mgr.id = channel; | |
634 | ||
635 | dss_install_mgr_ops(&mgr_ops); | |
636 | ||
637 | /* TODO: fix hard-coded setup.. add properties! */ | |
638 | info = &omap_crtc->info; | |
639 | info->default_color = 0x00000000; | |
640 | info->trans_key = 0x00000000; | |
641 | info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
642 | info->trans_enabled = false; | |
bb5c2d9a | 643 | |
cd5351f4 RC |
644 | drm_crtc_init(dev, crtc, &omap_crtc_funcs); |
645 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); | |
646 | ||
3c810c61 RC |
647 | omap_plane_install_properties(omap_crtc->plane, &crtc->base); |
648 | ||
cd5351f4 RC |
649 | return crtc; |
650 | ||
651 | fail: | |
d21a9d3b | 652 | if (crtc) |
65b0bd06 | 653 | omap_crtc_destroy(crtc); |
d21a9d3b | 654 | |
cd5351f4 RC |
655 | return NULL; |
656 | } |