Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
69a12263 LP |
20 | #include <drm/drm_atomic.h> |
21 | #include <drm/drm_atomic_helper.h> | |
2d278f54 LP |
22 | #include <drm/drm_crtc.h> |
23 | #include <drm/drm_crtc_helper.h> | |
b9ed9f0e | 24 | #include <drm/drm_mode.h> |
3cb9ae4f | 25 | #include <drm/drm_plane_helper.h> |
2d278f54 LP |
26 | |
27 | #include "omap_drv.h" | |
cd5351f4 RC |
28 | |
29 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
30 | ||
31 | struct omap_crtc { | |
32 | struct drm_crtc base; | |
f5f9454c | 33 | |
bb5c2d9a | 34 | const char *name; |
f5f9454c | 35 | enum omap_channel channel; |
f5f9454c | 36 | |
f5f9454c | 37 | struct omap_video_timings timings; |
f5f9454c | 38 | |
a42133a7 | 39 | struct omap_drm_irq vblank_irq; |
f5f9454c RC |
40 | struct omap_drm_irq error_irq; |
41 | ||
a36af73f | 42 | bool ignore_digit_sync_lost; |
5f741b39 TV |
43 | |
44 | bool pending; | |
45 | wait_queue_head_t pending_wait; | |
f5f9454c RC |
46 | }; |
47 | ||
971fb3e5 LP |
48 | /* ----------------------------------------------------------------------------- |
49 | * Helper Functions | |
50 | */ | |
51 | ||
0d8f371f AT |
52 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
53 | { | |
54 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
55 | ||
56 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
57 | } | |
58 | ||
4029755e | 59 | struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
971fb3e5 LP |
60 | { |
61 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
62 | return &omap_crtc->timings; | |
63 | } | |
64 | ||
65 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
66 | { | |
67 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
68 | return omap_crtc->channel; | |
69 | } | |
70 | ||
5f741b39 TV |
71 | int omap_crtc_wait_pending(struct drm_crtc *crtc) |
72 | { | |
73 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
74 | ||
61f3c40b TV |
75 | /* |
76 | * Timeout is set to a "sufficiently" high value, which should cover | |
77 | * a single frame refresh even on slower displays. | |
78 | */ | |
5f741b39 TV |
79 | return wait_event_timeout(omap_crtc->pending_wait, |
80 | !omap_crtc->pending, | |
61f3c40b | 81 | msecs_to_jiffies(250)); |
5f741b39 TV |
82 | } |
83 | ||
971fb3e5 LP |
84 | /* ----------------------------------------------------------------------------- |
85 | * DSS Manager Functions | |
86 | */ | |
87 | ||
f5f9454c RC |
88 | /* |
89 | * Manager-ops, callbacks from output when they need to configure | |
90 | * the upstream part of the video pipe. | |
91 | * | |
92 | * Most of these we can ignore until we add support for command-mode | |
93 | * panels.. for video-mode the crtc-helpers already do an adequate | |
94 | * job of sequencing the setup of the video pipe in the proper order | |
95 | */ | |
96 | ||
04b1fc02 TV |
97 | /* ovl-mgr-id -> crtc */ |
98 | static struct omap_crtc *omap_crtcs[8]; | |
3a924138 | 99 | static struct omap_dss_device *omap_crtc_output[8]; |
04b1fc02 | 100 | |
f5f9454c | 101 | /* we can probably ignore these until we support command-mode panels: */ |
4343f0f8 | 102 | static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 103 | struct omap_dss_device *dst) |
a7e71e7f | 104 | { |
3a924138 | 105 | if (omap_crtc_output[mgr->id]) |
a7e71e7f TV |
106 | return -EINVAL; |
107 | ||
7b9cb5ee | 108 | if ((dispc_mgr_get_supported_outputs(mgr->id) & dst->id) == 0) |
a7e71e7f TV |
109 | return -EINVAL; |
110 | ||
3a924138 TV |
111 | omap_crtc_output[mgr->id] = dst; |
112 | ||
a7e71e7f TV |
113 | dst->manager = mgr; |
114 | mgr->output = dst; | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
4343f0f8 | 119 | static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 120 | struct omap_dss_device *dst) |
a7e71e7f | 121 | { |
3a924138 TV |
122 | omap_crtc_output[mgr->id] = NULL; |
123 | ||
a7e71e7f TV |
124 | mgr->output->manager = NULL; |
125 | mgr->output = NULL; | |
126 | } | |
127 | ||
4343f0f8 | 128 | static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr) |
f5f9454c RC |
129 | { |
130 | } | |
131 | ||
4029755e | 132 | /* Called only from the encoder enable/disable and suspend/resume handlers. */ |
8472b570 LP |
133 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) |
134 | { | |
135 | struct drm_device *dev = crtc->dev; | |
136 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
137 | enum omap_channel channel = omap_crtc->channel; | |
138 | struct omap_irq_wait *wait; | |
139 | u32 framedone_irq, vsync_irq; | |
140 | int ret; | |
141 | ||
3a924138 | 142 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { |
4e4b53ce TV |
143 | dispc_mgr_enable(channel, enable); |
144 | return; | |
145 | } | |
146 | ||
8472b570 LP |
147 | if (dispc_mgr_is_enabled(channel) == enable) |
148 | return; | |
149 | ||
ef422283 TV |
150 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
151 | /* | |
152 | * Digit output produces some sync lost interrupts during the | |
153 | * first frame when enabling, so we need to ignore those. | |
154 | */ | |
155 | omap_crtc->ignore_digit_sync_lost = true; | |
156 | } | |
8472b570 LP |
157 | |
158 | framedone_irq = dispc_mgr_get_framedone_irq(channel); | |
159 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | |
160 | ||
161 | if (enable) { | |
162 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
163 | } else { | |
164 | /* | |
165 | * When we disable the digit output, we need to wait for | |
166 | * FRAMEDONE to know that DISPC has finished with the output. | |
167 | * | |
168 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
169 | * that case we need to use vsync interrupt, and wait for both | |
170 | * even and odd frames. | |
171 | */ | |
172 | ||
173 | if (framedone_irq) | |
174 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
175 | else | |
176 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
177 | } | |
178 | ||
179 | dispc_mgr_enable(channel, enable); | |
180 | ||
181 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
182 | if (ret) { | |
183 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
184 | omap_crtc->name, enable ? "enable" : "disable"); | |
185 | } | |
186 | ||
ef422283 TV |
187 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
188 | omap_crtc->ignore_digit_sync_lost = false; | |
189 | /* make sure the irq handler sees the value above */ | |
190 | mb(); | |
191 | } | |
8472b570 LP |
192 | } |
193 | ||
506096a1 | 194 | |
4343f0f8 | 195 | static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr) |
f5f9454c | 196 | { |
506096a1 | 197 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
dee8260d | 198 | struct omap_overlay_manager_info info; |
506096a1 | 199 | |
dee8260d LP |
200 | memset(&info, 0, sizeof(info)); |
201 | info.default_color = 0x00000000; | |
202 | info.trans_key = 0x00000000; | |
203 | info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
204 | info.trans_enabled = false; | |
205 | ||
206 | dispc_mgr_setup(omap_crtc->channel, &info); | |
506096a1 TV |
207 | dispc_mgr_set_timings(omap_crtc->channel, |
208 | &omap_crtc->timings); | |
8472b570 | 209 | omap_crtc_set_enabled(&omap_crtc->base, true); |
506096a1 | 210 | |
f5f9454c RC |
211 | return 0; |
212 | } | |
213 | ||
4343f0f8 | 214 | static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr) |
f5f9454c | 215 | { |
506096a1 TV |
216 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
217 | ||
8472b570 | 218 | omap_crtc_set_enabled(&omap_crtc->base, false); |
f5f9454c RC |
219 | } |
220 | ||
4343f0f8 | 221 | static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr, |
f5f9454c RC |
222 | const struct omap_video_timings *timings) |
223 | { | |
04b1fc02 | 224 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
225 | DBG("%s", omap_crtc->name); |
226 | omap_crtc->timings = *timings; | |
f5f9454c RC |
227 | } |
228 | ||
4343f0f8 | 229 | static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr, |
f5f9454c RC |
230 | const struct dss_lcd_mgr_config *config) |
231 | { | |
04b1fc02 | 232 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
233 | DBG("%s", omap_crtc->name); |
234 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
235 | } | |
236 | ||
4343f0f8 | 237 | static int omap_crtc_dss_register_framedone( |
f5f9454c RC |
238 | struct omap_overlay_manager *mgr, |
239 | void (*handler)(void *), void *data) | |
240 | { | |
241 | return 0; | |
242 | } | |
243 | ||
4343f0f8 | 244 | static void omap_crtc_dss_unregister_framedone( |
f5f9454c RC |
245 | struct omap_overlay_manager *mgr, |
246 | void (*handler)(void *), void *data) | |
247 | { | |
248 | } | |
249 | ||
250 | static const struct dss_mgr_ops mgr_ops = { | |
4343f0f8 LP |
251 | .connect = omap_crtc_dss_connect, |
252 | .disconnect = omap_crtc_dss_disconnect, | |
253 | .start_update = omap_crtc_dss_start_update, | |
254 | .enable = omap_crtc_dss_enable, | |
255 | .disable = omap_crtc_dss_disable, | |
256 | .set_timings = omap_crtc_dss_set_timings, | |
257 | .set_lcd_config = omap_crtc_dss_set_lcd_config, | |
258 | .register_framedone_handler = omap_crtc_dss_register_framedone, | |
259 | .unregister_framedone_handler = omap_crtc_dss_unregister_framedone, | |
cd5351f4 RC |
260 | }; |
261 | ||
971fb3e5 | 262 | /* ----------------------------------------------------------------------------- |
1d5e5ea1 | 263 | * Setup, Flush and Page Flip |
971fb3e5 LP |
264 | */ |
265 | ||
fa16d262 | 266 | static void omap_crtc_complete_page_flip(struct drm_crtc *crtc) |
15d02e92 | 267 | { |
fa16d262 | 268 | struct drm_pending_vblank_event *event; |
15d02e92 | 269 | struct drm_device *dev = crtc->dev; |
fa16d262 | 270 | unsigned long flags; |
15d02e92 | 271 | |
5f741b39 | 272 | event = crtc->state->event; |
c397cfd4 | 273 | |
5f741b39 TV |
274 | if (!event) |
275 | return; | |
c397cfd4 LP |
276 | |
277 | spin_lock_irqsave(&dev->event_lock, flags); | |
c397cfd4 | 278 | |
5f741b39 | 279 | list_del(&event->base.link); |
c397cfd4 | 280 | |
5f741b39 TV |
281 | /* |
282 | * Queue the event for delivery if it's still linked to a file | |
283 | * handle, otherwise just destroy it. | |
284 | */ | |
285 | if (event->base.file_priv) | |
286 | drm_crtc_send_vblank_event(crtc, event); | |
287 | else | |
288 | event->base.destroy(&event->base); | |
c397cfd4 | 289 | |
5f741b39 | 290 | spin_unlock_irqrestore(&dev->event_lock, flags); |
15d02e92 LP |
291 | } |
292 | ||
971fb3e5 LP |
293 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
294 | { | |
295 | struct omap_crtc *omap_crtc = | |
296 | container_of(irq, struct omap_crtc, error_irq); | |
a36af73f TV |
297 | |
298 | if (omap_crtc->ignore_digit_sync_lost) { | |
299 | irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
300 | if (!irqstatus) | |
301 | return; | |
302 | } | |
303 | ||
3b143fc8 | 304 | DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); |
971fb3e5 LP |
305 | } |
306 | ||
a42133a7 | 307 | static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
971fb3e5 LP |
308 | { |
309 | struct omap_crtc *omap_crtc = | |
a42133a7 LP |
310 | container_of(irq, struct omap_crtc, vblank_irq); |
311 | struct drm_device *dev = omap_crtc->base.dev; | |
971fb3e5 | 312 | |
a42133a7 LP |
313 | if (dispc_mgr_go_busy(omap_crtc->channel)) |
314 | return; | |
315 | ||
316 | DBG("%s: apply done", omap_crtc->name); | |
5f741b39 | 317 | |
a42133a7 LP |
318 | __omap_irq_unregister(dev, &omap_crtc->vblank_irq); |
319 | ||
5f741b39 TV |
320 | rmb(); |
321 | WARN_ON(!omap_crtc->pending); | |
322 | omap_crtc->pending = false; | |
323 | wmb(); | |
324 | ||
325 | /* wake up userspace */ | |
fa16d262 | 326 | omap_crtc_complete_page_flip(&omap_crtc->base); |
a42133a7 | 327 | |
5f741b39 TV |
328 | /* wake up omap_atomic_complete */ |
329 | wake_up(&omap_crtc->pending_wait); | |
971fb3e5 LP |
330 | } |
331 | ||
971fb3e5 LP |
332 | /* ----------------------------------------------------------------------------- |
333 | * CRTC Functions | |
f5f9454c RC |
334 | */ |
335 | ||
cd5351f4 RC |
336 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
337 | { | |
338 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
339 | |
340 | DBG("%s", omap_crtc->name); | |
341 | ||
a42133a7 | 342 | WARN_ON(omap_crtc->vblank_irq.registered); |
f5f9454c RC |
343 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); |
344 | ||
cd5351f4 | 345 | drm_crtc_cleanup(crtc); |
f5f9454c | 346 | |
cd5351f4 RC |
347 | kfree(omap_crtc); |
348 | } | |
349 | ||
f1d57fb5 LP |
350 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, |
351 | const struct drm_display_mode *mode, | |
352 | struct drm_display_mode *adjusted_mode) | |
353 | { | |
354 | return true; | |
355 | } | |
356 | ||
357 | static void omap_crtc_enable(struct drm_crtc *crtc) | |
cd5351f4 RC |
358 | { |
359 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
360 | ||
f1d57fb5 | 361 | DBG("%s", omap_crtc->name); |
f5f9454c | 362 | |
5f741b39 TV |
363 | rmb(); |
364 | WARN_ON(omap_crtc->pending); | |
365 | omap_crtc->pending = true; | |
366 | wmb(); | |
367 | ||
368 | omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); | |
369 | ||
f1d57fb5 | 370 | drm_crtc_vblank_on(crtc); |
cd5351f4 RC |
371 | } |
372 | ||
f1d57fb5 | 373 | static void omap_crtc_disable(struct drm_crtc *crtc) |
cd5351f4 | 374 | { |
f1d57fb5 | 375 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f1d57fb5 LP |
376 | |
377 | DBG("%s", omap_crtc->name); | |
378 | ||
f1d57fb5 | 379 | drm_crtc_vblank_off(crtc); |
cd5351f4 RC |
380 | } |
381 | ||
f7a73b65 | 382 | static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) |
cd5351f4 RC |
383 | { |
384 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f7a73b65 | 385 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
f5f9454c RC |
386 | |
387 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
f7a73b65 LP |
388 | omap_crtc->name, mode->base.id, mode->name, |
389 | mode->vrefresh, mode->clock, | |
390 | mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, | |
391 | mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, | |
392 | mode->type, mode->flags); | |
f5f9454c RC |
393 | |
394 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
cd5351f4 RC |
395 | } |
396 | ||
c201d00f DV |
397 | static void omap_crtc_atomic_begin(struct drm_crtc *crtc, |
398 | struct drm_crtc_state *old_crtc_state) | |
de8e4100 | 399 | { |
fa16d262 | 400 | } |
cd5351f4 | 401 | |
c201d00f DV |
402 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc, |
403 | struct drm_crtc_state *old_crtc_state) | |
fa16d262 | 404 | { |
6646dfd0 TV |
405 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
406 | ||
407 | WARN_ON(omap_crtc->vblank_irq.registered); | |
408 | ||
409 | if (dispc_mgr_is_enabled(omap_crtc->channel)) { | |
5f741b39 | 410 | |
6646dfd0 TV |
411 | DBG("%s: GO", omap_crtc->name); |
412 | ||
5f741b39 TV |
413 | rmb(); |
414 | WARN_ON(omap_crtc->pending); | |
415 | omap_crtc->pending = true; | |
416 | wmb(); | |
417 | ||
6646dfd0 TV |
418 | dispc_mgr_go(omap_crtc->channel); |
419 | omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); | |
6646dfd0 | 420 | } |
cd5351f4 RC |
421 | } |
422 | ||
6bdad6cf TV |
423 | static bool omap_crtc_is_plane_prop(struct drm_device *dev, |
424 | struct drm_property *property) | |
425 | { | |
426 | struct omap_drm_private *priv = dev->dev_private; | |
427 | ||
428 | return property == priv->zorder_prop || | |
429 | property == dev->mode_config.rotation_property; | |
430 | } | |
431 | ||
afc34932 LP |
432 | static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, |
433 | struct drm_crtc_state *state, | |
434 | struct drm_property *property, | |
435 | uint64_t val) | |
3c810c61 | 436 | { |
6bdad6cf | 437 | struct drm_device *dev = crtc->dev; |
afc34932 | 438 | |
6bdad6cf TV |
439 | if (omap_crtc_is_plane_prop(dev, property)) { |
440 | struct drm_plane_state *plane_state; | |
441 | struct drm_plane *plane = crtc->primary; | |
442 | ||
443 | /* | |
444 | * Delegate property set to the primary plane. Get the plane | |
445 | * state and set the property directly. | |
446 | */ | |
afc34932 | 447 | |
6bdad6cf TV |
448 | plane_state = drm_atomic_get_plane_state(state->state, plane); |
449 | if (IS_ERR(plane_state)) | |
450 | return PTR_ERR(plane_state); | |
afc34932 | 451 | |
6bdad6cf TV |
452 | return drm_atomic_plane_set_property(plane, plane_state, |
453 | property, val); | |
454 | } | |
455 | ||
456 | return -EINVAL; | |
afc34932 | 457 | } |
1e0fdfc2 | 458 | |
afc34932 LP |
459 | static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, |
460 | const struct drm_crtc_state *state, | |
461 | struct drm_property *property, | |
462 | uint64_t *val) | |
463 | { | |
6bdad6cf TV |
464 | struct drm_device *dev = crtc->dev; |
465 | ||
466 | if (omap_crtc_is_plane_prop(dev, property)) { | |
467 | /* | |
468 | * Delegate property get to the primary plane. The | |
469 | * drm_atomic_plane_get_property() function isn't exported, but | |
470 | * can be called through drm_object_property_get_value() as that | |
471 | * will call drm_atomic_get_property() for atomic drivers. | |
472 | */ | |
473 | return drm_object_property_get_value(&crtc->primary->base, | |
474 | property, val); | |
475 | } | |
476 | ||
477 | return -EINVAL; | |
3c810c61 RC |
478 | } |
479 | ||
cd5351f4 | 480 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
69a12263 | 481 | .reset = drm_atomic_helper_crtc_reset, |
9416c9df | 482 | .set_config = drm_atomic_helper_set_config, |
cd5351f4 | 483 | .destroy = omap_crtc_destroy, |
fa16d262 | 484 | .page_flip = drm_atomic_helper_page_flip, |
afc34932 | 485 | .set_property = drm_atomic_helper_crtc_set_property, |
69a12263 LP |
486 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
487 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
afc34932 LP |
488 | .atomic_set_property = omap_crtc_atomic_set_property, |
489 | .atomic_get_property = omap_crtc_atomic_get_property, | |
cd5351f4 RC |
490 | }; |
491 | ||
492 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
cd5351f4 | 493 | .mode_fixup = omap_crtc_mode_fixup, |
f7a73b65 | 494 | .mode_set_nofb = omap_crtc_mode_set_nofb, |
f1d57fb5 LP |
495 | .disable = omap_crtc_disable, |
496 | .enable = omap_crtc_enable, | |
de8e4100 LP |
497 | .atomic_begin = omap_crtc_atomic_begin, |
498 | .atomic_flush = omap_crtc_atomic_flush, | |
cd5351f4 RC |
499 | }; |
500 | ||
971fb3e5 LP |
501 | /* ----------------------------------------------------------------------------- |
502 | * Init and Cleanup | |
503 | */ | |
e2f8fd74 | 504 | |
f5f9454c | 505 | static const char *channel_names[] = { |
222025e4 LP |
506 | [OMAP_DSS_CHANNEL_LCD] = "lcd", |
507 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
508 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
509 | [OMAP_DSS_CHANNEL_LCD3] = "lcd3", | |
f5f9454c RC |
510 | }; |
511 | ||
04b1fc02 TV |
512 | void omap_crtc_pre_init(void) |
513 | { | |
514 | dss_install_mgr_ops(&mgr_ops); | |
515 | } | |
516 | ||
3a01ab25 AT |
517 | void omap_crtc_pre_uninit(void) |
518 | { | |
519 | dss_uninstall_mgr_ops(); | |
520 | } | |
521 | ||
cd5351f4 RC |
522 | /* initialize crtc */ |
523 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 524 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
525 | { |
526 | struct drm_crtc *crtc = NULL; | |
f5f9454c | 527 | struct omap_crtc *omap_crtc; |
ef6b0e02 | 528 | int ret; |
f5f9454c RC |
529 | |
530 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 531 | |
f5f9454c | 532 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 533 | if (!omap_crtc) |
ef6b0e02 | 534 | return NULL; |
cd5351f4 | 535 | |
cd5351f4 | 536 | crtc = &omap_crtc->base; |
bb5c2d9a | 537 | |
5f741b39 | 538 | init_waitqueue_head(&omap_crtc->pending_wait); |
f5f9454c | 539 | |
0d8f371f | 540 | omap_crtc->channel = channel; |
0d8f371f | 541 | omap_crtc->name = channel_names[channel]; |
0d8f371f | 542 | |
a42133a7 LP |
543 | omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc); |
544 | omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq; | |
f5f9454c RC |
545 | |
546 | omap_crtc->error_irq.irqmask = | |
547 | dispc_mgr_get_sync_lost_irq(channel); | |
548 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
549 | omap_irq_register(dev, &omap_crtc->error_irq); | |
550 | ||
ef6b0e02 | 551 | ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, |
f9882876 | 552 | &omap_crtc_funcs, NULL); |
ef6b0e02 LP |
553 | if (ret < 0) { |
554 | kfree(omap_crtc); | |
555 | return NULL; | |
556 | } | |
557 | ||
cd5351f4 RC |
558 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); |
559 | ||
ef6b0e02 | 560 | omap_plane_install_properties(crtc->primary, &crtc->base); |
3c810c61 | 561 | |
04b1fc02 TV |
562 | omap_crtcs[channel] = omap_crtc; |
563 | ||
cd5351f4 | 564 | return crtc; |
cd5351f4 | 565 | } |