Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
b9ed9f0e | 22 | #include <drm/drm_mode.h> |
3cb9ae4f | 23 | #include <drm/drm_plane_helper.h> |
cd5351f4 RC |
24 | #include "drm_crtc.h" |
25 | #include "drm_crtc_helper.h" | |
26 | ||
27 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
28 | ||
29 | struct omap_crtc { | |
30 | struct drm_crtc base; | |
f5f9454c | 31 | |
bb5c2d9a | 32 | const char *name; |
f5f9454c RC |
33 | int pipe; |
34 | enum omap_channel channel; | |
35 | struct omap_overlay_manager_info info; | |
c7aef12f | 36 | struct drm_encoder *current_encoder; |
f5f9454c RC |
37 | |
38 | /* | |
39 | * Temporary: eventually this will go away, but it is needed | |
40 | * for now to keep the output's happy. (They only need | |
41 | * mgr->id.) Eventually this will be replaced w/ something | |
42 | * more common-panel-framework-y | |
43 | */ | |
04b1fc02 | 44 | struct omap_overlay_manager *mgr; |
f5f9454c RC |
45 | |
46 | struct omap_video_timings timings; | |
47 | bool enabled; | |
f5f9454c RC |
48 | |
49 | struct omap_drm_apply apply; | |
50 | ||
51 | struct omap_drm_irq apply_irq; | |
52 | struct omap_drm_irq error_irq; | |
53 | ||
54 | /* list of in-progress apply's: */ | |
55 | struct list_head pending_applies; | |
56 | ||
57 | /* list of queued apply's: */ | |
58 | struct list_head queued_applies; | |
59 | ||
60 | /* for handling queued and in-progress applies: */ | |
61 | struct work_struct apply_work; | |
cd5351f4 | 62 | |
bb5c2d9a | 63 | /* if there is a pending flip, these will be non-null: */ |
cd5351f4 | 64 | struct drm_pending_vblank_event *event; |
bb5c2d9a | 65 | struct drm_framebuffer *old_fb; |
f5f9454c RC |
66 | |
67 | /* for handling page flips without caring about what | |
68 | * the callback is called from. Possibly we should just | |
69 | * make omap_gem always call the cb from the worker so | |
70 | * we don't have to care about this.. | |
71 | * | |
72 | * XXX maybe fold into apply_work?? | |
73 | */ | |
74 | struct work_struct page_flip_work; | |
a36af73f TV |
75 | |
76 | bool ignore_digit_sync_lost; | |
f5f9454c RC |
77 | }; |
78 | ||
971fb3e5 LP |
79 | /* ----------------------------------------------------------------------------- |
80 | * Helper Functions | |
81 | */ | |
82 | ||
0d8f371f AT |
83 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
84 | { | |
85 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
86 | ||
87 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
88 | } | |
89 | ||
971fb3e5 LP |
90 | const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
91 | { | |
92 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
93 | return &omap_crtc->timings; | |
94 | } | |
95 | ||
96 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
97 | { | |
98 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
99 | return omap_crtc->channel; | |
100 | } | |
101 | ||
102 | /* ----------------------------------------------------------------------------- | |
103 | * DSS Manager Functions | |
104 | */ | |
105 | ||
f5f9454c RC |
106 | /* |
107 | * Manager-ops, callbacks from output when they need to configure | |
108 | * the upstream part of the video pipe. | |
109 | * | |
110 | * Most of these we can ignore until we add support for command-mode | |
111 | * panels.. for video-mode the crtc-helpers already do an adequate | |
112 | * job of sequencing the setup of the video pipe in the proper order | |
113 | */ | |
114 | ||
04b1fc02 TV |
115 | /* ovl-mgr-id -> crtc */ |
116 | static struct omap_crtc *omap_crtcs[8]; | |
117 | ||
f5f9454c | 118 | /* we can probably ignore these until we support command-mode panels: */ |
a7e71e7f | 119 | static int omap_crtc_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 120 | struct omap_dss_device *dst) |
a7e71e7f TV |
121 | { |
122 | if (mgr->output) | |
123 | return -EINVAL; | |
124 | ||
125 | if ((mgr->supported_outputs & dst->id) == 0) | |
126 | return -EINVAL; | |
127 | ||
128 | dst->manager = mgr; | |
129 | mgr->output = dst; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static void omap_crtc_disconnect(struct omap_overlay_manager *mgr, | |
1f68d9c4 | 135 | struct omap_dss_device *dst) |
a7e71e7f TV |
136 | { |
137 | mgr->output->manager = NULL; | |
138 | mgr->output = NULL; | |
139 | } | |
140 | ||
f5f9454c RC |
141 | static void omap_crtc_start_update(struct omap_overlay_manager *mgr) |
142 | { | |
143 | } | |
144 | ||
8472b570 LP |
145 | /* Called only from CRTC pre_apply and suspend/resume handlers. */ |
146 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |
147 | { | |
148 | struct drm_device *dev = crtc->dev; | |
149 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
150 | enum omap_channel channel = omap_crtc->channel; | |
151 | struct omap_irq_wait *wait; | |
152 | u32 framedone_irq, vsync_irq; | |
153 | int ret; | |
154 | ||
155 | if (dispc_mgr_is_enabled(channel) == enable) | |
156 | return; | |
157 | ||
158 | /* | |
159 | * Digit output produces some sync lost interrupts during the first | |
160 | * frame when enabling, so we need to ignore those. | |
161 | */ | |
a36af73f | 162 | omap_crtc->ignore_digit_sync_lost = true; |
8472b570 LP |
163 | |
164 | framedone_irq = dispc_mgr_get_framedone_irq(channel); | |
165 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | |
166 | ||
167 | if (enable) { | |
168 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
169 | } else { | |
170 | /* | |
171 | * When we disable the digit output, we need to wait for | |
172 | * FRAMEDONE to know that DISPC has finished with the output. | |
173 | * | |
174 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
175 | * that case we need to use vsync interrupt, and wait for both | |
176 | * even and odd frames. | |
177 | */ | |
178 | ||
179 | if (framedone_irq) | |
180 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
181 | else | |
182 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
183 | } | |
184 | ||
185 | dispc_mgr_enable(channel, enable); | |
186 | ||
187 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
188 | if (ret) { | |
189 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
190 | omap_crtc->name, enable ? "enable" : "disable"); | |
191 | } | |
192 | ||
a36af73f TV |
193 | omap_crtc->ignore_digit_sync_lost = false; |
194 | /* make sure the irq handler sees the value above */ | |
195 | mb(); | |
8472b570 LP |
196 | } |
197 | ||
506096a1 | 198 | |
f5f9454c RC |
199 | static int omap_crtc_enable(struct omap_overlay_manager *mgr) |
200 | { | |
506096a1 TV |
201 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
202 | ||
203 | dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info); | |
204 | dispc_mgr_set_timings(omap_crtc->channel, | |
205 | &omap_crtc->timings); | |
8472b570 | 206 | omap_crtc_set_enabled(&omap_crtc->base, true); |
506096a1 | 207 | |
f5f9454c RC |
208 | return 0; |
209 | } | |
210 | ||
211 | static void omap_crtc_disable(struct omap_overlay_manager *mgr) | |
212 | { | |
506096a1 TV |
213 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
214 | ||
8472b570 | 215 | omap_crtc_set_enabled(&omap_crtc->base, false); |
f5f9454c RC |
216 | } |
217 | ||
218 | static void omap_crtc_set_timings(struct omap_overlay_manager *mgr, | |
219 | const struct omap_video_timings *timings) | |
220 | { | |
04b1fc02 | 221 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
222 | DBG("%s", omap_crtc->name); |
223 | omap_crtc->timings = *timings; | |
f5f9454c RC |
224 | } |
225 | ||
226 | static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr, | |
227 | const struct dss_lcd_mgr_config *config) | |
228 | { | |
04b1fc02 | 229 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
230 | DBG("%s", omap_crtc->name); |
231 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
232 | } | |
233 | ||
234 | static int omap_crtc_register_framedone_handler( | |
235 | struct omap_overlay_manager *mgr, | |
236 | void (*handler)(void *), void *data) | |
237 | { | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static void omap_crtc_unregister_framedone_handler( | |
242 | struct omap_overlay_manager *mgr, | |
243 | void (*handler)(void *), void *data) | |
244 | { | |
245 | } | |
246 | ||
247 | static const struct dss_mgr_ops mgr_ops = { | |
222025e4 LP |
248 | .connect = omap_crtc_connect, |
249 | .disconnect = omap_crtc_disconnect, | |
250 | .start_update = omap_crtc_start_update, | |
251 | .enable = omap_crtc_enable, | |
252 | .disable = omap_crtc_disable, | |
253 | .set_timings = omap_crtc_set_timings, | |
254 | .set_lcd_config = omap_crtc_set_lcd_config, | |
255 | .register_framedone_handler = omap_crtc_register_framedone_handler, | |
256 | .unregister_framedone_handler = omap_crtc_unregister_framedone_handler, | |
cd5351f4 RC |
257 | }; |
258 | ||
971fb3e5 LP |
259 | /* ----------------------------------------------------------------------------- |
260 | * Apply Logic | |
261 | */ | |
262 | ||
263 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
264 | { | |
265 | struct omap_crtc *omap_crtc = | |
266 | container_of(irq, struct omap_crtc, error_irq); | |
a36af73f TV |
267 | |
268 | if (omap_crtc->ignore_digit_sync_lost) { | |
269 | irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
270 | if (!irqstatus) | |
271 | return; | |
272 | } | |
273 | ||
3b143fc8 | 274 | DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); |
971fb3e5 LP |
275 | } |
276 | ||
277 | static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
278 | { | |
279 | struct omap_crtc *omap_crtc = | |
280 | container_of(irq, struct omap_crtc, apply_irq); | |
281 | struct drm_crtc *crtc = &omap_crtc->base; | |
282 | ||
971fb3e5 LP |
283 | if (!dispc_mgr_go_busy(omap_crtc->channel)) { |
284 | struct omap_drm_private *priv = | |
285 | crtc->dev->dev_private; | |
286 | DBG("%s: apply done", omap_crtc->name); | |
287 | __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq); | |
288 | queue_work(priv->wq, &omap_crtc->apply_work); | |
289 | } | |
290 | } | |
291 | ||
292 | static void apply_worker(struct work_struct *work) | |
293 | { | |
294 | struct omap_crtc *omap_crtc = | |
295 | container_of(work, struct omap_crtc, apply_work); | |
296 | struct drm_crtc *crtc = &omap_crtc->base; | |
297 | struct drm_device *dev = crtc->dev; | |
298 | struct omap_drm_apply *apply, *n; | |
299 | bool need_apply; | |
300 | ||
301 | /* | |
302 | * Synchronize everything on mode_config.mutex, to keep | |
303 | * the callbacks and list modification all serialized | |
304 | * with respect to modesetting ioctls from userspace. | |
305 | */ | |
306 | drm_modeset_lock(&crtc->mutex, NULL); | |
307 | dispc_runtime_get(); | |
308 | ||
309 | /* | |
310 | * If we are still pending a previous update, wait.. when the | |
311 | * pending update completes, we get kicked again. | |
312 | */ | |
313 | if (omap_crtc->apply_irq.registered) | |
314 | goto out; | |
315 | ||
316 | /* finish up previous apply's: */ | |
317 | list_for_each_entry_safe(apply, n, | |
318 | &omap_crtc->pending_applies, pending_node) { | |
319 | apply->post_apply(apply); | |
320 | list_del(&apply->pending_node); | |
321 | } | |
322 | ||
323 | need_apply = !list_empty(&omap_crtc->queued_applies); | |
324 | ||
325 | /* then handle the next round of of queued apply's: */ | |
326 | list_for_each_entry_safe(apply, n, | |
327 | &omap_crtc->queued_applies, queued_node) { | |
328 | apply->pre_apply(apply); | |
329 | list_del(&apply->queued_node); | |
330 | apply->queued = false; | |
331 | list_add_tail(&apply->pending_node, | |
332 | &omap_crtc->pending_applies); | |
333 | } | |
334 | ||
335 | if (need_apply) { | |
336 | enum omap_channel channel = omap_crtc->channel; | |
337 | ||
338 | DBG("%s: GO", omap_crtc->name); | |
339 | ||
340 | if (dispc_mgr_is_enabled(channel)) { | |
341 | dispc_mgr_go(channel); | |
342 | omap_irq_register(dev, &omap_crtc->apply_irq); | |
343 | } else { | |
344 | struct omap_drm_private *priv = dev->dev_private; | |
345 | queue_work(priv->wq, &omap_crtc->apply_work); | |
346 | } | |
347 | } | |
348 | ||
349 | out: | |
350 | dispc_runtime_put(); | |
351 | drm_modeset_unlock(&crtc->mutex); | |
352 | } | |
353 | ||
354 | int omap_crtc_apply(struct drm_crtc *crtc, | |
355 | struct omap_drm_apply *apply) | |
356 | { | |
357 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
358 | ||
359 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
360 | ||
361 | /* no need to queue it again if it is already queued: */ | |
362 | if (apply->queued) | |
363 | return 0; | |
364 | ||
365 | apply->queued = true; | |
366 | list_add_tail(&apply->queued_node, &omap_crtc->queued_applies); | |
367 | ||
368 | /* | |
369 | * If there are no currently pending updates, then go ahead and | |
370 | * kick the worker immediately, otherwise it will run again when | |
371 | * the current update finishes. | |
372 | */ | |
373 | if (list_empty(&omap_crtc->pending_applies)) { | |
374 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
375 | queue_work(priv->wq, &omap_crtc->apply_work); | |
376 | } | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static void omap_crtc_pre_apply(struct omap_drm_apply *apply) | |
382 | { | |
383 | struct omap_crtc *omap_crtc = | |
384 | container_of(apply, struct omap_crtc, apply); | |
385 | struct drm_crtc *crtc = &omap_crtc->base; | |
386 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
387 | struct drm_encoder *encoder = NULL; | |
388 | unsigned int i; | |
389 | ||
390 | DBG("%s: enabled=%d", omap_crtc->name, omap_crtc->enabled); | |
391 | ||
392 | for (i = 0; i < priv->num_encoders; i++) { | |
393 | if (priv->encoders[i]->crtc == crtc) { | |
394 | encoder = priv->encoders[i]; | |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
399 | if (omap_crtc->current_encoder && encoder != omap_crtc->current_encoder) | |
400 | omap_encoder_set_enabled(omap_crtc->current_encoder, false); | |
401 | ||
402 | omap_crtc->current_encoder = encoder; | |
403 | ||
404 | if (!omap_crtc->enabled) { | |
405 | if (encoder) | |
406 | omap_encoder_set_enabled(encoder, false); | |
407 | } else { | |
408 | if (encoder) { | |
409 | omap_encoder_set_enabled(encoder, false); | |
410 | omap_encoder_update(encoder, omap_crtc->mgr, | |
411 | &omap_crtc->timings); | |
412 | omap_encoder_set_enabled(encoder, true); | |
413 | } | |
414 | } | |
415 | } | |
416 | ||
417 | static void omap_crtc_post_apply(struct omap_drm_apply *apply) | |
418 | { | |
419 | /* nothing needed for post-apply */ | |
420 | } | |
421 | ||
422 | void omap_crtc_flush(struct drm_crtc *crtc) | |
423 | { | |
424 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
425 | int loops = 0; | |
426 | ||
427 | while (!list_empty(&omap_crtc->pending_applies) || | |
428 | !list_empty(&omap_crtc->queued_applies) || | |
429 | omap_crtc->event || omap_crtc->old_fb) { | |
430 | ||
431 | if (++loops > 10) { | |
432 | dev_err(crtc->dev->dev, | |
433 | "omap_crtc_flush() timeout\n"); | |
434 | break; | |
435 | } | |
436 | ||
437 | schedule_timeout_uninterruptible(msecs_to_jiffies(20)); | |
438 | } | |
439 | } | |
440 | ||
441 | /* ----------------------------------------------------------------------------- | |
442 | * CRTC Functions | |
f5f9454c RC |
443 | */ |
444 | ||
cd5351f4 RC |
445 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
446 | { | |
447 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
448 | |
449 | DBG("%s", omap_crtc->name); | |
450 | ||
451 | WARN_ON(omap_crtc->apply_irq.registered); | |
452 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); | |
453 | ||
cd5351f4 | 454 | drm_crtc_cleanup(crtc); |
f5f9454c | 455 | |
cd5351f4 RC |
456 | kfree(omap_crtc); |
457 | } | |
458 | ||
459 | static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) | |
460 | { | |
bb5c2d9a | 461 | struct omap_drm_private *priv = crtc->dev->dev_private; |
cd5351f4 | 462 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f5f9454c | 463 | bool enabled = (mode == DRM_MODE_DPMS_ON); |
bb5c2d9a | 464 | int i; |
cd5351f4 | 465 | |
f5f9454c RC |
466 | DBG("%s: %d", omap_crtc->name, mode); |
467 | ||
468 | if (enabled != omap_crtc->enabled) { | |
469 | omap_crtc->enabled = enabled; | |
f5f9454c | 470 | omap_crtc_apply(crtc, &omap_crtc->apply); |
cd5351f4 | 471 | |
ef6b0e02 | 472 | /* Enable/disable all planes associated with the CRTC. */ |
f5f9454c RC |
473 | for (i = 0; i < priv->num_planes; i++) { |
474 | struct drm_plane *plane = priv->planes[i]; | |
475 | if (plane->crtc == crtc) | |
2debab97 | 476 | WARN_ON(omap_plane_set_enable(plane, enabled)); |
f5f9454c | 477 | } |
cd5351f4 | 478 | } |
cd5351f4 RC |
479 | } |
480 | ||
481 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 482 | const struct drm_display_mode *mode, |
bb5c2d9a | 483 | struct drm_display_mode *adjusted_mode) |
cd5351f4 | 484 | { |
cd5351f4 RC |
485 | return true; |
486 | } | |
487 | ||
488 | static int omap_crtc_mode_set(struct drm_crtc *crtc, | |
bb5c2d9a RC |
489 | struct drm_display_mode *mode, |
490 | struct drm_display_mode *adjusted_mode, | |
491 | int x, int y, | |
492 | struct drm_framebuffer *old_fb) | |
cd5351f4 RC |
493 | { |
494 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
495 | ||
f5f9454c RC |
496 | mode = adjusted_mode; |
497 | ||
498 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
499 | omap_crtc->name, mode->base.id, mode->name, | |
500 | mode->vrefresh, mode->clock, | |
501 | mode->hdisplay, mode->hsync_start, | |
502 | mode->hsync_end, mode->htotal, | |
503 | mode->vdisplay, mode->vsync_start, | |
504 | mode->vsync_end, mode->vtotal, | |
505 | mode->type, mode->flags); | |
506 | ||
507 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
f5f9454c | 508 | |
ef6b0e02 LP |
509 | /* |
510 | * The primary plane CRTC can be reset if the plane is disabled directly | |
511 | * through the universal plane API. Set it again here. | |
512 | */ | |
513 | crtc->primary->crtc = crtc; | |
514 | ||
515 | return omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, | |
a350da8b LP |
516 | 0, 0, mode->hdisplay, mode->vdisplay, |
517 | x, y, mode->hdisplay, mode->vdisplay, | |
518 | NULL, NULL); | |
cd5351f4 RC |
519 | } |
520 | ||
521 | static void omap_crtc_prepare(struct drm_crtc *crtc) | |
522 | { | |
523 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 524 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
525 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
526 | } | |
527 | ||
528 | static void omap_crtc_commit(struct drm_crtc *crtc) | |
529 | { | |
530 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 531 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
532 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
533 | } | |
534 | ||
535 | static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
bb5c2d9a | 536 | struct drm_framebuffer *old_fb) |
cd5351f4 | 537 | { |
ef6b0e02 | 538 | struct drm_plane *plane = crtc->primary; |
bb5c2d9a | 539 | struct drm_display_mode *mode = &crtc->mode; |
cd5351f4 | 540 | |
f4510a27 | 541 | return omap_plane_mode_set(plane, crtc, crtc->primary->fb, |
a350da8b LP |
542 | 0, 0, mode->hdisplay, mode->vdisplay, |
543 | x, y, mode->hdisplay, mode->vdisplay, | |
544 | NULL, NULL); | |
cd5351f4 RC |
545 | } |
546 | ||
72d0c336 | 547 | static void vblank_cb(void *arg) |
cd5351f4 RC |
548 | { |
549 | struct drm_crtc *crtc = arg; | |
550 | struct drm_device *dev = crtc->dev; | |
551 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
cd5351f4 RC |
552 | unsigned long flags; |
553 | ||
f5f9454c RC |
554 | spin_lock_irqsave(&dev->event_lock, flags); |
555 | ||
556 | /* wakeup userspace */ | |
557 | if (omap_crtc->event) | |
558 | drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); | |
cd5351f4 RC |
559 | |
560 | omap_crtc->event = NULL; | |
f5f9454c | 561 | omap_crtc->old_fb = NULL; |
cd5351f4 | 562 | |
f5f9454c | 563 | spin_unlock_irqrestore(&dev->event_lock, flags); |
cd5351f4 RC |
564 | } |
565 | ||
f5f9454c | 566 | static void page_flip_worker(struct work_struct *work) |
72d0c336 | 567 | { |
f5f9454c RC |
568 | struct omap_crtc *omap_crtc = |
569 | container_of(work, struct omap_crtc, page_flip_work); | |
570 | struct drm_crtc *crtc = &omap_crtc->base; | |
f5f9454c | 571 | struct drm_display_mode *mode = &crtc->mode; |
119c0814 | 572 | struct drm_gem_object *bo; |
72d0c336 | 573 | |
51fd371b | 574 | drm_modeset_lock(&crtc->mutex, NULL); |
ef6b0e02 | 575 | omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, |
a350da8b LP |
576 | 0, 0, mode->hdisplay, mode->vdisplay, |
577 | crtc->x, crtc->y, mode->hdisplay, mode->vdisplay, | |
578 | vblank_cb, crtc); | |
51fd371b | 579 | drm_modeset_unlock(&crtc->mutex); |
119c0814 | 580 | |
f4510a27 | 581 | bo = omap_framebuffer_bo(crtc->primary->fb, 0); |
119c0814 | 582 | drm_gem_object_unreference_unlocked(bo); |
72d0c336 RC |
583 | } |
584 | ||
f5f9454c RC |
585 | static void page_flip_cb(void *arg) |
586 | { | |
587 | struct drm_crtc *crtc = arg; | |
588 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
589 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
590 | ||
591 | /* avoid assumptions about what ctxt we are called from: */ | |
592 | queue_work(priv->wq, &omap_crtc->page_flip_work); | |
593 | } | |
594 | ||
cd5351f4 RC |
595 | static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, |
596 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
597 | struct drm_pending_vblank_event *event, |
598 | uint32_t page_flip_flags) | |
cd5351f4 RC |
599 | { |
600 | struct drm_device *dev = crtc->dev; | |
601 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f4510a27 | 602 | struct drm_plane *primary = crtc->primary; |
119c0814 | 603 | struct drm_gem_object *bo; |
38e5597a | 604 | unsigned long flags; |
cd5351f4 | 605 | |
f4510a27 | 606 | DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1, |
f5f9454c | 607 | fb->base.id, event); |
cd5351f4 | 608 | |
38e5597a AT |
609 | spin_lock_irqsave(&dev->event_lock, flags); |
610 | ||
f5f9454c | 611 | if (omap_crtc->old_fb) { |
38e5597a | 612 | spin_unlock_irqrestore(&dev->event_lock, flags); |
cd5351f4 | 613 | dev_err(dev->dev, "already a pending flip\n"); |
549a7549 | 614 | return -EBUSY; |
cd5351f4 RC |
615 | } |
616 | ||
cd5351f4 | 617 | omap_crtc->event = event; |
bc905ace | 618 | omap_crtc->old_fb = primary->fb = fb; |
cd5351f4 | 619 | |
38e5597a AT |
620 | spin_unlock_irqrestore(&dev->event_lock, flags); |
621 | ||
119c0814 RC |
622 | /* |
623 | * Hold a reference temporarily until the crtc is updated | |
624 | * and takes the reference to the bo. This avoids it | |
625 | * getting freed from under us: | |
626 | */ | |
627 | bo = omap_framebuffer_bo(fb, 0); | |
628 | drm_gem_object_reference(bo); | |
629 | ||
630 | omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc); | |
cd5351f4 RC |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
3c810c61 RC |
635 | static int omap_crtc_set_property(struct drm_crtc *crtc, |
636 | struct drm_property *property, uint64_t val) | |
637 | { | |
1e0fdfc2 RC |
638 | struct omap_drm_private *priv = crtc->dev->dev_private; |
639 | ||
640 | if (property == priv->rotation_prop) { | |
641 | crtc->invert_dimensions = | |
642 | !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270))); | |
643 | } | |
644 | ||
ef6b0e02 | 645 | return omap_plane_set_property(crtc->primary, property, val); |
3c810c61 RC |
646 | } |
647 | ||
cd5351f4 | 648 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
cd5351f4 RC |
649 | .set_config = drm_crtc_helper_set_config, |
650 | .destroy = omap_crtc_destroy, | |
651 | .page_flip = omap_crtc_page_flip_locked, | |
3c810c61 | 652 | .set_property = omap_crtc_set_property, |
cd5351f4 RC |
653 | }; |
654 | ||
655 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
656 | .dpms = omap_crtc_dpms, | |
657 | .mode_fixup = omap_crtc_mode_fixup, | |
658 | .mode_set = omap_crtc_mode_set, | |
659 | .prepare = omap_crtc_prepare, | |
660 | .commit = omap_crtc_commit, | |
661 | .mode_set_base = omap_crtc_mode_set_base, | |
cd5351f4 RC |
662 | }; |
663 | ||
971fb3e5 LP |
664 | /* ----------------------------------------------------------------------------- |
665 | * Init and Cleanup | |
666 | */ | |
e2f8fd74 | 667 | |
f5f9454c | 668 | static const char *channel_names[] = { |
222025e4 LP |
669 | [OMAP_DSS_CHANNEL_LCD] = "lcd", |
670 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
671 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
672 | [OMAP_DSS_CHANNEL_LCD3] = "lcd3", | |
f5f9454c RC |
673 | }; |
674 | ||
04b1fc02 TV |
675 | void omap_crtc_pre_init(void) |
676 | { | |
677 | dss_install_mgr_ops(&mgr_ops); | |
678 | } | |
679 | ||
3a01ab25 AT |
680 | void omap_crtc_pre_uninit(void) |
681 | { | |
682 | dss_uninstall_mgr_ops(); | |
683 | } | |
684 | ||
cd5351f4 RC |
685 | /* initialize crtc */ |
686 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 687 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
688 | { |
689 | struct drm_crtc *crtc = NULL; | |
f5f9454c RC |
690 | struct omap_crtc *omap_crtc; |
691 | struct omap_overlay_manager_info *info; | |
ef6b0e02 | 692 | int ret; |
f5f9454c RC |
693 | |
694 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 695 | |
f5f9454c | 696 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 697 | if (!omap_crtc) |
ef6b0e02 | 698 | return NULL; |
cd5351f4 | 699 | |
cd5351f4 | 700 | crtc = &omap_crtc->base; |
bb5c2d9a | 701 | |
f5f9454c RC |
702 | INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); |
703 | INIT_WORK(&omap_crtc->apply_work, apply_worker); | |
704 | ||
705 | INIT_LIST_HEAD(&omap_crtc->pending_applies); | |
706 | INIT_LIST_HEAD(&omap_crtc->queued_applies); | |
707 | ||
708 | omap_crtc->apply.pre_apply = omap_crtc_pre_apply; | |
709 | omap_crtc->apply.post_apply = omap_crtc_post_apply; | |
710 | ||
0d8f371f | 711 | omap_crtc->channel = channel; |
0d8f371f AT |
712 | omap_crtc->name = channel_names[channel]; |
713 | omap_crtc->pipe = id; | |
714 | ||
715 | omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); | |
f5f9454c RC |
716 | omap_crtc->apply_irq.irq = omap_crtc_apply_irq; |
717 | ||
718 | omap_crtc->error_irq.irqmask = | |
719 | dispc_mgr_get_sync_lost_irq(channel); | |
720 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
721 | omap_irq_register(dev, &omap_crtc->error_irq); | |
722 | ||
f5f9454c | 723 | /* temporary: */ |
04b1fc02 | 724 | omap_crtc->mgr = omap_dss_get_overlay_manager(channel); |
f5f9454c RC |
725 | |
726 | /* TODO: fix hard-coded setup.. add properties! */ | |
727 | info = &omap_crtc->info; | |
728 | info->default_color = 0x00000000; | |
729 | info->trans_key = 0x00000000; | |
730 | info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
731 | info->trans_enabled = false; | |
bb5c2d9a | 732 | |
ef6b0e02 LP |
733 | ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, |
734 | &omap_crtc_funcs); | |
735 | if (ret < 0) { | |
736 | kfree(omap_crtc); | |
737 | return NULL; | |
738 | } | |
739 | ||
cd5351f4 RC |
740 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); |
741 | ||
ef6b0e02 | 742 | omap_plane_install_properties(crtc->primary, &crtc->base); |
3c810c61 | 743 | |
04b1fc02 TV |
744 | omap_crtcs[channel] = omap_crtc; |
745 | ||
cd5351f4 | 746 | return crtc; |
cd5351f4 | 747 | } |