Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
a42133a7 LP |
20 | #include <linux/completion.h> |
21 | ||
69a12263 LP |
22 | #include <drm/drm_atomic.h> |
23 | #include <drm/drm_atomic_helper.h> | |
2d278f54 LP |
24 | #include <drm/drm_crtc.h> |
25 | #include <drm/drm_crtc_helper.h> | |
b9ed9f0e | 26 | #include <drm/drm_mode.h> |
3cb9ae4f | 27 | #include <drm/drm_plane_helper.h> |
2d278f54 LP |
28 | |
29 | #include "omap_drv.h" | |
cd5351f4 RC |
30 | |
31 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
32 | ||
33 | struct omap_crtc { | |
34 | struct drm_crtc base; | |
f5f9454c | 35 | |
bb5c2d9a | 36 | const char *name; |
f5f9454c | 37 | enum omap_channel channel; |
f5f9454c RC |
38 | |
39 | /* | |
40 | * Temporary: eventually this will go away, but it is needed | |
41 | * for now to keep the output's happy. (They only need | |
42 | * mgr->id.) Eventually this will be replaced w/ something | |
43 | * more common-panel-framework-y | |
44 | */ | |
04b1fc02 | 45 | struct omap_overlay_manager *mgr; |
f5f9454c RC |
46 | |
47 | struct omap_video_timings timings; | |
f5f9454c | 48 | |
a42133a7 | 49 | struct omap_drm_irq vblank_irq; |
f5f9454c RC |
50 | struct omap_drm_irq error_irq; |
51 | ||
fa16d262 LP |
52 | /* pending event */ |
53 | struct drm_pending_vblank_event *event; | |
c397cfd4 | 54 | wait_queue_head_t flip_wait; |
f5f9454c | 55 | |
a42133a7 LP |
56 | struct completion completion; |
57 | ||
a36af73f | 58 | bool ignore_digit_sync_lost; |
f5f9454c RC |
59 | }; |
60 | ||
971fb3e5 LP |
61 | /* ----------------------------------------------------------------------------- |
62 | * Helper Functions | |
63 | */ | |
64 | ||
0d8f371f AT |
65 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
66 | { | |
67 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
68 | ||
69 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
70 | } | |
71 | ||
4029755e | 72 | struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
971fb3e5 LP |
73 | { |
74 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
75 | return &omap_crtc->timings; | |
76 | } | |
77 | ||
78 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
79 | { | |
80 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
81 | return omap_crtc->channel; | |
82 | } | |
83 | ||
84 | /* ----------------------------------------------------------------------------- | |
85 | * DSS Manager Functions | |
86 | */ | |
87 | ||
f5f9454c RC |
88 | /* |
89 | * Manager-ops, callbacks from output when they need to configure | |
90 | * the upstream part of the video pipe. | |
91 | * | |
92 | * Most of these we can ignore until we add support for command-mode | |
93 | * panels.. for video-mode the crtc-helpers already do an adequate | |
94 | * job of sequencing the setup of the video pipe in the proper order | |
95 | */ | |
96 | ||
04b1fc02 TV |
97 | /* ovl-mgr-id -> crtc */ |
98 | static struct omap_crtc *omap_crtcs[8]; | |
99 | ||
f5f9454c | 100 | /* we can probably ignore these until we support command-mode panels: */ |
4343f0f8 | 101 | static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 102 | struct omap_dss_device *dst) |
a7e71e7f TV |
103 | { |
104 | if (mgr->output) | |
105 | return -EINVAL; | |
106 | ||
107 | if ((mgr->supported_outputs & dst->id) == 0) | |
108 | return -EINVAL; | |
109 | ||
110 | dst->manager = mgr; | |
111 | mgr->output = dst; | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
4343f0f8 | 116 | static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 117 | struct omap_dss_device *dst) |
a7e71e7f TV |
118 | { |
119 | mgr->output->manager = NULL; | |
120 | mgr->output = NULL; | |
121 | } | |
122 | ||
4343f0f8 | 123 | static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr) |
f5f9454c RC |
124 | { |
125 | } | |
126 | ||
4029755e | 127 | /* Called only from the encoder enable/disable and suspend/resume handlers. */ |
8472b570 LP |
128 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) |
129 | { | |
130 | struct drm_device *dev = crtc->dev; | |
131 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
132 | enum omap_channel channel = omap_crtc->channel; | |
133 | struct omap_irq_wait *wait; | |
134 | u32 framedone_irq, vsync_irq; | |
135 | int ret; | |
136 | ||
137 | if (dispc_mgr_is_enabled(channel) == enable) | |
138 | return; | |
139 | ||
ef422283 TV |
140 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
141 | /* | |
142 | * Digit output produces some sync lost interrupts during the | |
143 | * first frame when enabling, so we need to ignore those. | |
144 | */ | |
145 | omap_crtc->ignore_digit_sync_lost = true; | |
146 | } | |
8472b570 LP |
147 | |
148 | framedone_irq = dispc_mgr_get_framedone_irq(channel); | |
149 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | |
150 | ||
151 | if (enable) { | |
152 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
153 | } else { | |
154 | /* | |
155 | * When we disable the digit output, we need to wait for | |
156 | * FRAMEDONE to know that DISPC has finished with the output. | |
157 | * | |
158 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
159 | * that case we need to use vsync interrupt, and wait for both | |
160 | * even and odd frames. | |
161 | */ | |
162 | ||
163 | if (framedone_irq) | |
164 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
165 | else | |
166 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
167 | } | |
168 | ||
169 | dispc_mgr_enable(channel, enable); | |
170 | ||
171 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
172 | if (ret) { | |
173 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
174 | omap_crtc->name, enable ? "enable" : "disable"); | |
175 | } | |
176 | ||
ef422283 TV |
177 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
178 | omap_crtc->ignore_digit_sync_lost = false; | |
179 | /* make sure the irq handler sees the value above */ | |
180 | mb(); | |
181 | } | |
8472b570 LP |
182 | } |
183 | ||
506096a1 | 184 | |
4343f0f8 | 185 | static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr) |
f5f9454c | 186 | { |
506096a1 | 187 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
dee8260d | 188 | struct omap_overlay_manager_info info; |
506096a1 | 189 | |
dee8260d LP |
190 | memset(&info, 0, sizeof(info)); |
191 | info.default_color = 0x00000000; | |
192 | info.trans_key = 0x00000000; | |
193 | info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
194 | info.trans_enabled = false; | |
195 | ||
196 | dispc_mgr_setup(omap_crtc->channel, &info); | |
506096a1 TV |
197 | dispc_mgr_set_timings(omap_crtc->channel, |
198 | &omap_crtc->timings); | |
8472b570 | 199 | omap_crtc_set_enabled(&omap_crtc->base, true); |
506096a1 | 200 | |
f5f9454c RC |
201 | return 0; |
202 | } | |
203 | ||
4343f0f8 | 204 | static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr) |
f5f9454c | 205 | { |
506096a1 TV |
206 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
207 | ||
8472b570 | 208 | omap_crtc_set_enabled(&omap_crtc->base, false); |
f5f9454c RC |
209 | } |
210 | ||
4343f0f8 | 211 | static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr, |
f5f9454c RC |
212 | const struct omap_video_timings *timings) |
213 | { | |
04b1fc02 | 214 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
215 | DBG("%s", omap_crtc->name); |
216 | omap_crtc->timings = *timings; | |
f5f9454c RC |
217 | } |
218 | ||
4343f0f8 | 219 | static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr, |
f5f9454c RC |
220 | const struct dss_lcd_mgr_config *config) |
221 | { | |
04b1fc02 | 222 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
223 | DBG("%s", omap_crtc->name); |
224 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
225 | } | |
226 | ||
4343f0f8 | 227 | static int omap_crtc_dss_register_framedone( |
f5f9454c RC |
228 | struct omap_overlay_manager *mgr, |
229 | void (*handler)(void *), void *data) | |
230 | { | |
231 | return 0; | |
232 | } | |
233 | ||
4343f0f8 | 234 | static void omap_crtc_dss_unregister_framedone( |
f5f9454c RC |
235 | struct omap_overlay_manager *mgr, |
236 | void (*handler)(void *), void *data) | |
237 | { | |
238 | } | |
239 | ||
240 | static const struct dss_mgr_ops mgr_ops = { | |
4343f0f8 LP |
241 | .connect = omap_crtc_dss_connect, |
242 | .disconnect = omap_crtc_dss_disconnect, | |
243 | .start_update = omap_crtc_dss_start_update, | |
244 | .enable = omap_crtc_dss_enable, | |
245 | .disable = omap_crtc_dss_disable, | |
246 | .set_timings = omap_crtc_dss_set_timings, | |
247 | .set_lcd_config = omap_crtc_dss_set_lcd_config, | |
248 | .register_framedone_handler = omap_crtc_dss_register_framedone, | |
249 | .unregister_framedone_handler = omap_crtc_dss_unregister_framedone, | |
cd5351f4 RC |
250 | }; |
251 | ||
971fb3e5 | 252 | /* ----------------------------------------------------------------------------- |
1d5e5ea1 | 253 | * Setup, Flush and Page Flip |
971fb3e5 LP |
254 | */ |
255 | ||
fa16d262 | 256 | static void omap_crtc_complete_page_flip(struct drm_crtc *crtc) |
15d02e92 LP |
257 | { |
258 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
fa16d262 | 259 | struct drm_pending_vblank_event *event; |
15d02e92 | 260 | struct drm_device *dev = crtc->dev; |
fa16d262 | 261 | unsigned long flags; |
15d02e92 | 262 | |
fa16d262 | 263 | spin_lock_irqsave(&dev->event_lock, flags); |
15d02e92 | 264 | |
fa16d262 LP |
265 | event = omap_crtc->event; |
266 | omap_crtc->event = NULL; | |
c397cfd4 | 267 | |
fa16d262 | 268 | if (event) { |
1cfe19aa LP |
269 | list_del(&event->base.link); |
270 | ||
271 | /* | |
272 | * Queue the event for delivery if it's still linked to a file | |
273 | * handle, otherwise just destroy it. | |
274 | */ | |
275 | if (event->base.file_priv) | |
276 | drm_crtc_send_vblank_event(crtc, event); | |
277 | else | |
278 | event->base.destroy(&event->base); | |
279 | ||
c397cfd4 | 280 | wake_up(&omap_crtc->flip_wait); |
fa16d262 LP |
281 | drm_crtc_vblank_put(crtc); |
282 | } | |
283 | ||
284 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
c397cfd4 LP |
285 | } |
286 | ||
287 | static bool omap_crtc_page_flip_pending(struct drm_crtc *crtc) | |
288 | { | |
289 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
290 | struct drm_device *dev = crtc->dev; | |
291 | unsigned long flags; | |
292 | bool pending; | |
293 | ||
294 | spin_lock_irqsave(&dev->event_lock, flags); | |
fa16d262 | 295 | pending = omap_crtc->event != NULL; |
c397cfd4 LP |
296 | spin_unlock_irqrestore(&dev->event_lock, flags); |
297 | ||
298 | return pending; | |
299 | } | |
300 | ||
301 | static void omap_crtc_wait_page_flip(struct drm_crtc *crtc) | |
302 | { | |
303 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
c397cfd4 LP |
304 | |
305 | if (wait_event_timeout(omap_crtc->flip_wait, | |
306 | !omap_crtc_page_flip_pending(crtc), | |
307 | msecs_to_jiffies(50))) | |
308 | return; | |
309 | ||
310 | dev_warn(crtc->dev->dev, "page flip timeout!\n"); | |
311 | ||
fa16d262 | 312 | omap_crtc_complete_page_flip(crtc); |
15d02e92 LP |
313 | } |
314 | ||
971fb3e5 LP |
315 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
316 | { | |
317 | struct omap_crtc *omap_crtc = | |
318 | container_of(irq, struct omap_crtc, error_irq); | |
a36af73f TV |
319 | |
320 | if (omap_crtc->ignore_digit_sync_lost) { | |
321 | irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
322 | if (!irqstatus) | |
323 | return; | |
324 | } | |
325 | ||
3b143fc8 | 326 | DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); |
971fb3e5 LP |
327 | } |
328 | ||
a42133a7 | 329 | static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
971fb3e5 LP |
330 | { |
331 | struct omap_crtc *omap_crtc = | |
a42133a7 LP |
332 | container_of(irq, struct omap_crtc, vblank_irq); |
333 | struct drm_device *dev = omap_crtc->base.dev; | |
971fb3e5 | 334 | |
a42133a7 LP |
335 | if (dispc_mgr_go_busy(omap_crtc->channel)) |
336 | return; | |
337 | ||
338 | DBG("%s: apply done", omap_crtc->name); | |
339 | __omap_irq_unregister(dev, &omap_crtc->vblank_irq); | |
340 | ||
a42133a7 | 341 | /* wakeup userspace */ |
fa16d262 | 342 | omap_crtc_complete_page_flip(&omap_crtc->base); |
a42133a7 LP |
343 | |
344 | complete(&omap_crtc->completion); | |
971fb3e5 LP |
345 | } |
346 | ||
bec10a2a | 347 | static int omap_crtc_flush(struct drm_crtc *crtc) |
971fb3e5 | 348 | { |
a42133a7 | 349 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
971fb3e5 | 350 | |
a42133a7 | 351 | DBG("%s: GO", omap_crtc->name); |
971fb3e5 | 352 | |
a42133a7 | 353 | WARN_ON(omap_crtc->vblank_irq.registered); |
971fb3e5 | 354 | |
a42133a7 LP |
355 | if (dispc_mgr_is_enabled(omap_crtc->channel)) { |
356 | dispc_mgr_go(omap_crtc->channel); | |
357 | omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); | |
971fb3e5 | 358 | |
a42133a7 LP |
359 | WARN_ON(!wait_for_completion_timeout(&omap_crtc->completion, |
360 | msecs_to_jiffies(100))); | |
361 | reinit_completion(&omap_crtc->completion); | |
362 | } | |
971fb3e5 | 363 | |
971fb3e5 LP |
364 | return 0; |
365 | } | |
366 | ||
971fb3e5 LP |
367 | /* ----------------------------------------------------------------------------- |
368 | * CRTC Functions | |
f5f9454c RC |
369 | */ |
370 | ||
cd5351f4 RC |
371 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
372 | { | |
373 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
374 | |
375 | DBG("%s", omap_crtc->name); | |
376 | ||
a42133a7 | 377 | WARN_ON(omap_crtc->vblank_irq.registered); |
f5f9454c RC |
378 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); |
379 | ||
cd5351f4 | 380 | drm_crtc_cleanup(crtc); |
f5f9454c | 381 | |
cd5351f4 RC |
382 | kfree(omap_crtc); |
383 | } | |
384 | ||
f1d57fb5 LP |
385 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, |
386 | const struct drm_display_mode *mode, | |
387 | struct drm_display_mode *adjusted_mode) | |
388 | { | |
389 | return true; | |
390 | } | |
391 | ||
392 | static void omap_crtc_enable(struct drm_crtc *crtc) | |
cd5351f4 RC |
393 | { |
394 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
395 | ||
f1d57fb5 | 396 | DBG("%s", omap_crtc->name); |
f5f9454c | 397 | |
f1d57fb5 | 398 | drm_crtc_vblank_on(crtc); |
cd5351f4 RC |
399 | } |
400 | ||
f1d57fb5 | 401 | static void omap_crtc_disable(struct drm_crtc *crtc) |
cd5351f4 | 402 | { |
f1d57fb5 | 403 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f1d57fb5 LP |
404 | |
405 | DBG("%s", omap_crtc->name); | |
406 | ||
f1d57fb5 | 407 | omap_crtc_wait_page_flip(crtc); |
f1d57fb5 | 408 | drm_crtc_vblank_off(crtc); |
cd5351f4 RC |
409 | } |
410 | ||
f7a73b65 | 411 | static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) |
cd5351f4 RC |
412 | { |
413 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f7a73b65 | 414 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
f5f9454c RC |
415 | |
416 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
f7a73b65 LP |
417 | omap_crtc->name, mode->base.id, mode->name, |
418 | mode->vrefresh, mode->clock, | |
419 | mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, | |
420 | mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, | |
421 | mode->type, mode->flags); | |
f5f9454c RC |
422 | |
423 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
cd5351f4 RC |
424 | } |
425 | ||
de8e4100 LP |
426 | static void omap_crtc_atomic_begin(struct drm_crtc *crtc) |
427 | { | |
fa16d262 | 428 | struct drm_pending_vblank_event *event = crtc->state->event; |
f5f9454c | 429 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
cd5351f4 | 430 | struct drm_device *dev = crtc->dev; |
38e5597a | 431 | unsigned long flags; |
cd5351f4 | 432 | |
fa16d262 LP |
433 | if (event) { |
434 | WARN_ON(omap_crtc->event); | |
435 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
38e5597a | 436 | |
fa16d262 LP |
437 | spin_lock_irqsave(&dev->event_lock, flags); |
438 | omap_crtc->event = event; | |
38e5597a | 439 | spin_unlock_irqrestore(&dev->event_lock, flags); |
cd5351f4 | 440 | } |
fa16d262 | 441 | } |
cd5351f4 | 442 | |
fa16d262 LP |
443 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc) |
444 | { | |
445 | omap_crtc_flush(crtc); | |
cd5351f4 | 446 | |
afc34932 LP |
447 | crtc->invert_dimensions = !!(crtc->primary->state->rotation & |
448 | (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))); | |
cd5351f4 RC |
449 | } |
450 | ||
afc34932 LP |
451 | static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, |
452 | struct drm_crtc_state *state, | |
453 | struct drm_property *property, | |
454 | uint64_t val) | |
3c810c61 | 455 | { |
afc34932 LP |
456 | struct drm_plane_state *plane_state; |
457 | struct drm_plane *plane = crtc->primary; | |
458 | ||
459 | /* | |
460 | * Delegate property set to the primary plane. Get the plane state and | |
461 | * set the property directly. | |
462 | */ | |
463 | ||
464 | plane_state = drm_atomic_get_plane_state(state->state, plane); | |
465 | if (!plane_state) | |
466 | return -EINVAL; | |
467 | ||
468 | return drm_atomic_plane_set_property(plane, plane_state, property, val); | |
469 | } | |
1e0fdfc2 | 470 | |
afc34932 LP |
471 | static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, |
472 | const struct drm_crtc_state *state, | |
473 | struct drm_property *property, | |
474 | uint64_t *val) | |
475 | { | |
476 | /* | |
477 | * Delegate property get to the primary plane. The | |
478 | * drm_atomic_plane_get_property() function isn't exported, but can be | |
479 | * called through drm_object_property_get_value() as that will call | |
480 | * drm_atomic_get_property() for atomic drivers. | |
481 | */ | |
482 | return drm_object_property_get_value(&crtc->primary->base, property, | |
483 | val); | |
3c810c61 RC |
484 | } |
485 | ||
cd5351f4 | 486 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
69a12263 | 487 | .reset = drm_atomic_helper_crtc_reset, |
9416c9df | 488 | .set_config = drm_atomic_helper_set_config, |
cd5351f4 | 489 | .destroy = omap_crtc_destroy, |
fa16d262 | 490 | .page_flip = drm_atomic_helper_page_flip, |
afc34932 | 491 | .set_property = drm_atomic_helper_crtc_set_property, |
69a12263 LP |
492 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
493 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
afc34932 LP |
494 | .atomic_set_property = omap_crtc_atomic_set_property, |
495 | .atomic_get_property = omap_crtc_atomic_get_property, | |
cd5351f4 RC |
496 | }; |
497 | ||
498 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
cd5351f4 | 499 | .mode_fixup = omap_crtc_mode_fixup, |
f7a73b65 | 500 | .mode_set_nofb = omap_crtc_mode_set_nofb, |
f1d57fb5 LP |
501 | .disable = omap_crtc_disable, |
502 | .enable = omap_crtc_enable, | |
de8e4100 LP |
503 | .atomic_begin = omap_crtc_atomic_begin, |
504 | .atomic_flush = omap_crtc_atomic_flush, | |
cd5351f4 RC |
505 | }; |
506 | ||
971fb3e5 LP |
507 | /* ----------------------------------------------------------------------------- |
508 | * Init and Cleanup | |
509 | */ | |
e2f8fd74 | 510 | |
f5f9454c | 511 | static const char *channel_names[] = { |
222025e4 LP |
512 | [OMAP_DSS_CHANNEL_LCD] = "lcd", |
513 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
514 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
515 | [OMAP_DSS_CHANNEL_LCD3] = "lcd3", | |
f5f9454c RC |
516 | }; |
517 | ||
04b1fc02 TV |
518 | void omap_crtc_pre_init(void) |
519 | { | |
520 | dss_install_mgr_ops(&mgr_ops); | |
521 | } | |
522 | ||
3a01ab25 AT |
523 | void omap_crtc_pre_uninit(void) |
524 | { | |
525 | dss_uninstall_mgr_ops(); | |
526 | } | |
527 | ||
cd5351f4 RC |
528 | /* initialize crtc */ |
529 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 530 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
531 | { |
532 | struct drm_crtc *crtc = NULL; | |
f5f9454c | 533 | struct omap_crtc *omap_crtc; |
ef6b0e02 | 534 | int ret; |
f5f9454c RC |
535 | |
536 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 537 | |
f5f9454c | 538 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 539 | if (!omap_crtc) |
ef6b0e02 | 540 | return NULL; |
cd5351f4 | 541 | |
cd5351f4 | 542 | crtc = &omap_crtc->base; |
bb5c2d9a | 543 | |
c397cfd4 | 544 | init_waitqueue_head(&omap_crtc->flip_wait); |
a42133a7 | 545 | init_completion(&omap_crtc->completion); |
f5f9454c | 546 | |
0d8f371f | 547 | omap_crtc->channel = channel; |
0d8f371f | 548 | omap_crtc->name = channel_names[channel]; |
0d8f371f | 549 | |
a42133a7 LP |
550 | omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc); |
551 | omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq; | |
f5f9454c RC |
552 | |
553 | omap_crtc->error_irq.irqmask = | |
554 | dispc_mgr_get_sync_lost_irq(channel); | |
555 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
556 | omap_irq_register(dev, &omap_crtc->error_irq); | |
557 | ||
f5f9454c | 558 | /* temporary: */ |
04b1fc02 | 559 | omap_crtc->mgr = omap_dss_get_overlay_manager(channel); |
f5f9454c | 560 | |
ef6b0e02 LP |
561 | ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, |
562 | &omap_crtc_funcs); | |
563 | if (ret < 0) { | |
564 | kfree(omap_crtc); | |
565 | return NULL; | |
566 | } | |
567 | ||
cd5351f4 RC |
568 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); |
569 | ||
ef6b0e02 | 570 | omap_plane_install_properties(crtc->primary, &crtc->base); |
3c810c61 | 571 | |
04b1fc02 TV |
572 | omap_crtcs[channel] = omap_crtc; |
573 | ||
cd5351f4 | 574 | return crtc; |
cd5351f4 | 575 | } |