Commit | Line | Data |
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71e8831f AG |
1 | /* |
2 | * DMM IOMMU driver support functions for TI OMAP processors. | |
3 | * | |
4 | * Author: Rob Clark <rob@ti.com> | |
5 | * Andy Gross <andy.gross@ti.com> | |
6 | * | |
7 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation version 2. | |
12 | * | |
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
14 | * kind, whether express or implied; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> /* platform_device() */ | |
21 | #include <linux/errno.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/wait.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/vmalloc.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/list.h> | |
71e8831f AG |
32 | |
33 | #include "omap_dmm_tiler.h" | |
34 | #include "omap_dmm_priv.h" | |
35 | ||
5c137797 AG |
36 | #define DMM_DRIVER_NAME "dmm" |
37 | ||
71e8831f AG |
38 | /* mappings for associating views to luts */ |
39 | static struct tcm *containers[TILFMT_NFORMATS]; | |
40 | static struct dmm *omap_dmm; | |
41 | ||
ef445934 AG |
42 | /* global spinlock for protecting lists */ |
43 | static DEFINE_SPINLOCK(list_lock); | |
44 | ||
71e8831f AG |
45 | /* Geometry table */ |
46 | #define GEOM(xshift, yshift, bytes_per_pixel) { \ | |
47 | .x_shft = (xshift), \ | |
48 | .y_shft = (yshift), \ | |
49 | .cpp = (bytes_per_pixel), \ | |
50 | .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \ | |
51 | .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \ | |
52 | } | |
53 | ||
54 | static const struct { | |
55 | uint32_t x_shft; /* unused X-bits (as part of bpp) */ | |
56 | uint32_t y_shft; /* unused Y-bits (as part of bpp) */ | |
57 | uint32_t cpp; /* bytes/chars per pixel */ | |
58 | uint32_t slot_w; /* width of each slot (in pixels) */ | |
59 | uint32_t slot_h; /* height of each slot (in pixels) */ | |
60 | } geom[TILFMT_NFORMATS] = { | |
61 | [TILFMT_8BIT] = GEOM(0, 0, 1), | |
62 | [TILFMT_16BIT] = GEOM(0, 1, 2), | |
63 | [TILFMT_32BIT] = GEOM(1, 1, 4), | |
64 | [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1), | |
65 | }; | |
66 | ||
67 | ||
68 | /* lookup table for registers w/ per-engine instances */ | |
69 | static const uint32_t reg[][4] = { | |
70 | [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, | |
71 | DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, | |
72 | [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, | |
73 | DMM_PAT_DESCR__2, DMM_PAT_DESCR__3}, | |
74 | }; | |
75 | ||
76 | /* simple allocator to grab next 16 byte aligned memory from txn */ | |
77 | static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) | |
78 | { | |
79 | void *ptr; | |
80 | struct refill_engine *engine = txn->engine_handle; | |
81 | ||
82 | /* dmm programming requires 16 byte aligned addresses */ | |
83 | txn->current_pa = round_up(txn->current_pa, 16); | |
84 | txn->current_va = (void *)round_up((long)txn->current_va, 16); | |
85 | ||
86 | ptr = txn->current_va; | |
87 | *pa = txn->current_pa; | |
88 | ||
89 | txn->current_pa += sz; | |
90 | txn->current_va += sz; | |
91 | ||
92 | BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); | |
93 | ||
94 | return ptr; | |
95 | } | |
96 | ||
97 | /* check status and spin until wait_mask comes true */ | |
98 | static int wait_status(struct refill_engine *engine, uint32_t wait_mask) | |
99 | { | |
100 | struct dmm *dmm = engine->dmm; | |
101 | uint32_t r = 0, err, i; | |
102 | ||
103 | i = DMM_FIXED_RETRY_COUNT; | |
104 | while (true) { | |
105 | r = readl(dmm->base + reg[PAT_STATUS][engine->id]); | |
106 | err = r & DMM_PATSTATUS_ERR; | |
107 | if (err) | |
108 | return -EFAULT; | |
109 | ||
110 | if ((r & wait_mask) == wait_mask) | |
111 | break; | |
112 | ||
113 | if (--i == 0) | |
114 | return -ETIMEDOUT; | |
115 | ||
116 | udelay(1); | |
117 | } | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
faaa0540 AG |
122 | static void release_engine(struct refill_engine *engine) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&list_lock, flags); | |
127 | list_add(&engine->idle_node, &omap_dmm->idle_head); | |
128 | spin_unlock_irqrestore(&list_lock, flags); | |
129 | ||
130 | atomic_inc(&omap_dmm->engine_counter); | |
131 | wake_up_interruptible(&omap_dmm->engine_queue); | |
132 | } | |
133 | ||
d7de9935 | 134 | static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) |
71e8831f AG |
135 | { |
136 | struct dmm *dmm = arg; | |
137 | uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS); | |
138 | int i; | |
139 | ||
140 | /* ack IRQ */ | |
141 | writel(status, dmm->base + DMM_PAT_IRQSTATUS); | |
142 | ||
143 | for (i = 0; i < dmm->num_engines; i++) { | |
faaa0540 | 144 | if (status & DMM_IRQSTAT_LST) { |
71e8831f AG |
145 | wake_up_interruptible(&dmm->engines[i].wait_for_refill); |
146 | ||
faaa0540 AG |
147 | if (dmm->engines[i].async) |
148 | release_engine(&dmm->engines[i]); | |
149 | } | |
150 | ||
71e8831f AG |
151 | status >>= 8; |
152 | } | |
153 | ||
154 | return IRQ_HANDLED; | |
155 | } | |
156 | ||
157 | /** | |
158 | * Get a handle for a DMM transaction | |
159 | */ | |
160 | static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) | |
161 | { | |
162 | struct dmm_txn *txn = NULL; | |
163 | struct refill_engine *engine = NULL; | |
faaa0540 AG |
164 | int ret; |
165 | unsigned long flags; | |
166 | ||
71e8831f | 167 | |
faaa0540 AG |
168 | /* wait until an engine is available */ |
169 | ret = wait_event_interruptible(omap_dmm->engine_queue, | |
170 | atomic_add_unless(&omap_dmm->engine_counter, -1, 0)); | |
171 | if (ret) | |
172 | return ERR_PTR(ret); | |
71e8831f AG |
173 | |
174 | /* grab an idle engine */ | |
faaa0540 | 175 | spin_lock_irqsave(&list_lock, flags); |
71e8831f AG |
176 | if (!list_empty(&dmm->idle_head)) { |
177 | engine = list_entry(dmm->idle_head.next, struct refill_engine, | |
178 | idle_node); | |
179 | list_del(&engine->idle_node); | |
180 | } | |
faaa0540 | 181 | spin_unlock_irqrestore(&list_lock, flags); |
71e8831f AG |
182 | |
183 | BUG_ON(!engine); | |
184 | ||
185 | txn = &engine->txn; | |
186 | engine->tcm = tcm; | |
187 | txn->engine_handle = engine; | |
188 | txn->last_pat = NULL; | |
189 | txn->current_va = engine->refill_va; | |
190 | txn->current_pa = engine->refill_pa; | |
191 | ||
192 | return txn; | |
193 | } | |
194 | ||
195 | /** | |
196 | * Add region to DMM transaction. If pages or pages[i] is NULL, then the | |
197 | * corresponding slot is cleared (ie. dummy_pa is programmed) | |
198 | */ | |
faaa0540 | 199 | static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, |
a6a91827 | 200 | struct page **pages, uint32_t npages, uint32_t roll) |
71e8831f AG |
201 | { |
202 | dma_addr_t pat_pa = 0; | |
203 | uint32_t *data; | |
204 | struct pat *pat; | |
205 | struct refill_engine *engine = txn->engine_handle; | |
206 | int columns = (1 + area->x1 - area->x0); | |
207 | int rows = (1 + area->y1 - area->y0); | |
208 | int i = columns*rows; | |
71e8831f AG |
209 | |
210 | pat = alloc_dma(txn, sizeof(struct pat), &pat_pa); | |
211 | ||
212 | if (txn->last_pat) | |
213 | txn->last_pat->next_pa = (uint32_t)pat_pa; | |
214 | ||
215 | pat->area = *area; | |
c6b7ae55 AG |
216 | |
217 | /* adjust Y coordinates based off of container parameters */ | |
218 | pat->area.y0 += engine->tcm->y_offset; | |
219 | pat->area.y1 += engine->tcm->y_offset; | |
220 | ||
71e8831f AG |
221 | pat->ctrl = (struct pat_ctrl){ |
222 | .start = 1, | |
223 | .lut_id = engine->tcm->lut_id, | |
224 | }; | |
225 | ||
226 | data = alloc_dma(txn, 4*i, &pat->data_pa); | |
227 | ||
228 | while (i--) { | |
a6a91827 RC |
229 | int n = i + roll; |
230 | if (n >= npages) | |
231 | n -= npages; | |
232 | data[i] = (pages && pages[n]) ? | |
233 | page_to_phys(pages[n]) : engine->dmm->dummy_pa; | |
71e8831f AG |
234 | } |
235 | ||
71e8831f AG |
236 | txn->last_pat = pat; |
237 | ||
faaa0540 | 238 | return; |
71e8831f AG |
239 | } |
240 | ||
241 | /** | |
242 | * Commit the DMM transaction. | |
243 | */ | |
244 | static int dmm_txn_commit(struct dmm_txn *txn, bool wait) | |
245 | { | |
246 | int ret = 0; | |
247 | struct refill_engine *engine = txn->engine_handle; | |
248 | struct dmm *dmm = engine->dmm; | |
249 | ||
250 | if (!txn->last_pat) { | |
251 | dev_err(engine->dmm->dev, "need at least one txn\n"); | |
252 | ret = -EINVAL; | |
253 | goto cleanup; | |
254 | } | |
255 | ||
256 | txn->last_pat->next_pa = 0; | |
257 | ||
258 | /* write to PAT_DESCR to clear out any pending transaction */ | |
259 | writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]); | |
260 | ||
261 | /* wait for engine ready: */ | |
262 | ret = wait_status(engine, DMM_PATSTATUS_READY); | |
263 | if (ret) { | |
264 | ret = -EFAULT; | |
265 | goto cleanup; | |
266 | } | |
267 | ||
faaa0540 AG |
268 | /* mark whether it is async to denote list management in IRQ handler */ |
269 | engine->async = wait ? false : true; | |
270 | ||
71e8831f AG |
271 | /* kick reload */ |
272 | writel(engine->refill_pa, | |
273 | dmm->base + reg[PAT_DESCR][engine->id]); | |
274 | ||
275 | if (wait) { | |
276 | if (wait_event_interruptible_timeout(engine->wait_for_refill, | |
277 | wait_status(engine, DMM_PATSTATUS_READY) == 0, | |
278 | msecs_to_jiffies(1)) <= 0) { | |
279 | dev_err(dmm->dev, "timed out waiting for done\n"); | |
280 | ret = -ETIMEDOUT; | |
281 | } | |
282 | } | |
283 | ||
284 | cleanup: | |
faaa0540 AG |
285 | /* only place engine back on list if we are done with it */ |
286 | if (ret || wait) | |
287 | release_engine(engine); | |
71e8831f | 288 | |
71e8831f AG |
289 | return ret; |
290 | } | |
291 | ||
292 | /* | |
293 | * DMM programming | |
294 | */ | |
a6a91827 RC |
295 | static int fill(struct tcm_area *area, struct page **pages, |
296 | uint32_t npages, uint32_t roll, bool wait) | |
71e8831f AG |
297 | { |
298 | int ret = 0; | |
299 | struct tcm_area slice, area_s; | |
300 | struct dmm_txn *txn; | |
301 | ||
302 | txn = dmm_txn_init(omap_dmm, area->tcm); | |
303 | if (IS_ERR_OR_NULL(txn)) | |
295c799a | 304 | return -ENOMEM; |
71e8831f AG |
305 | |
306 | tcm_for_each_slice(slice, *area, area_s) { | |
307 | struct pat_area p_area = { | |
308 | .x0 = slice.p0.x, .y0 = slice.p0.y, | |
309 | .x1 = slice.p1.x, .y1 = slice.p1.y, | |
310 | }; | |
311 | ||
faaa0540 | 312 | dmm_txn_append(txn, &p_area, pages, npages, roll); |
71e8831f | 313 | |
a6a91827 | 314 | roll += tcm_sizeof(slice); |
71e8831f AG |
315 | } |
316 | ||
317 | ret = dmm_txn_commit(txn, wait); | |
318 | ||
71e8831f AG |
319 | return ret; |
320 | } | |
321 | ||
322 | /* | |
323 | * Pin/unpin | |
324 | */ | |
325 | ||
326 | /* note: slots for which pages[i] == NULL are filled w/ dummy page | |
327 | */ | |
a6a91827 RC |
328 | int tiler_pin(struct tiler_block *block, struct page **pages, |
329 | uint32_t npages, uint32_t roll, bool wait) | |
71e8831f AG |
330 | { |
331 | int ret; | |
332 | ||
a6a91827 | 333 | ret = fill(&block->area, pages, npages, roll, wait); |
71e8831f AG |
334 | |
335 | if (ret) | |
336 | tiler_unpin(block); | |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
341 | int tiler_unpin(struct tiler_block *block) | |
342 | { | |
a6a91827 | 343 | return fill(&block->area, NULL, 0, 0, false); |
71e8831f AG |
344 | } |
345 | ||
346 | /* | |
347 | * Reserve/release | |
348 | */ | |
349 | struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, | |
350 | uint16_t h, uint16_t align) | |
351 | { | |
352 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); | |
353 | u32 min_align = 128; | |
354 | int ret; | |
faaa0540 | 355 | unsigned long flags; |
71e8831f AG |
356 | |
357 | BUG_ON(!validfmt(fmt)); | |
358 | ||
359 | /* convert width/height to slots */ | |
360 | w = DIV_ROUND_UP(w, geom[fmt].slot_w); | |
361 | h = DIV_ROUND_UP(h, geom[fmt].slot_h); | |
362 | ||
363 | /* convert alignment to slots */ | |
364 | min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp)); | |
365 | align = ALIGN(align, min_align); | |
366 | align /= geom[fmt].slot_w * geom[fmt].cpp; | |
367 | ||
368 | block->fmt = fmt; | |
369 | ||
370 | ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area); | |
371 | if (ret) { | |
372 | kfree(block); | |
1c3a4dc3 | 373 | return ERR_PTR(-ENOMEM); |
71e8831f AG |
374 | } |
375 | ||
376 | /* add to allocation list */ | |
faaa0540 | 377 | spin_lock_irqsave(&list_lock, flags); |
71e8831f | 378 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
faaa0540 | 379 | spin_unlock_irqrestore(&list_lock, flags); |
71e8831f AG |
380 | |
381 | return block; | |
382 | } | |
383 | ||
384 | struct tiler_block *tiler_reserve_1d(size_t size) | |
385 | { | |
386 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); | |
387 | int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; | |
faaa0540 | 388 | unsigned long flags; |
71e8831f AG |
389 | |
390 | if (!block) | |
d7de9935 | 391 | return ERR_PTR(-ENOMEM); |
71e8831f AG |
392 | |
393 | block->fmt = TILFMT_PAGE; | |
394 | ||
395 | if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages, | |
396 | &block->area)) { | |
397 | kfree(block); | |
1c3a4dc3 | 398 | return ERR_PTR(-ENOMEM); |
71e8831f AG |
399 | } |
400 | ||
faaa0540 | 401 | spin_lock_irqsave(&list_lock, flags); |
71e8831f | 402 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
faaa0540 | 403 | spin_unlock_irqrestore(&list_lock, flags); |
71e8831f AG |
404 | |
405 | return block; | |
406 | } | |
407 | ||
408 | /* note: if you have pin'd pages, you should have already unpin'd first! */ | |
409 | int tiler_release(struct tiler_block *block) | |
410 | { | |
411 | int ret = tcm_free(&block->area); | |
faaa0540 | 412 | unsigned long flags; |
71e8831f AG |
413 | |
414 | if (block->area.tcm) | |
415 | dev_err(omap_dmm->dev, "failed to release block\n"); | |
416 | ||
faaa0540 | 417 | spin_lock_irqsave(&list_lock, flags); |
71e8831f | 418 | list_del(&block->alloc_node); |
faaa0540 | 419 | spin_unlock_irqrestore(&list_lock, flags); |
71e8831f AG |
420 | |
421 | kfree(block); | |
422 | return ret; | |
423 | } | |
424 | ||
425 | /* | |
426 | * Utils | |
427 | */ | |
428 | ||
3c810c61 RC |
429 | /* calculate the tiler space address of a pixel in a view orientation... |
430 | * below description copied from the display subsystem section of TRM: | |
431 | * | |
432 | * When the TILER is addressed, the bits: | |
433 | * [28:27] = 0x0 for 8-bit tiled | |
434 | * 0x1 for 16-bit tiled | |
435 | * 0x2 for 32-bit tiled | |
436 | * 0x3 for page mode | |
437 | * [31:29] = 0x0 for 0-degree view | |
438 | * 0x1 for 180-degree view + mirroring | |
439 | * 0x2 for 0-degree view + mirroring | |
440 | * 0x3 for 180-degree view | |
441 | * 0x4 for 270-degree view + mirroring | |
442 | * 0x5 for 270-degree view | |
443 | * 0x6 for 90-degree view | |
444 | * 0x7 for 90-degree view + mirroring | |
445 | * Otherwise the bits indicated the corresponding bit address to access | |
446 | * the SDRAM. | |
447 | */ | |
448 | static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y) | |
71e8831f AG |
449 | { |
450 | u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment; | |
451 | ||
452 | x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft; | |
453 | y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft; | |
454 | alignment = geom[fmt].x_shft + geom[fmt].y_shft; | |
455 | ||
456 | /* validate coordinate */ | |
457 | x_mask = MASK(x_bits); | |
458 | y_mask = MASK(y_bits); | |
459 | ||
3c810c61 RC |
460 | if (x < 0 || x > x_mask || y < 0 || y > y_mask) { |
461 | DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u", | |
462 | x, x, x_mask, y, y, y_mask); | |
71e8831f | 463 | return 0; |
3c810c61 | 464 | } |
71e8831f AG |
465 | |
466 | /* account for mirroring */ | |
467 | if (orient & MASK_X_INVERT) | |
468 | x ^= x_mask; | |
469 | if (orient & MASK_Y_INVERT) | |
470 | y ^= y_mask; | |
471 | ||
472 | /* get coordinate address */ | |
473 | if (orient & MASK_XY_FLIP) | |
474 | tmp = ((x << y_bits) + y); | |
475 | else | |
476 | tmp = ((y << x_bits) + x); | |
477 | ||
478 | return TIL_ADDR((tmp << alignment), orient, fmt); | |
479 | } | |
480 | ||
481 | dma_addr_t tiler_ssptr(struct tiler_block *block) | |
482 | { | |
483 | BUG_ON(!validfmt(block->fmt)); | |
484 | ||
3c810c61 | 485 | return TILVIEW_8BIT + tiler_get_address(block->fmt, 0, |
71e8831f AG |
486 | block->area.p0.x * geom[block->fmt].slot_w, |
487 | block->area.p0.y * geom[block->fmt].slot_h); | |
488 | } | |
489 | ||
3c810c61 RC |
490 | dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, |
491 | uint32_t x, uint32_t y) | |
492 | { | |
493 | struct tcm_pt *p = &block->area.p0; | |
494 | BUG_ON(!validfmt(block->fmt)); | |
495 | ||
496 | return tiler_get_address(block->fmt, orient, | |
497 | (p->x * geom[block->fmt].slot_w) + x, | |
498 | (p->y * geom[block->fmt].slot_h) + y); | |
499 | } | |
500 | ||
71e8831f AG |
501 | void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h) |
502 | { | |
503 | BUG_ON(!validfmt(fmt)); | |
504 | *w = round_up(*w, geom[fmt].slot_w); | |
505 | *h = round_up(*h, geom[fmt].slot_h); | |
506 | } | |
507 | ||
3c810c61 | 508 | uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) |
71e8831f AG |
509 | { |
510 | BUG_ON(!validfmt(fmt)); | |
511 | ||
3c810c61 RC |
512 | if (orient & MASK_XY_FLIP) |
513 | return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft); | |
514 | else | |
515 | return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); | |
71e8831f AG |
516 | } |
517 | ||
518 | size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h) | |
519 | { | |
520 | tiler_align(fmt, &w, &h); | |
521 | return geom[fmt].cpp * w * h; | |
522 | } | |
523 | ||
524 | size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h) | |
525 | { | |
526 | BUG_ON(!validfmt(fmt)); | |
527 | return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; | |
528 | } | |
529 | ||
e5e4e9b7 | 530 | bool dmm_is_available(void) |
5c137797 AG |
531 | { |
532 | return omap_dmm ? true : false; | |
533 | } | |
534 | ||
535 | static int omap_dmm_remove(struct platform_device *dev) | |
71e8831f AG |
536 | { |
537 | struct tiler_block *block, *_block; | |
538 | int i; | |
faaa0540 | 539 | unsigned long flags; |
71e8831f AG |
540 | |
541 | if (omap_dmm) { | |
542 | /* free all area regions */ | |
faaa0540 | 543 | spin_lock_irqsave(&list_lock, flags); |
71e8831f AG |
544 | list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head, |
545 | alloc_node) { | |
546 | list_del(&block->alloc_node); | |
547 | kfree(block); | |
548 | } | |
faaa0540 | 549 | spin_unlock_irqrestore(&list_lock, flags); |
71e8831f AG |
550 | |
551 | for (i = 0; i < omap_dmm->num_lut; i++) | |
552 | if (omap_dmm->tcm && omap_dmm->tcm[i]) | |
553 | omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]); | |
554 | kfree(omap_dmm->tcm); | |
555 | ||
556 | kfree(omap_dmm->engines); | |
557 | if (omap_dmm->refill_va) | |
fe4fc163 | 558 | dma_free_writecombine(omap_dmm->dev, |
71e8831f AG |
559 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
560 | omap_dmm->refill_va, | |
561 | omap_dmm->refill_pa); | |
562 | if (omap_dmm->dummy_page) | |
563 | __free_page(omap_dmm->dummy_page); | |
564 | ||
ef445934 | 565 | if (omap_dmm->irq > 0) |
71e8831f AG |
566 | free_irq(omap_dmm->irq, omap_dmm); |
567 | ||
5c137797 | 568 | iounmap(omap_dmm->base); |
71e8831f | 569 | kfree(omap_dmm); |
5c137797 | 570 | omap_dmm = NULL; |
71e8831f AG |
571 | } |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
5c137797 | 576 | static int omap_dmm_probe(struct platform_device *dev) |
71e8831f AG |
577 | { |
578 | int ret = -EFAULT, i; | |
579 | struct tcm_area area = {0}; | |
0f562d16 | 580 | u32 hwinfo, pat_geom; |
5c137797 | 581 | struct resource *mem; |
71e8831f AG |
582 | |
583 | omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL); | |
78110bb8 | 584 | if (!omap_dmm) |
71e8831f | 585 | goto fail; |
71e8831f | 586 | |
ef445934 AG |
587 | /* initialize lists */ |
588 | INIT_LIST_HEAD(&omap_dmm->alloc_head); | |
589 | INIT_LIST_HEAD(&omap_dmm->idle_head); | |
590 | ||
faaa0540 AG |
591 | init_waitqueue_head(&omap_dmm->engine_queue); |
592 | ||
71e8831f | 593 | /* lookup hwmod data - base address and irq */ |
5c137797 AG |
594 | mem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
595 | if (!mem) { | |
596 | dev_err(&dev->dev, "failed to get base address resource\n"); | |
597 | goto fail; | |
598 | } | |
599 | ||
600 | omap_dmm->base = ioremap(mem->start, SZ_2K); | |
71e8831f AG |
601 | |
602 | if (!omap_dmm->base) { | |
5c137797 | 603 | dev_err(&dev->dev, "failed to get dmm base address\n"); |
71e8831f AG |
604 | goto fail; |
605 | } | |
606 | ||
5c137797 AG |
607 | omap_dmm->irq = platform_get_irq(dev, 0); |
608 | if (omap_dmm->irq < 0) { | |
609 | dev_err(&dev->dev, "failed to get IRQ resource\n"); | |
610 | goto fail; | |
611 | } | |
612 | ||
613 | omap_dmm->dev = &dev->dev; | |
614 | ||
71e8831f AG |
615 | hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO); |
616 | omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; | |
617 | omap_dmm->num_lut = (hwinfo >> 16) & 0x1F; | |
618 | omap_dmm->container_width = 256; | |
619 | omap_dmm->container_height = 128; | |
620 | ||
faaa0540 AG |
621 | atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); |
622 | ||
71e8831f AG |
623 | /* read out actual LUT width and height */ |
624 | pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY); | |
625 | omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5; | |
626 | omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5; | |
627 | ||
c6b7ae55 AG |
628 | /* increment LUT by one if on OMAP5 */ |
629 | /* LUT has twice the height, and is split into a separate container */ | |
630 | if (omap_dmm->lut_height != omap_dmm->container_height) | |
631 | omap_dmm->num_lut++; | |
632 | ||
71e8831f AG |
633 | /* initialize DMM registers */ |
634 | writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0); | |
635 | writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1); | |
636 | writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0); | |
637 | writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE); | |
638 | writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0); | |
639 | writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1); | |
640 | ||
641 | ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED, | |
642 | "omap_dmm_irq_handler", omap_dmm); | |
643 | ||
644 | if (ret) { | |
5c137797 | 645 | dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n", |
71e8831f AG |
646 | omap_dmm->irq, ret); |
647 | omap_dmm->irq = -1; | |
648 | goto fail; | |
649 | } | |
650 | ||
a6a91827 RC |
651 | /* Enable all interrupts for each refill engine except |
652 | * ERR_LUT_MISS<n> (which is just advisory, and we don't care | |
653 | * about because we want to be able to refill live scanout | |
654 | * buffers for accelerated pan/scroll) and FILL_DSC<n> which | |
655 | * we just generally don't care about. | |
656 | */ | |
657 | writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET); | |
71e8831f | 658 | |
71e8831f AG |
659 | omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32); |
660 | if (!omap_dmm->dummy_page) { | |
5c137797 | 661 | dev_err(&dev->dev, "could not allocate dummy page\n"); |
71e8831f AG |
662 | ret = -ENOMEM; |
663 | goto fail; | |
664 | } | |
5c137797 AG |
665 | |
666 | /* set dma mask for device */ | |
667 | /* NOTE: this is a workaround for the hwmod not initializing properly */ | |
668 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
669 | ||
71e8831f AG |
670 | omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page); |
671 | ||
672 | /* alloc refill memory */ | |
fe4fc163 | 673 | omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev, |
71e8831f AG |
674 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
675 | &omap_dmm->refill_pa, GFP_KERNEL); | |
676 | if (!omap_dmm->refill_va) { | |
5c137797 | 677 | dev_err(&dev->dev, "could not allocate refill memory\n"); |
71e8831f AG |
678 | goto fail; |
679 | } | |
680 | ||
681 | /* alloc engines */ | |
78110bb8 JP |
682 | omap_dmm->engines = kcalloc(omap_dmm->num_engines, |
683 | sizeof(struct refill_engine), GFP_KERNEL); | |
71e8831f | 684 | if (!omap_dmm->engines) { |
71e8831f AG |
685 | ret = -ENOMEM; |
686 | goto fail; | |
687 | } | |
688 | ||
71e8831f AG |
689 | for (i = 0; i < omap_dmm->num_engines; i++) { |
690 | omap_dmm->engines[i].id = i; | |
691 | omap_dmm->engines[i].dmm = omap_dmm; | |
692 | omap_dmm->engines[i].refill_va = omap_dmm->refill_va + | |
693 | (REFILL_BUFFER_SIZE * i); | |
694 | omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + | |
695 | (REFILL_BUFFER_SIZE * i); | |
696 | init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill); | |
697 | ||
698 | list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); | |
699 | } | |
700 | ||
78110bb8 | 701 | omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm), |
71e8831f AG |
702 | GFP_KERNEL); |
703 | if (!omap_dmm->tcm) { | |
71e8831f AG |
704 | ret = -ENOMEM; |
705 | goto fail; | |
706 | } | |
707 | ||
708 | /* init containers */ | |
c6b7ae55 AG |
709 | /* Each LUT is associated with a TCM (container manager). We use the |
710 | lut_id to denote the lut_id used to identify the correct LUT for | |
711 | programming during reill operations */ | |
71e8831f AG |
712 | for (i = 0; i < omap_dmm->num_lut; i++) { |
713 | omap_dmm->tcm[i] = sita_init(omap_dmm->container_width, | |
714 | omap_dmm->container_height, | |
715 | NULL); | |
716 | ||
717 | if (!omap_dmm->tcm[i]) { | |
5c137797 | 718 | dev_err(&dev->dev, "failed to allocate container\n"); |
71e8831f AG |
719 | ret = -ENOMEM; |
720 | goto fail; | |
721 | } | |
722 | ||
723 | omap_dmm->tcm[i]->lut_id = i; | |
724 | } | |
725 | ||
726 | /* assign access mode containers to applicable tcm container */ | |
727 | /* OMAP 4 has 1 container for all 4 views */ | |
c6b7ae55 | 728 | /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */ |
71e8831f AG |
729 | containers[TILFMT_8BIT] = omap_dmm->tcm[0]; |
730 | containers[TILFMT_16BIT] = omap_dmm->tcm[0]; | |
731 | containers[TILFMT_32BIT] = omap_dmm->tcm[0]; | |
c6b7ae55 AG |
732 | |
733 | if (omap_dmm->container_height != omap_dmm->lut_height) { | |
734 | /* second LUT is used for PAGE mode. Programming must use | |
735 | y offset that is added to all y coordinates. LUT id is still | |
736 | 0, because it is the same LUT, just the upper 128 lines */ | |
737 | containers[TILFMT_PAGE] = omap_dmm->tcm[1]; | |
738 | omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET; | |
739 | omap_dmm->tcm[1]->lut_id = 0; | |
740 | } else { | |
741 | containers[TILFMT_PAGE] = omap_dmm->tcm[0]; | |
742 | } | |
71e8831f | 743 | |
71e8831f | 744 | area = (struct tcm_area) { |
71e8831f AG |
745 | .tcm = NULL, |
746 | .p1.x = omap_dmm->container_width - 1, | |
747 | .p1.y = omap_dmm->container_height - 1, | |
748 | }; | |
749 | ||
71e8831f AG |
750 | /* initialize all LUTs to dummy page entries */ |
751 | for (i = 0; i < omap_dmm->num_lut; i++) { | |
752 | area.tcm = omap_dmm->tcm[i]; | |
a6a91827 | 753 | if (fill(&area, NULL, 0, 0, true)) |
71e8831f AG |
754 | dev_err(omap_dmm->dev, "refill failed"); |
755 | } | |
756 | ||
757 | dev_info(omap_dmm->dev, "initialized all PAT entries\n"); | |
758 | ||
759 | return 0; | |
760 | ||
761 | fail: | |
ef445934 AG |
762 | if (omap_dmm_remove(dev)) |
763 | dev_err(&dev->dev, "cleanup failed\n"); | |
71e8831f AG |
764 | return ret; |
765 | } | |
6169a148 AG |
766 | |
767 | /* | |
768 | * debugfs support | |
769 | */ | |
770 | ||
771 | #ifdef CONFIG_DEBUG_FS | |
772 | ||
773 | static const char *alphabet = "abcdefghijklmnopqrstuvwxyz" | |
774 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; | |
775 | static const char *special = ".,:;'\"`~!^-+"; | |
776 | ||
777 | static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a, | |
778 | char c, bool ovw) | |
779 | { | |
780 | int x, y; | |
781 | for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) | |
782 | for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) | |
783 | if (map[y][x] == ' ' || ovw) | |
784 | map[y][x] = c; | |
785 | } | |
786 | ||
787 | static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p, | |
788 | char c) | |
789 | { | |
790 | map[p->y / ydiv][p->x / xdiv] = c; | |
791 | } | |
792 | ||
793 | static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p) | |
794 | { | |
795 | return map[p->y / ydiv][p->x / xdiv]; | |
796 | } | |
797 | ||
798 | static int map_width(int xdiv, int x0, int x1) | |
799 | { | |
800 | return (x1 / xdiv) - (x0 / xdiv) + 1; | |
801 | } | |
802 | ||
803 | static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1) | |
804 | { | |
805 | char *p = map[yd] + (x0 / xdiv); | |
806 | int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2; | |
807 | if (w >= 0) { | |
808 | p += w; | |
809 | while (*nice) | |
810 | *p++ = *nice++; | |
811 | } | |
812 | } | |
813 | ||
814 | static void map_1d_info(char **map, int xdiv, int ydiv, char *nice, | |
815 | struct tcm_area *a) | |
816 | { | |
817 | sprintf(nice, "%dK", tcm_sizeof(*a) * 4); | |
818 | if (a->p0.y + 1 < a->p1.y) { | |
819 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, | |
820 | 256 - 1); | |
821 | } else if (a->p0.y < a->p1.y) { | |
822 | if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1)) | |
823 | text_map(map, xdiv, nice, a->p0.y / ydiv, | |
824 | a->p0.x + xdiv, 256 - 1); | |
825 | else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) | |
826 | text_map(map, xdiv, nice, a->p1.y / ydiv, | |
827 | 0, a->p1.y - xdiv); | |
828 | } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) { | |
829 | text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x); | |
830 | } | |
831 | } | |
832 | ||
833 | static void map_2d_info(char **map, int xdiv, int ydiv, char *nice, | |
834 | struct tcm_area *a) | |
835 | { | |
836 | sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a)); | |
837 | if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) | |
838 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, | |
839 | a->p0.x, a->p1.x); | |
840 | } | |
841 | ||
842 | int tiler_map_show(struct seq_file *s, void *arg) | |
843 | { | |
844 | int xdiv = 2, ydiv = 1; | |
845 | char **map = NULL, *global_map; | |
846 | struct tiler_block *block; | |
847 | struct tcm_area a, p; | |
848 | int i; | |
849 | const char *m2d = alphabet; | |
850 | const char *a2d = special; | |
851 | const char *m2dp = m2d, *a2dp = a2d; | |
852 | char nice[128]; | |
02646fb8 AG |
853 | int h_adj; |
854 | int w_adj; | |
6169a148 | 855 | unsigned long flags; |
c6b7ae55 AG |
856 | int lut_idx; |
857 | ||
6169a148 | 858 | |
02646fb8 AG |
859 | if (!omap_dmm) { |
860 | /* early return if dmm/tiler device is not initialized */ | |
861 | return 0; | |
862 | } | |
863 | ||
c6b7ae55 AG |
864 | h_adj = omap_dmm->container_height / ydiv; |
865 | w_adj = omap_dmm->container_width / xdiv; | |
02646fb8 | 866 | |
c6b7ae55 AG |
867 | map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL); |
868 | global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL); | |
6169a148 AG |
869 | |
870 | if (!map || !global_map) | |
871 | goto error; | |
872 | ||
c6b7ae55 AG |
873 | for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) { |
874 | memset(map, 0, sizeof(h_adj * sizeof(*map))); | |
875 | memset(global_map, ' ', (w_adj + 1) * h_adj); | |
6169a148 | 876 | |
c6b7ae55 AG |
877 | for (i = 0; i < omap_dmm->container_height; i++) { |
878 | map[i] = global_map + i * (w_adj + 1); | |
879 | map[i][w_adj] = 0; | |
880 | } | |
881 | ||
882 | spin_lock_irqsave(&list_lock, flags); | |
883 | ||
884 | list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) { | |
885 | if (block->area.tcm == omap_dmm->tcm[lut_idx]) { | |
886 | if (block->fmt != TILFMT_PAGE) { | |
887 | fill_map(map, xdiv, ydiv, &block->area, | |
888 | *m2dp, true); | |
889 | if (!*++a2dp) | |
890 | a2dp = a2d; | |
891 | if (!*++m2dp) | |
892 | m2dp = m2d; | |
893 | map_2d_info(map, xdiv, ydiv, nice, | |
894 | &block->area); | |
895 | } else { | |
896 | bool start = read_map_pt(map, xdiv, | |
897 | ydiv, &block->area.p0) == ' '; | |
898 | bool end = read_map_pt(map, xdiv, ydiv, | |
899 | &block->area.p1) == ' '; | |
900 | ||
901 | tcm_for_each_slice(a, block->area, p) | |
902 | fill_map(map, xdiv, ydiv, &a, | |
903 | '=', true); | |
904 | fill_map_pt(map, xdiv, ydiv, | |
905 | &block->area.p0, | |
6169a148 | 906 | start ? '<' : 'X'); |
c6b7ae55 AG |
907 | fill_map_pt(map, xdiv, ydiv, |
908 | &block->area.p1, | |
6169a148 | 909 | end ? '>' : 'X'); |
c6b7ae55 AG |
910 | map_1d_info(map, xdiv, ydiv, nice, |
911 | &block->area); | |
912 | } | |
913 | } | |
6169a148 | 914 | } |
6169a148 | 915 | |
c6b7ae55 | 916 | spin_unlock_irqrestore(&list_lock, flags); |
6169a148 | 917 | |
c6b7ae55 AG |
918 | if (s) { |
919 | seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx); | |
920 | for (i = 0; i < 128; i++) | |
921 | seq_printf(s, "%03d:%s\n", i, map[i]); | |
922 | seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx); | |
923 | } else { | |
924 | dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n", | |
925 | lut_idx); | |
926 | for (i = 0; i < 128; i++) | |
927 | dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]); | |
928 | dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n", | |
929 | lut_idx); | |
930 | } | |
6169a148 AG |
931 | } |
932 | ||
933 | error: | |
934 | kfree(map); | |
935 | kfree(global_map); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | #endif | |
5c137797 | 940 | |
e78edba1 AG |
941 | #ifdef CONFIG_PM |
942 | static int omap_dmm_resume(struct device *dev) | |
943 | { | |
944 | struct tcm_area area; | |
945 | int i; | |
946 | ||
947 | if (!omap_dmm) | |
948 | return -ENODEV; | |
949 | ||
950 | area = (struct tcm_area) { | |
e78edba1 AG |
951 | .tcm = NULL, |
952 | .p1.x = omap_dmm->container_width - 1, | |
953 | .p1.y = omap_dmm->container_height - 1, | |
954 | }; | |
955 | ||
956 | /* initialize all LUTs to dummy page entries */ | |
957 | for (i = 0; i < omap_dmm->num_lut; i++) { | |
958 | area.tcm = omap_dmm->tcm[i]; | |
959 | if (fill(&area, NULL, 0, 0, true)) | |
960 | dev_err(dev, "refill failed"); | |
961 | } | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static const struct dev_pm_ops omap_dmm_pm_ops = { | |
967 | .resume = omap_dmm_resume, | |
968 | }; | |
969 | #endif | |
970 | ||
5c137797 AG |
971 | struct platform_driver omap_dmm_driver = { |
972 | .probe = omap_dmm_probe, | |
973 | .remove = omap_dmm_remove, | |
974 | .driver = { | |
975 | .owner = THIS_MODULE, | |
976 | .name = DMM_DRIVER_NAME, | |
e78edba1 AG |
977 | #ifdef CONFIG_PM |
978 | .pm = &omap_dmm_pm_ops, | |
979 | #endif | |
5c137797 AG |
980 | }, |
981 | }; | |
982 | ||
983 | MODULE_LICENSE("GPL v2"); | |
984 | MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>"); | |
985 | MODULE_DESCRIPTION("OMAP DMM/Tiler Driver"); | |
986 | MODULE_ALIAS("platform:" DMM_DRIVER_NAME); |