Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
748471a5 LP |
20 | #include <linux/wait.h> |
21 | ||
22 | #include <drm/drm_atomic.h> | |
cef77d40 | 23 | #include <drm/drm_atomic_helper.h> |
2d278f54 LP |
24 | #include <drm/drm_crtc_helper.h> |
25 | #include <drm/drm_fb_helper.h> | |
cd5351f4 | 26 | |
5c137797 | 27 | #include "omap_dmm_tiler.h" |
2d278f54 | 28 | #include "omap_drv.h" |
cd5351f4 RC |
29 | |
30 | #define DRIVER_NAME MODULE_NAME | |
31 | #define DRIVER_DESC "OMAP DRM" | |
32 | #define DRIVER_DATE "20110917" | |
33 | #define DRIVER_MAJOR 1 | |
34 | #define DRIVER_MINOR 0 | |
35 | #define DRIVER_PATCHLEVEL 0 | |
36 | ||
cd5351f4 RC |
37 | static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; |
38 | ||
39 | MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); | |
40 | module_param(num_crtc, int, 0600); | |
41 | ||
42 | /* | |
43 | * mode config funcs | |
44 | */ | |
45 | ||
46 | /* Notes about mapping DSS and DRM entities: | |
47 | * CRTC: overlay | |
48 | * encoder: manager.. with some extension to allow one primary CRTC | |
49 | * and zero or more video CRTC's to be mapped to one encoder? | |
50 | * connector: dssdev.. manager can be attached/detached from different | |
51 | * devices | |
52 | */ | |
53 | ||
54 | static void omap_fb_output_poll_changed(struct drm_device *dev) | |
55 | { | |
56 | struct omap_drm_private *priv = dev->dev_private; | |
57 | DBG("dev=%p", dev); | |
c7f904b3 | 58 | if (priv->fbdev) |
cd5351f4 | 59 | drm_fb_helper_hotplug_event(priv->fbdev); |
cd5351f4 RC |
60 | } |
61 | ||
748471a5 LP |
62 | struct omap_atomic_state_commit { |
63 | struct work_struct work; | |
64 | struct drm_device *dev; | |
65 | struct drm_atomic_state *state; | |
66 | u32 crtcs; | |
67 | }; | |
68 | ||
5f741b39 TV |
69 | static void omap_atomic_wait_for_completion(struct drm_device *dev, |
70 | struct drm_atomic_state *old_state) | |
71 | { | |
72 | struct drm_crtc_state *old_crtc_state; | |
73 | struct drm_crtc *crtc; | |
74 | unsigned int i; | |
75 | int ret; | |
76 | ||
77 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { | |
78 | if (!crtc->state->enable) | |
79 | continue; | |
80 | ||
81 | ret = omap_crtc_wait_pending(crtc); | |
82 | ||
83 | if (!ret) | |
84 | dev_warn(dev->dev, | |
85 | "atomic complete timeout (pipe %u)!\n", i); | |
86 | } | |
87 | } | |
88 | ||
748471a5 LP |
89 | static void omap_atomic_complete(struct omap_atomic_state_commit *commit) |
90 | { | |
91 | struct drm_device *dev = commit->dev; | |
92 | struct omap_drm_private *priv = dev->dev_private; | |
93 | struct drm_atomic_state *old_state = commit->state; | |
94 | ||
95 | /* Apply the atomic update. */ | |
69fb7c85 LP |
96 | dispc_runtime_get(); |
97 | ||
748471a5 | 98 | drm_atomic_helper_commit_modeset_disables(dev, old_state); |
aef9dbb8 | 99 | drm_atomic_helper_commit_planes(dev, old_state, false); |
748471a5 LP |
100 | drm_atomic_helper_commit_modeset_enables(dev, old_state); |
101 | ||
5f741b39 | 102 | omap_atomic_wait_for_completion(dev, old_state); |
748471a5 LP |
103 | |
104 | drm_atomic_helper_cleanup_planes(dev, old_state); | |
105 | ||
69fb7c85 LP |
106 | dispc_runtime_put(); |
107 | ||
748471a5 LP |
108 | drm_atomic_state_free(old_state); |
109 | ||
110 | /* Complete the commit, wake up any waiter. */ | |
111 | spin_lock(&priv->commit.lock); | |
112 | priv->commit.pending &= ~commit->crtcs; | |
113 | spin_unlock(&priv->commit.lock); | |
114 | ||
115 | wake_up_all(&priv->commit.wait); | |
116 | ||
117 | kfree(commit); | |
118 | } | |
119 | ||
120 | static void omap_atomic_work(struct work_struct *work) | |
121 | { | |
122 | struct omap_atomic_state_commit *commit = | |
123 | container_of(work, struct omap_atomic_state_commit, work); | |
124 | ||
125 | omap_atomic_complete(commit); | |
126 | } | |
127 | ||
128 | static bool omap_atomic_is_pending(struct omap_drm_private *priv, | |
129 | struct omap_atomic_state_commit *commit) | |
130 | { | |
131 | bool pending; | |
132 | ||
133 | spin_lock(&priv->commit.lock); | |
134 | pending = priv->commit.pending & commit->crtcs; | |
135 | spin_unlock(&priv->commit.lock); | |
136 | ||
137 | return pending; | |
138 | } | |
139 | ||
140 | static int omap_atomic_commit(struct drm_device *dev, | |
141 | struct drm_atomic_state *state, bool async) | |
142 | { | |
143 | struct omap_drm_private *priv = dev->dev_private; | |
144 | struct omap_atomic_state_commit *commit; | |
1cfe19aa | 145 | unsigned long flags; |
748471a5 LP |
146 | unsigned int i; |
147 | int ret; | |
148 | ||
149 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
153 | /* Allocate the commit object. */ | |
154 | commit = kzalloc(sizeof(*commit), GFP_KERNEL); | |
155 | if (commit == NULL) { | |
156 | ret = -ENOMEM; | |
157 | goto error; | |
158 | } | |
159 | ||
160 | INIT_WORK(&commit->work, omap_atomic_work); | |
161 | commit->dev = dev; | |
162 | commit->state = state; | |
163 | ||
164 | /* Wait until all affected CRTCs have completed previous commits and | |
165 | * mark them as pending. | |
166 | */ | |
167 | for (i = 0; i < dev->mode_config.num_crtc; ++i) { | |
168 | if (state->crtcs[i]) | |
169 | commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]); | |
170 | } | |
171 | ||
172 | wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit)); | |
173 | ||
174 | spin_lock(&priv->commit.lock); | |
175 | priv->commit.pending |= commit->crtcs; | |
176 | spin_unlock(&priv->commit.lock); | |
177 | ||
1cfe19aa LP |
178 | /* Keep track of all CRTC events to unlink them in preclose(). */ |
179 | spin_lock_irqsave(&dev->event_lock, flags); | |
180 | for (i = 0; i < dev->mode_config.num_crtc; ++i) { | |
181 | struct drm_crtc_state *cstate = state->crtc_states[i]; | |
182 | ||
183 | if (cstate && cstate->event) | |
184 | list_add_tail(&cstate->event->base.link, | |
185 | &priv->commit.events); | |
186 | } | |
187 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
188 | ||
748471a5 LP |
189 | /* Swap the state, this is the point of no return. */ |
190 | drm_atomic_helper_swap_state(dev, state); | |
191 | ||
192 | if (async) | |
193 | schedule_work(&commit->work); | |
194 | else | |
195 | omap_atomic_complete(commit); | |
196 | ||
197 | return 0; | |
198 | ||
199 | error: | |
200 | drm_atomic_helper_cleanup_planes(dev, state); | |
201 | return ret; | |
202 | } | |
203 | ||
e6ecefaa | 204 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 RC |
205 | .fb_create = omap_framebuffer_create, |
206 | .output_poll_changed = omap_fb_output_poll_changed, | |
cef77d40 | 207 | .atomic_check = drm_atomic_helper_check, |
748471a5 | 208 | .atomic_commit = omap_atomic_commit, |
cd5351f4 RC |
209 | }; |
210 | ||
211 | static int get_connector_type(struct omap_dss_device *dssdev) | |
212 | { | |
213 | switch (dssdev->type) { | |
214 | case OMAP_DISPLAY_TYPE_HDMI: | |
215 | return DRM_MODE_CONNECTOR_HDMIA; | |
4635c17d TV |
216 | case OMAP_DISPLAY_TYPE_DVI: |
217 | return DRM_MODE_CONNECTOR_DVID; | |
cd5351f4 RC |
218 | default: |
219 | return DRM_MODE_CONNECTOR_Unknown; | |
220 | } | |
221 | } | |
222 | ||
0d8f371f AT |
223 | static bool channel_used(struct drm_device *dev, enum omap_channel channel) |
224 | { | |
225 | struct omap_drm_private *priv = dev->dev_private; | |
226 | int i; | |
227 | ||
228 | for (i = 0; i < priv->num_crtcs; i++) { | |
229 | struct drm_crtc *crtc = priv->crtcs[i]; | |
230 | ||
231 | if (omap_crtc_channel(crtc) == channel) | |
232 | return true; | |
233 | } | |
234 | ||
235 | return false; | |
236 | } | |
cc823bdc AT |
237 | static void omap_disconnect_dssdevs(void) |
238 | { | |
239 | struct omap_dss_device *dssdev = NULL; | |
240 | ||
241 | for_each_dss_dev(dssdev) | |
242 | dssdev->driver->disconnect(dssdev); | |
243 | } | |
0d8f371f | 244 | |
3a01ab25 AT |
245 | static int omap_connect_dssdevs(void) |
246 | { | |
247 | int r; | |
248 | struct omap_dss_device *dssdev = NULL; | |
249 | bool no_displays = true; | |
250 | ||
251 | for_each_dss_dev(dssdev) { | |
252 | r = dssdev->driver->connect(dssdev); | |
253 | if (r == -EPROBE_DEFER) { | |
254 | omap_dss_put_device(dssdev); | |
255 | goto cleanup; | |
256 | } else if (r) { | |
257 | dev_warn(dssdev->dev, "could not connect display: %s\n", | |
258 | dssdev->name); | |
259 | } else { | |
260 | no_displays = false; | |
261 | } | |
262 | } | |
263 | ||
264 | if (no_displays) | |
265 | return -EPROBE_DEFER; | |
266 | ||
267 | return 0; | |
268 | ||
269 | cleanup: | |
270 | /* | |
271 | * if we are deferring probe, we disconnect the devices we previously | |
272 | * connected | |
273 | */ | |
cc823bdc | 274 | omap_disconnect_dssdevs(); |
3a01ab25 AT |
275 | |
276 | return r; | |
277 | } | |
0d8f371f | 278 | |
fb9a35f8 LP |
279 | static int omap_modeset_create_crtc(struct drm_device *dev, int id, |
280 | enum omap_channel channel) | |
281 | { | |
282 | struct omap_drm_private *priv = dev->dev_private; | |
283 | struct drm_plane *plane; | |
284 | struct drm_crtc *crtc; | |
285 | ||
ef6b0e02 | 286 | plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY); |
fb9a35f8 LP |
287 | if (IS_ERR(plane)) |
288 | return PTR_ERR(plane); | |
289 | ||
290 | crtc = omap_crtc_init(dev, plane, channel, id); | |
291 | ||
292 | BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); | |
293 | priv->crtcs[id] = crtc; | |
294 | priv->num_crtcs++; | |
295 | ||
296 | priv->planes[id] = plane; | |
297 | priv->num_planes++; | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
e2cd09b2 LP |
302 | static int omap_modeset_init_properties(struct drm_device *dev) |
303 | { | |
304 | struct omap_drm_private *priv = dev->dev_private; | |
305 | ||
306 | if (priv->has_dmm) { | |
307 | dev->mode_config.rotation_property = | |
308 | drm_mode_create_rotation_property(dev, | |
309 | BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | | |
310 | BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) | | |
311 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)); | |
312 | if (!dev->mode_config.rotation_property) | |
313 | return -ENOMEM; | |
314 | } | |
315 | ||
316 | priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3); | |
317 | if (!priv->zorder_prop) | |
318 | return -ENOMEM; | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
f5f9454c | 323 | static int omap_modeset_init(struct drm_device *dev) |
cd5351f4 RC |
324 | { |
325 | struct omap_drm_private *priv = dev->dev_private; | |
f5f9454c RC |
326 | struct omap_dss_device *dssdev = NULL; |
327 | int num_ovls = dss_feat_get_num_ovls(); | |
0d8f371f AT |
328 | int num_mgrs = dss_feat_get_num_mgrs(); |
329 | int num_crtcs; | |
330 | int i, id = 0; | |
fb9a35f8 | 331 | int ret; |
04b1fc02 | 332 | |
f5f9454c | 333 | drm_mode_config_init(dev); |
cd5351f4 | 334 | |
f5f9454c | 335 | omap_drm_irq_install(dev); |
cd5351f4 | 336 | |
e2cd09b2 LP |
337 | ret = omap_modeset_init_properties(dev); |
338 | if (ret < 0) | |
339 | return ret; | |
340 | ||
f5f9454c | 341 | /* |
0d8f371f AT |
342 | * We usually don't want to create a CRTC for each manager, at least |
343 | * not until we have a way to expose private planes to userspace. | |
344 | * Otherwise there would not be enough video pipes left for drm planes. | |
345 | * We use the num_crtc argument to limit the number of crtcs we create. | |
f5f9454c | 346 | */ |
0d8f371f | 347 | num_crtcs = min3(num_crtc, num_mgrs, num_ovls); |
cd5351f4 | 348 | |
0d8f371f | 349 | dssdev = NULL; |
cd5351f4 | 350 | |
f5f9454c RC |
351 | for_each_dss_dev(dssdev) { |
352 | struct drm_connector *connector; | |
353 | struct drm_encoder *encoder; | |
0d8f371f | 354 | enum omap_channel channel; |
a7e71e7f | 355 | struct omap_overlay_manager *mgr; |
c7f904b3 | 356 | |
3a01ab25 | 357 | if (!omapdss_device_is_connected(dssdev)) |
581382e3 | 358 | continue; |
a7e71e7f | 359 | |
f5f9454c | 360 | encoder = omap_encoder_init(dev, dssdev); |
cd5351f4 | 361 | |
f5f9454c RC |
362 | if (!encoder) { |
363 | dev_err(dev->dev, "could not create encoder: %s\n", | |
364 | dssdev->name); | |
365 | return -ENOMEM; | |
cd5351f4 RC |
366 | } |
367 | ||
f5f9454c RC |
368 | connector = omap_connector_init(dev, |
369 | get_connector_type(dssdev), dssdev, encoder); | |
cd5351f4 | 370 | |
f5f9454c RC |
371 | if (!connector) { |
372 | dev_err(dev->dev, "could not create connector: %s\n", | |
373 | dssdev->name); | |
374 | return -ENOMEM; | |
cd5351f4 | 375 | } |
bb5c2d9a | 376 | |
f5f9454c RC |
377 | BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); |
378 | BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); | |
cd5351f4 | 379 | |
f5f9454c RC |
380 | priv->encoders[priv->num_encoders++] = encoder; |
381 | priv->connectors[priv->num_connectors++] = connector; | |
cd5351f4 | 382 | |
f5f9454c | 383 | drm_mode_connector_attach_encoder(connector, encoder); |
cd5351f4 | 384 | |
0d8f371f AT |
385 | /* |
386 | * if we have reached the limit of the crtcs we are allowed to | |
387 | * create, let's not try to look for a crtc for this | |
388 | * panel/encoder and onwards, we will, of course, populate the | |
389 | * the possible_crtcs field for all the encoders with the final | |
390 | * set of crtcs we create | |
391 | */ | |
392 | if (id == num_crtcs) | |
393 | continue; | |
394 | ||
395 | /* | |
396 | * get the recommended DISPC channel for this encoder. For now, | |
397 | * we only try to get create a crtc out of the recommended, the | |
398 | * other possible channels to which the encoder can connect are | |
399 | * not considered. | |
400 | */ | |
0d8f371f | 401 | |
a7e71e7f TV |
402 | mgr = omapdss_find_mgr_from_display(dssdev); |
403 | channel = mgr->id; | |
0d8f371f AT |
404 | /* |
405 | * if this channel hasn't already been taken by a previously | |
406 | * allocated crtc, we create a new crtc for it | |
407 | */ | |
408 | if (!channel_used(dev, channel)) { | |
fb9a35f8 LP |
409 | ret = omap_modeset_create_crtc(dev, id, channel); |
410 | if (ret < 0) { | |
411 | dev_err(dev->dev, | |
412 | "could not create CRTC (channel %u)\n", | |
413 | channel); | |
414 | return ret; | |
415 | } | |
0d8f371f AT |
416 | |
417 | id++; | |
418 | } | |
419 | } | |
420 | ||
421 | /* | |
422 | * we have allocated crtcs according to the need of the panels/encoders, | |
423 | * adding more crtcs here if needed | |
424 | */ | |
425 | for (; id < num_crtcs; id++) { | |
426 | ||
427 | /* find a free manager for this crtc */ | |
428 | for (i = 0; i < num_mgrs; i++) { | |
fb9a35f8 | 429 | if (!channel_used(dev, i)) |
0d8f371f | 430 | break; |
0d8f371f AT |
431 | } |
432 | ||
433 | if (i == num_mgrs) { | |
434 | /* this shouldn't really happen */ | |
435 | dev_err(dev->dev, "no managers left for crtc\n"); | |
436 | return -ENOMEM; | |
437 | } | |
fb9a35f8 LP |
438 | |
439 | ret = omap_modeset_create_crtc(dev, id, i); | |
440 | if (ret < 0) { | |
441 | dev_err(dev->dev, | |
442 | "could not create CRTC (channel %u)\n", i); | |
443 | return ret; | |
444 | } | |
0d8f371f AT |
445 | } |
446 | ||
447 | /* | |
448 | * Create normal planes for the remaining overlays: | |
449 | */ | |
450 | for (; id < num_ovls; id++) { | |
fb9a35f8 LP |
451 | struct drm_plane *plane; |
452 | ||
ef6b0e02 | 453 | plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY); |
fb9a35f8 LP |
454 | if (IS_ERR(plane)) |
455 | return PTR_ERR(plane); | |
0d8f371f AT |
456 | |
457 | BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); | |
458 | priv->planes[priv->num_planes++] = plane; | |
459 | } | |
460 | ||
461 | for (i = 0; i < priv->num_encoders; i++) { | |
462 | struct drm_encoder *encoder = priv->encoders[i]; | |
463 | struct omap_dss_device *dssdev = | |
464 | omap_encoder_get_dssdev(encoder); | |
1f68d9c4 | 465 | struct omap_dss_device *output; |
be8e8e1c TV |
466 | |
467 | output = omapdss_find_output_from_display(dssdev); | |
0d8f371f | 468 | |
f5f9454c RC |
469 | /* figure out which crtc's we can connect the encoder to: */ |
470 | encoder->possible_crtcs = 0; | |
471 | for (id = 0; id < priv->num_crtcs; id++) { | |
0d8f371f AT |
472 | struct drm_crtc *crtc = priv->crtcs[id]; |
473 | enum omap_channel crtc_channel; | |
0d8f371f AT |
474 | |
475 | crtc_channel = omap_crtc_channel(crtc); | |
0d8f371f | 476 | |
17337297 | 477 | if (output->dispc_channel == crtc_channel) { |
f5f9454c | 478 | encoder->possible_crtcs |= (1 << id); |
17337297 TV |
479 | break; |
480 | } | |
bb5c2d9a | 481 | } |
820caabf TV |
482 | |
483 | omap_dss_put_device(output); | |
cd5351f4 RC |
484 | } |
485 | ||
0d8f371f AT |
486 | DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", |
487 | priv->num_planes, priv->num_crtcs, priv->num_encoders, | |
488 | priv->num_connectors); | |
489 | ||
6b8ca4cf RC |
490 | dev->mode_config.min_width = 32; |
491 | dev->mode_config.min_height = 32; | |
cd5351f4 RC |
492 | |
493 | /* note: eventually will need some cpu_is_omapXYZ() type stuff here | |
494 | * to fill in these limits properly on different OMAP generations.. | |
495 | */ | |
496 | dev->mode_config.max_width = 2048; | |
497 | dev->mode_config.max_height = 2048; | |
498 | ||
499 | dev->mode_config.funcs = &omap_mode_config_funcs; | |
500 | ||
69a12263 LP |
501 | drm_mode_config_reset(dev); |
502 | ||
cd5351f4 RC |
503 | return 0; |
504 | } | |
505 | ||
506 | static void omap_modeset_free(struct drm_device *dev) | |
507 | { | |
508 | drm_mode_config_cleanup(dev); | |
509 | } | |
510 | ||
511 | /* | |
512 | * drm ioctl funcs | |
513 | */ | |
514 | ||
515 | ||
516 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
517 | struct drm_file *file_priv) | |
518 | { | |
5e3b0874 | 519 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 RC |
520 | struct drm_omap_param *args = data; |
521 | ||
522 | DBG("%p: param=%llu", dev, args->param); | |
523 | ||
524 | switch (args->param) { | |
525 | case OMAP_PARAM_CHIPSET_ID: | |
5e3b0874 | 526 | args->value = priv->omaprev; |
cd5351f4 RC |
527 | break; |
528 | default: | |
529 | DBG("unknown parameter %lld", args->param); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
537 | struct drm_file *file_priv) | |
538 | { | |
539 | struct drm_omap_param *args = data; | |
540 | ||
541 | switch (args->param) { | |
542 | default: | |
543 | DBG("unknown parameter %lld", args->param); | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
ef3f4e99 LP |
550 | #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */ |
551 | ||
cd5351f4 RC |
552 | static int ioctl_gem_new(struct drm_device *dev, void *data, |
553 | struct drm_file *file_priv) | |
554 | { | |
555 | struct drm_omap_gem_new *args = data; | |
ef3f4e99 LP |
556 | u32 flags = args->flags & OMAP_BO_USER_MASK; |
557 | ||
f5f9454c | 558 | VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, |
ef3f4e99 LP |
559 | args->size.bytes, flags); |
560 | ||
561 | return omap_gem_new_handle(dev, file_priv, args->size, flags, | |
562 | &args->handle); | |
cd5351f4 RC |
563 | } |
564 | ||
565 | static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
566 | struct drm_file *file_priv) | |
567 | { | |
568 | struct drm_omap_gem_cpu_prep *args = data; | |
569 | struct drm_gem_object *obj; | |
570 | int ret; | |
571 | ||
572 | VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); | |
573 | ||
574 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 575 | if (!obj) |
cd5351f4 | 576 | return -ENOENT; |
cd5351f4 RC |
577 | |
578 | ret = omap_gem_op_sync(obj, args->op); | |
579 | ||
c7f904b3 | 580 | if (!ret) |
cd5351f4 | 581 | ret = omap_gem_op_start(obj, args->op); |
cd5351f4 RC |
582 | |
583 | drm_gem_object_unreference_unlocked(obj); | |
584 | ||
585 | return ret; | |
586 | } | |
587 | ||
588 | static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
589 | struct drm_file *file_priv) | |
590 | { | |
591 | struct drm_omap_gem_cpu_fini *args = data; | |
592 | struct drm_gem_object *obj; | |
593 | int ret; | |
594 | ||
595 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); | |
596 | ||
597 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 598 | if (!obj) |
cd5351f4 | 599 | return -ENOENT; |
cd5351f4 RC |
600 | |
601 | /* XXX flushy, flushy */ | |
602 | ret = 0; | |
603 | ||
c7f904b3 | 604 | if (!ret) |
cd5351f4 | 605 | ret = omap_gem_op_finish(obj, args->op); |
cd5351f4 RC |
606 | |
607 | drm_gem_object_unreference_unlocked(obj); | |
608 | ||
609 | return ret; | |
610 | } | |
611 | ||
612 | static int ioctl_gem_info(struct drm_device *dev, void *data, | |
613 | struct drm_file *file_priv) | |
614 | { | |
615 | struct drm_omap_gem_info *args = data; | |
616 | struct drm_gem_object *obj; | |
617 | int ret = 0; | |
618 | ||
f5f9454c | 619 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); |
cd5351f4 RC |
620 | |
621 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 622 | if (!obj) |
cd5351f4 | 623 | return -ENOENT; |
cd5351f4 | 624 | |
f7f9f453 | 625 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
626 | args->offset = omap_gem_mmap_offset(obj); |
627 | ||
628 | drm_gem_object_unreference_unlocked(obj); | |
629 | ||
630 | return ret; | |
631 | } | |
632 | ||
baa70943 | 633 | static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { |
f8c47144 DV |
634 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH), |
635 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
636 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH), | |
637 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH), | |
638 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH), | |
639 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH), | |
cd5351f4 RC |
640 | }; |
641 | ||
642 | /* | |
643 | * drm driver funcs | |
644 | */ | |
645 | ||
646 | /** | |
647 | * load - setup chip and create an initial config | |
648 | * @dev: DRM device | |
649 | * @flags: startup flags | |
650 | * | |
651 | * The driver load routine has to do several things: | |
652 | * - initialize the memory manager | |
653 | * - allocate initial config memory | |
654 | * - setup the DRM framebuffer with the allocated memory | |
655 | */ | |
656 | static int dev_load(struct drm_device *dev, unsigned long flags) | |
657 | { | |
5e3b0874 | 658 | struct omap_drm_platform_data *pdata = dev->dev->platform_data; |
cd5351f4 | 659 | struct omap_drm_private *priv; |
c397cfd4 | 660 | unsigned int i; |
cd5351f4 RC |
661 | int ret; |
662 | ||
663 | DBG("load: dev=%p", dev); | |
664 | ||
cd5351f4 | 665 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
78110bb8 | 666 | if (!priv) |
cd5351f4 | 667 | return -ENOMEM; |
cd5351f4 | 668 | |
5e3b0874 RC |
669 | priv->omaprev = pdata->omaprev; |
670 | ||
cd5351f4 RC |
671 | dev->dev_private = priv; |
672 | ||
4619cdbc | 673 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
748471a5 LP |
674 | init_waitqueue_head(&priv->commit.wait); |
675 | spin_lock_init(&priv->commit.lock); | |
1cfe19aa | 676 | INIT_LIST_HEAD(&priv->commit.events); |
5609f7fe | 677 | |
76c4055f | 678 | spin_lock_init(&priv->list_lock); |
f6b6036e RC |
679 | INIT_LIST_HEAD(&priv->obj_list); |
680 | ||
f7f9f453 RC |
681 | omap_gem_init(dev); |
682 | ||
cd5351f4 RC |
683 | ret = omap_modeset_init(dev); |
684 | if (ret) { | |
685 | dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret); | |
686 | dev->dev_private = NULL; | |
687 | kfree(priv); | |
688 | return ret; | |
689 | } | |
690 | ||
c397cfd4 | 691 | /* Initialize vblank handling, start with all CRTCs disabled. */ |
f5f9454c RC |
692 | ret = drm_vblank_init(dev, priv->num_crtcs); |
693 | if (ret) | |
694 | dev_warn(dev->dev, "could not init vblank\n"); | |
695 | ||
c397cfd4 LP |
696 | for (i = 0; i < priv->num_crtcs; i++) |
697 | drm_crtc_vblank_off(priv->crtcs[i]); | |
698 | ||
cd5351f4 | 699 | priv->fbdev = omap_fbdev_init(dev); |
cd5351f4 | 700 | |
e78edba1 AG |
701 | /* store off drm_device for use in pm ops */ |
702 | dev_set_drvdata(dev->dev, dev); | |
703 | ||
cd5351f4 RC |
704 | drm_kms_helper_poll_init(dev); |
705 | ||
cd5351f4 RC |
706 | return 0; |
707 | } | |
708 | ||
709 | static int dev_unload(struct drm_device *dev) | |
710 | { | |
5609f7fe RC |
711 | struct omap_drm_private *priv = dev->dev_private; |
712 | ||
cd5351f4 RC |
713 | DBG("unload: dev=%p", dev); |
714 | ||
cd5351f4 RC |
715 | drm_kms_helper_poll_fini(dev); |
716 | ||
c7c1aecd TV |
717 | if (priv->fbdev) |
718 | omap_fbdev_free(dev); | |
e2f8fd74 | 719 | |
cd5351f4 | 720 | omap_modeset_free(dev); |
f7f9f453 | 721 | omap_gem_deinit(dev); |
cd5351f4 | 722 | |
5609f7fe RC |
723 | destroy_workqueue(priv->wq); |
724 | ||
80e4ed54 AT |
725 | drm_vblank_cleanup(dev); |
726 | omap_drm_irq_uninstall(dev); | |
727 | ||
cd5351f4 RC |
728 | kfree(dev->dev_private); |
729 | dev->dev_private = NULL; | |
730 | ||
e78edba1 AG |
731 | dev_set_drvdata(dev->dev, NULL); |
732 | ||
cd5351f4 RC |
733 | return 0; |
734 | } | |
735 | ||
736 | static int dev_open(struct drm_device *dev, struct drm_file *file) | |
737 | { | |
738 | file->driver_priv = NULL; | |
739 | ||
740 | DBG("open: dev=%p, file=%p", dev, file); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
cd5351f4 RC |
745 | /** |
746 | * lastclose - clean up after all DRM clients have exited | |
747 | * @dev: DRM device | |
748 | * | |
749 | * Take care of cleaning up after all DRM clients have exited. In the | |
750 | * mode setting case, we want to restore the kernel's initial mode (just | |
751 | * in case the last client left us in a bad state). | |
752 | */ | |
753 | static void dev_lastclose(struct drm_device *dev) | |
754 | { | |
3c810c61 RC |
755 | int i; |
756 | ||
f15a66e6 | 757 | /* we don't support vga_switcheroo.. so just make sure the fbdev |
cd5351f4 RC |
758 | * mode is active |
759 | */ | |
760 | struct omap_drm_private *priv = dev->dev_private; | |
761 | int ret; | |
762 | ||
763 | DBG("lastclose: dev=%p", dev); | |
764 | ||
e2cd09b2 | 765 | if (dev->mode_config.rotation_property) { |
c2a6a552 RC |
766 | /* need to restore default rotation state.. not sure |
767 | * if there is a cleaner way to restore properties to | |
768 | * default state? Maybe a flag that properties should | |
769 | * automatically be restored to default state on | |
770 | * lastclose? | |
771 | */ | |
772 | for (i = 0; i < priv->num_crtcs; i++) { | |
773 | drm_object_property_set_value(&priv->crtcs[i]->base, | |
e2cd09b2 | 774 | dev->mode_config.rotation_property, 0); |
c2a6a552 | 775 | } |
3c810c61 | 776 | |
c2a6a552 RC |
777 | for (i = 0; i < priv->num_planes; i++) { |
778 | drm_object_property_set_value(&priv->planes[i]->base, | |
e2cd09b2 | 779 | dev->mode_config.rotation_property, 0); |
c2a6a552 | 780 | } |
3c810c61 RC |
781 | } |
782 | ||
c7c1aecd TV |
783 | if (priv->fbdev) { |
784 | ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
785 | if (ret) | |
786 | DBG("failed to restore crtc mode"); | |
787 | } | |
cd5351f4 RC |
788 | } |
789 | ||
790 | static void dev_preclose(struct drm_device *dev, struct drm_file *file) | |
791 | { | |
1d5e5ea1 | 792 | struct omap_drm_private *priv = dev->dev_private; |
1cfe19aa LP |
793 | struct drm_pending_event *event; |
794 | unsigned long flags; | |
1d5e5ea1 | 795 | |
cd5351f4 | 796 | DBG("preclose: dev=%p", dev); |
1d5e5ea1 | 797 | |
1cfe19aa LP |
798 | /* |
799 | * Unlink all pending CRTC events to make sure they won't be queued up | |
800 | * by a pending asynchronous commit. | |
801 | */ | |
802 | spin_lock_irqsave(&dev->event_lock, flags); | |
803 | list_for_each_entry(event, &priv->commit.events, link) { | |
804 | if (event->file_priv == file) { | |
805 | file->event_space += event->event->length; | |
806 | event->file_priv = NULL; | |
807 | } | |
808 | } | |
809 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
cd5351f4 RC |
810 | } |
811 | ||
812 | static void dev_postclose(struct drm_device *dev, struct drm_file *file) | |
813 | { | |
814 | DBG("postclose: dev=%p, file=%p", dev, file); | |
815 | } | |
816 | ||
78b68556 | 817 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
818 | .fault = omap_gem_fault, |
819 | .open = drm_gem_vm_open, | |
820 | .close = drm_gem_vm_close, | |
821 | }; | |
822 | ||
ff4f3876 | 823 | static const struct file_operations omapdriver_fops = { |
222025e4 LP |
824 | .owner = THIS_MODULE, |
825 | .open = drm_open, | |
826 | .unlocked_ioctl = drm_ioctl, | |
827 | .release = drm_release, | |
828 | .mmap = omap_gem_mmap, | |
829 | .poll = drm_poll, | |
830 | .read = drm_read, | |
831 | .llseek = noop_llseek, | |
ff4f3876 RC |
832 | }; |
833 | ||
cd5351f4 | 834 | static struct drm_driver omap_drm_driver = { |
728fea77 TV |
835 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
836 | DRIVER_ATOMIC, | |
222025e4 LP |
837 | .load = dev_load, |
838 | .unload = dev_unload, | |
839 | .open = dev_open, | |
840 | .lastclose = dev_lastclose, | |
841 | .preclose = dev_preclose, | |
842 | .postclose = dev_postclose, | |
843 | .set_busid = drm_platform_set_busid, | |
b44f8408 | 844 | .get_vblank_counter = drm_vblank_no_hw_counter, |
222025e4 LP |
845 | .enable_vblank = omap_irq_enable_vblank, |
846 | .disable_vblank = omap_irq_disable_vblank, | |
6169a148 | 847 | #ifdef CONFIG_DEBUG_FS |
222025e4 LP |
848 | .debugfs_init = omap_debugfs_init, |
849 | .debugfs_cleanup = omap_debugfs_cleanup, | |
6169a148 | 850 | #endif |
222025e4 LP |
851 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
852 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
853 | .gem_prime_export = omap_gem_prime_export, | |
854 | .gem_prime_import = omap_gem_prime_import, | |
855 | .gem_free_object = omap_gem_free_object, | |
856 | .gem_vm_ops = &omap_gem_vm_ops, | |
857 | .dumb_create = omap_gem_dumb_create, | |
858 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
859 | .dumb_destroy = drm_gem_dumb_destroy, | |
860 | .ioctls = ioctls, | |
861 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
862 | .fops = &omapdriver_fops, | |
863 | .name = DRIVER_NAME, | |
864 | .desc = DRIVER_DESC, | |
865 | .date = DRIVER_DATE, | |
866 | .major = DRIVER_MAJOR, | |
867 | .minor = DRIVER_MINOR, | |
868 | .patchlevel = DRIVER_PATCHLEVEL, | |
cd5351f4 RC |
869 | }; |
870 | ||
cd5351f4 RC |
871 | static int pdev_probe(struct platform_device *device) |
872 | { | |
3a01ab25 AT |
873 | int r; |
874 | ||
591a0ac7 TV |
875 | if (omapdss_is_initialized() == false) |
876 | return -EPROBE_DEFER; | |
877 | ||
3a01ab25 AT |
878 | omap_crtc_pre_init(); |
879 | ||
880 | r = omap_connect_dssdevs(); | |
881 | if (r) { | |
882 | omap_crtc_pre_uninit(); | |
883 | return r; | |
884 | } | |
885 | ||
cd5351f4 RC |
886 | DBG("%s", device->name); |
887 | return drm_platform_init(&omap_drm_driver, device); | |
888 | } | |
889 | ||
890 | static int pdev_remove(struct platform_device *device) | |
891 | { | |
892 | DBG(""); | |
5c137797 | 893 | |
707cf58a TV |
894 | drm_put_dev(platform_get_drvdata(device)); |
895 | ||
cc823bdc AT |
896 | omap_disconnect_dssdevs(); |
897 | omap_crtc_pre_uninit(); | |
fd3c0253 | 898 | |
cd5351f4 RC |
899 | return 0; |
900 | } | |
901 | ||
8450c8d0 | 902 | #ifdef CONFIG_PM_SLEEP |
ccd7b5ed TV |
903 | static int omap_drm_suspend(struct device *dev) |
904 | { | |
905 | struct drm_device *drm_dev = dev_get_drvdata(dev); | |
906 | ||
907 | drm_kms_helper_poll_disable(drm_dev); | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | static int omap_drm_resume(struct device *dev) | |
913 | { | |
914 | struct drm_device *drm_dev = dev_get_drvdata(dev); | |
915 | ||
916 | drm_kms_helper_poll_enable(drm_dev); | |
917 | ||
918 | return omap_gem_resume(dev); | |
919 | } | |
e78edba1 AG |
920 | #endif |
921 | ||
8450c8d0 GS |
922 | static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); |
923 | ||
6717cd29 | 924 | static struct platform_driver pdev = { |
222025e4 LP |
925 | .driver = { |
926 | .name = DRIVER_NAME, | |
222025e4 | 927 | .pm = &omapdrm_pm_ops, |
222025e4 LP |
928 | }, |
929 | .probe = pdev_probe, | |
930 | .remove = pdev_remove, | |
cd5351f4 RC |
931 | }; |
932 | ||
e1c49bdc TR |
933 | static struct platform_driver * const drivers[] = { |
934 | &omap_dmm_driver, | |
935 | &pdev, | |
936 | }; | |
937 | ||
cd5351f4 RC |
938 | static int __init omap_drm_init(void) |
939 | { | |
940 | DBG("init"); | |
ea7e3a66 | 941 | |
e1c49bdc | 942 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
943 | } |
944 | ||
945 | static void __exit omap_drm_fini(void) | |
946 | { | |
947 | DBG("fini"); | |
ea7e3a66 | 948 | |
e1c49bdc | 949 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
950 | } |
951 | ||
952 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
953 | late_initcall(omap_drm_init); | |
954 | module_exit(omap_drm_fini); | |
955 | ||
956 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
957 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
958 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
959 | MODULE_LICENSE("GPL v2"); |