Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
22 | #include "drm_crtc_helper.h" | |
23 | #include "drm_fb_helper.h" | |
5c137797 | 24 | #include "omap_dmm_tiler.h" |
cd5351f4 RC |
25 | |
26 | #define DRIVER_NAME MODULE_NAME | |
27 | #define DRIVER_DESC "OMAP DRM" | |
28 | #define DRIVER_DATE "20110917" | |
29 | #define DRIVER_MAJOR 1 | |
30 | #define DRIVER_MINOR 0 | |
31 | #define DRIVER_PATCHLEVEL 0 | |
32 | ||
cd5351f4 RC |
33 | static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; |
34 | ||
35 | MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); | |
36 | module_param(num_crtc, int, 0600); | |
37 | ||
38 | /* | |
39 | * mode config funcs | |
40 | */ | |
41 | ||
42 | /* Notes about mapping DSS and DRM entities: | |
43 | * CRTC: overlay | |
44 | * encoder: manager.. with some extension to allow one primary CRTC | |
45 | * and zero or more video CRTC's to be mapped to one encoder? | |
46 | * connector: dssdev.. manager can be attached/detached from different | |
47 | * devices | |
48 | */ | |
49 | ||
50 | static void omap_fb_output_poll_changed(struct drm_device *dev) | |
51 | { | |
52 | struct omap_drm_private *priv = dev->dev_private; | |
53 | DBG("dev=%p", dev); | |
c7f904b3 | 54 | if (priv->fbdev) |
cd5351f4 | 55 | drm_fb_helper_hotplug_event(priv->fbdev); |
cd5351f4 RC |
56 | } |
57 | ||
e6ecefaa | 58 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 RC |
59 | .fb_create = omap_framebuffer_create, |
60 | .output_poll_changed = omap_fb_output_poll_changed, | |
61 | }; | |
62 | ||
63 | static int get_connector_type(struct omap_dss_device *dssdev) | |
64 | { | |
65 | switch (dssdev->type) { | |
66 | case OMAP_DISPLAY_TYPE_HDMI: | |
67 | return DRM_MODE_CONNECTOR_HDMIA; | |
4635c17d TV |
68 | case OMAP_DISPLAY_TYPE_DVI: |
69 | return DRM_MODE_CONNECTOR_DVID; | |
cd5351f4 RC |
70 | default: |
71 | return DRM_MODE_CONNECTOR_Unknown; | |
72 | } | |
73 | } | |
74 | ||
0d8f371f AT |
75 | static bool channel_used(struct drm_device *dev, enum omap_channel channel) |
76 | { | |
77 | struct omap_drm_private *priv = dev->dev_private; | |
78 | int i; | |
79 | ||
80 | for (i = 0; i < priv->num_crtcs; i++) { | |
81 | struct drm_crtc *crtc = priv->crtcs[i]; | |
82 | ||
83 | if (omap_crtc_channel(crtc) == channel) | |
84 | return true; | |
85 | } | |
86 | ||
87 | return false; | |
88 | } | |
89 | ||
f5f9454c | 90 | static int omap_modeset_init(struct drm_device *dev) |
cd5351f4 RC |
91 | { |
92 | struct omap_drm_private *priv = dev->dev_private; | |
f5f9454c RC |
93 | struct omap_dss_device *dssdev = NULL; |
94 | int num_ovls = dss_feat_get_num_ovls(); | |
0d8f371f AT |
95 | int num_mgrs = dss_feat_get_num_mgrs(); |
96 | int num_crtcs; | |
97 | int i, id = 0; | |
a7e71e7f | 98 | int r; |
cd5351f4 | 99 | |
04b1fc02 TV |
100 | omap_crtc_pre_init(); |
101 | ||
f5f9454c | 102 | drm_mode_config_init(dev); |
cd5351f4 | 103 | |
f5f9454c | 104 | omap_drm_irq_install(dev); |
cd5351f4 | 105 | |
f5f9454c | 106 | /* |
0d8f371f AT |
107 | * We usually don't want to create a CRTC for each manager, at least |
108 | * not until we have a way to expose private planes to userspace. | |
109 | * Otherwise there would not be enough video pipes left for drm planes. | |
110 | * We use the num_crtc argument to limit the number of crtcs we create. | |
f5f9454c | 111 | */ |
0d8f371f | 112 | num_crtcs = min3(num_crtc, num_mgrs, num_ovls); |
cd5351f4 | 113 | |
0d8f371f | 114 | dssdev = NULL; |
cd5351f4 | 115 | |
f5f9454c RC |
116 | for_each_dss_dev(dssdev) { |
117 | struct drm_connector *connector; | |
118 | struct drm_encoder *encoder; | |
0d8f371f | 119 | enum omap_channel channel; |
a7e71e7f | 120 | struct omap_overlay_manager *mgr; |
c7f904b3 | 121 | |
f5f9454c RC |
122 | if (!dssdev->driver) { |
123 | dev_warn(dev->dev, "%s has no driver.. skipping it\n", | |
124 | dssdev->name); | |
581382e3 | 125 | continue; |
cd5351f4 | 126 | } |
cd5351f4 | 127 | |
f5f9454c RC |
128 | if (!(dssdev->driver->get_timings || |
129 | dssdev->driver->read_edid)) { | |
130 | dev_warn(dev->dev, "%s driver does not support " | |
131 | "get_timings or read_edid.. skipping it!\n", | |
132 | dssdev->name); | |
581382e3 | 133 | continue; |
cd5351f4 | 134 | } |
cd5351f4 | 135 | |
a7e71e7f TV |
136 | r = dssdev->driver->connect(dssdev); |
137 | if (r) { | |
138 | dev_err(dev->dev, "could not connect display: %s\n", | |
139 | dssdev->name); | |
140 | continue; | |
141 | } | |
142 | ||
f5f9454c | 143 | encoder = omap_encoder_init(dev, dssdev); |
cd5351f4 | 144 | |
f5f9454c RC |
145 | if (!encoder) { |
146 | dev_err(dev->dev, "could not create encoder: %s\n", | |
147 | dssdev->name); | |
148 | return -ENOMEM; | |
cd5351f4 RC |
149 | } |
150 | ||
f5f9454c RC |
151 | connector = omap_connector_init(dev, |
152 | get_connector_type(dssdev), dssdev, encoder); | |
cd5351f4 | 153 | |
f5f9454c RC |
154 | if (!connector) { |
155 | dev_err(dev->dev, "could not create connector: %s\n", | |
156 | dssdev->name); | |
157 | return -ENOMEM; | |
cd5351f4 | 158 | } |
bb5c2d9a | 159 | |
f5f9454c RC |
160 | BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); |
161 | BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); | |
cd5351f4 | 162 | |
f5f9454c RC |
163 | priv->encoders[priv->num_encoders++] = encoder; |
164 | priv->connectors[priv->num_connectors++] = connector; | |
cd5351f4 | 165 | |
f5f9454c | 166 | drm_mode_connector_attach_encoder(connector, encoder); |
cd5351f4 | 167 | |
0d8f371f AT |
168 | /* |
169 | * if we have reached the limit of the crtcs we are allowed to | |
170 | * create, let's not try to look for a crtc for this | |
171 | * panel/encoder and onwards, we will, of course, populate the | |
172 | * the possible_crtcs field for all the encoders with the final | |
173 | * set of crtcs we create | |
174 | */ | |
175 | if (id == num_crtcs) | |
176 | continue; | |
177 | ||
178 | /* | |
179 | * get the recommended DISPC channel for this encoder. For now, | |
180 | * we only try to get create a crtc out of the recommended, the | |
181 | * other possible channels to which the encoder can connect are | |
182 | * not considered. | |
183 | */ | |
0d8f371f | 184 | |
a7e71e7f TV |
185 | mgr = omapdss_find_mgr_from_display(dssdev); |
186 | channel = mgr->id; | |
0d8f371f AT |
187 | /* |
188 | * if this channel hasn't already been taken by a previously | |
189 | * allocated crtc, we create a new crtc for it | |
190 | */ | |
191 | if (!channel_used(dev, channel)) { | |
192 | struct drm_plane *plane; | |
193 | struct drm_crtc *crtc; | |
194 | ||
195 | plane = omap_plane_init(dev, id, true); | |
196 | crtc = omap_crtc_init(dev, plane, channel, id); | |
197 | ||
198 | BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); | |
199 | priv->crtcs[id] = crtc; | |
200 | priv->num_crtcs++; | |
201 | ||
202 | priv->planes[id] = plane; | |
203 | priv->num_planes++; | |
204 | ||
205 | id++; | |
206 | } | |
207 | } | |
208 | ||
209 | /* | |
210 | * we have allocated crtcs according to the need of the panels/encoders, | |
211 | * adding more crtcs here if needed | |
212 | */ | |
213 | for (; id < num_crtcs; id++) { | |
214 | ||
215 | /* find a free manager for this crtc */ | |
216 | for (i = 0; i < num_mgrs; i++) { | |
217 | if (!channel_used(dev, i)) { | |
218 | struct drm_plane *plane; | |
219 | struct drm_crtc *crtc; | |
220 | ||
221 | plane = omap_plane_init(dev, id, true); | |
222 | crtc = omap_crtc_init(dev, plane, i, id); | |
223 | ||
224 | BUG_ON(priv->num_crtcs >= | |
225 | ARRAY_SIZE(priv->crtcs)); | |
226 | ||
227 | priv->crtcs[id] = crtc; | |
228 | priv->num_crtcs++; | |
229 | ||
230 | priv->planes[id] = plane; | |
231 | priv->num_planes++; | |
232 | ||
233 | break; | |
234 | } else { | |
235 | continue; | |
236 | } | |
237 | } | |
238 | ||
239 | if (i == num_mgrs) { | |
240 | /* this shouldn't really happen */ | |
241 | dev_err(dev->dev, "no managers left for crtc\n"); | |
242 | return -ENOMEM; | |
243 | } | |
244 | } | |
245 | ||
246 | /* | |
247 | * Create normal planes for the remaining overlays: | |
248 | */ | |
249 | for (; id < num_ovls; id++) { | |
250 | struct drm_plane *plane = omap_plane_init(dev, id, false); | |
251 | ||
252 | BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); | |
253 | priv->planes[priv->num_planes++] = plane; | |
254 | } | |
255 | ||
256 | for (i = 0; i < priv->num_encoders; i++) { | |
257 | struct drm_encoder *encoder = priv->encoders[i]; | |
258 | struct omap_dss_device *dssdev = | |
259 | omap_encoder_get_dssdev(encoder); | |
1f68d9c4 | 260 | struct omap_dss_device *output; |
be8e8e1c TV |
261 | |
262 | output = omapdss_find_output_from_display(dssdev); | |
0d8f371f | 263 | |
f5f9454c RC |
264 | /* figure out which crtc's we can connect the encoder to: */ |
265 | encoder->possible_crtcs = 0; | |
266 | for (id = 0; id < priv->num_crtcs; id++) { | |
0d8f371f AT |
267 | struct drm_crtc *crtc = priv->crtcs[id]; |
268 | enum omap_channel crtc_channel; | |
269 | enum omap_dss_output_id supported_outputs; | |
270 | ||
271 | crtc_channel = omap_crtc_channel(crtc); | |
272 | supported_outputs = | |
273 | dss_feat_get_supported_outputs(crtc_channel); | |
274 | ||
be8e8e1c | 275 | if (supported_outputs & output->id) |
f5f9454c | 276 | encoder->possible_crtcs |= (1 << id); |
bb5c2d9a | 277 | } |
820caabf TV |
278 | |
279 | omap_dss_put_device(output); | |
cd5351f4 RC |
280 | } |
281 | ||
0d8f371f AT |
282 | DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", |
283 | priv->num_planes, priv->num_crtcs, priv->num_encoders, | |
284 | priv->num_connectors); | |
285 | ||
6b8ca4cf RC |
286 | dev->mode_config.min_width = 32; |
287 | dev->mode_config.min_height = 32; | |
cd5351f4 RC |
288 | |
289 | /* note: eventually will need some cpu_is_omapXYZ() type stuff here | |
290 | * to fill in these limits properly on different OMAP generations.. | |
291 | */ | |
292 | dev->mode_config.max_width = 2048; | |
293 | dev->mode_config.max_height = 2048; | |
294 | ||
295 | dev->mode_config.funcs = &omap_mode_config_funcs; | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static void omap_modeset_free(struct drm_device *dev) | |
301 | { | |
302 | drm_mode_config_cleanup(dev); | |
303 | } | |
304 | ||
305 | /* | |
306 | * drm ioctl funcs | |
307 | */ | |
308 | ||
309 | ||
310 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
311 | struct drm_file *file_priv) | |
312 | { | |
5e3b0874 | 313 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 RC |
314 | struct drm_omap_param *args = data; |
315 | ||
316 | DBG("%p: param=%llu", dev, args->param); | |
317 | ||
318 | switch (args->param) { | |
319 | case OMAP_PARAM_CHIPSET_ID: | |
5e3b0874 | 320 | args->value = priv->omaprev; |
cd5351f4 RC |
321 | break; |
322 | default: | |
323 | DBG("unknown parameter %lld", args->param); | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
331 | struct drm_file *file_priv) | |
332 | { | |
333 | struct drm_omap_param *args = data; | |
334 | ||
335 | switch (args->param) { | |
336 | default: | |
337 | DBG("unknown parameter %lld", args->param); | |
338 | return -EINVAL; | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | static int ioctl_gem_new(struct drm_device *dev, void *data, | |
345 | struct drm_file *file_priv) | |
346 | { | |
347 | struct drm_omap_gem_new *args = data; | |
f5f9454c | 348 | VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, |
cd5351f4 RC |
349 | args->size.bytes, args->flags); |
350 | return omap_gem_new_handle(dev, file_priv, args->size, | |
351 | args->flags, &args->handle); | |
352 | } | |
353 | ||
354 | static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
355 | struct drm_file *file_priv) | |
356 | { | |
357 | struct drm_omap_gem_cpu_prep *args = data; | |
358 | struct drm_gem_object *obj; | |
359 | int ret; | |
360 | ||
361 | VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); | |
362 | ||
363 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 364 | if (!obj) |
cd5351f4 | 365 | return -ENOENT; |
cd5351f4 RC |
366 | |
367 | ret = omap_gem_op_sync(obj, args->op); | |
368 | ||
c7f904b3 | 369 | if (!ret) |
cd5351f4 | 370 | ret = omap_gem_op_start(obj, args->op); |
cd5351f4 RC |
371 | |
372 | drm_gem_object_unreference_unlocked(obj); | |
373 | ||
374 | return ret; | |
375 | } | |
376 | ||
377 | static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
378 | struct drm_file *file_priv) | |
379 | { | |
380 | struct drm_omap_gem_cpu_fini *args = data; | |
381 | struct drm_gem_object *obj; | |
382 | int ret; | |
383 | ||
384 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); | |
385 | ||
386 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 387 | if (!obj) |
cd5351f4 | 388 | return -ENOENT; |
cd5351f4 RC |
389 | |
390 | /* XXX flushy, flushy */ | |
391 | ret = 0; | |
392 | ||
c7f904b3 | 393 | if (!ret) |
cd5351f4 | 394 | ret = omap_gem_op_finish(obj, args->op); |
cd5351f4 RC |
395 | |
396 | drm_gem_object_unreference_unlocked(obj); | |
397 | ||
398 | return ret; | |
399 | } | |
400 | ||
401 | static int ioctl_gem_info(struct drm_device *dev, void *data, | |
402 | struct drm_file *file_priv) | |
403 | { | |
404 | struct drm_omap_gem_info *args = data; | |
405 | struct drm_gem_object *obj; | |
406 | int ret = 0; | |
407 | ||
f5f9454c | 408 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); |
cd5351f4 RC |
409 | |
410 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 411 | if (!obj) |
cd5351f4 | 412 | return -ENOENT; |
cd5351f4 | 413 | |
f7f9f453 | 414 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
415 | args->offset = omap_gem_mmap_offset(obj); |
416 | ||
417 | drm_gem_object_unreference_unlocked(obj); | |
418 | ||
419 | return ret; | |
420 | } | |
421 | ||
baa70943 | 422 | static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { |
cd5351f4 RC |
423 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH), |
424 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
425 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH), | |
426 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH), | |
427 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH), | |
428 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH), | |
429 | }; | |
430 | ||
431 | /* | |
432 | * drm driver funcs | |
433 | */ | |
434 | ||
435 | /** | |
436 | * load - setup chip and create an initial config | |
437 | * @dev: DRM device | |
438 | * @flags: startup flags | |
439 | * | |
440 | * The driver load routine has to do several things: | |
441 | * - initialize the memory manager | |
442 | * - allocate initial config memory | |
443 | * - setup the DRM framebuffer with the allocated memory | |
444 | */ | |
445 | static int dev_load(struct drm_device *dev, unsigned long flags) | |
446 | { | |
5e3b0874 | 447 | struct omap_drm_platform_data *pdata = dev->dev->platform_data; |
cd5351f4 RC |
448 | struct omap_drm_private *priv; |
449 | int ret; | |
450 | ||
451 | DBG("load: dev=%p", dev); | |
452 | ||
cd5351f4 | 453 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
78110bb8 | 454 | if (!priv) |
cd5351f4 | 455 | return -ENOMEM; |
cd5351f4 | 456 | |
5e3b0874 RC |
457 | priv->omaprev = pdata->omaprev; |
458 | ||
cd5351f4 RC |
459 | dev->dev_private = priv; |
460 | ||
4619cdbc | 461 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
5609f7fe | 462 | |
f6b6036e RC |
463 | INIT_LIST_HEAD(&priv->obj_list); |
464 | ||
f7f9f453 RC |
465 | omap_gem_init(dev); |
466 | ||
cd5351f4 RC |
467 | ret = omap_modeset_init(dev); |
468 | if (ret) { | |
469 | dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret); | |
470 | dev->dev_private = NULL; | |
471 | kfree(priv); | |
472 | return ret; | |
473 | } | |
474 | ||
f5f9454c RC |
475 | ret = drm_vblank_init(dev, priv->num_crtcs); |
476 | if (ret) | |
477 | dev_warn(dev->dev, "could not init vblank\n"); | |
478 | ||
cd5351f4 RC |
479 | priv->fbdev = omap_fbdev_init(dev); |
480 | if (!priv->fbdev) { | |
481 | dev_warn(dev->dev, "omap_fbdev_init failed\n"); | |
482 | /* well, limp along without an fbdev.. maybe X11 will work? */ | |
483 | } | |
484 | ||
e78edba1 AG |
485 | /* store off drm_device for use in pm ops */ |
486 | dev_set_drvdata(dev->dev, dev); | |
487 | ||
cd5351f4 RC |
488 | drm_kms_helper_poll_init(dev); |
489 | ||
cd5351f4 RC |
490 | return 0; |
491 | } | |
492 | ||
493 | static int dev_unload(struct drm_device *dev) | |
494 | { | |
5609f7fe RC |
495 | struct omap_drm_private *priv = dev->dev_private; |
496 | ||
cd5351f4 RC |
497 | DBG("unload: dev=%p", dev); |
498 | ||
cd5351f4 | 499 | drm_kms_helper_poll_fini(dev); |
f5f9454c RC |
500 | drm_vblank_cleanup(dev); |
501 | omap_drm_irq_uninstall(dev); | |
cd5351f4 RC |
502 | |
503 | omap_fbdev_free(dev); | |
cd5351f4 | 504 | omap_modeset_free(dev); |
f7f9f453 | 505 | omap_gem_deinit(dev); |
cd5351f4 | 506 | |
5609f7fe RC |
507 | flush_workqueue(priv->wq); |
508 | destroy_workqueue(priv->wq); | |
509 | ||
cd5351f4 RC |
510 | kfree(dev->dev_private); |
511 | dev->dev_private = NULL; | |
512 | ||
e78edba1 AG |
513 | dev_set_drvdata(dev->dev, NULL); |
514 | ||
cd5351f4 RC |
515 | return 0; |
516 | } | |
517 | ||
518 | static int dev_open(struct drm_device *dev, struct drm_file *file) | |
519 | { | |
520 | file->driver_priv = NULL; | |
521 | ||
522 | DBG("open: dev=%p, file=%p", dev, file); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
cd5351f4 RC |
527 | /** |
528 | * lastclose - clean up after all DRM clients have exited | |
529 | * @dev: DRM device | |
530 | * | |
531 | * Take care of cleaning up after all DRM clients have exited. In the | |
532 | * mode setting case, we want to restore the kernel's initial mode (just | |
533 | * in case the last client left us in a bad state). | |
534 | */ | |
535 | static void dev_lastclose(struct drm_device *dev) | |
536 | { | |
3c810c61 RC |
537 | int i; |
538 | ||
cd5351f4 RC |
539 | /* we don't support vga-switcheroo.. so just make sure the fbdev |
540 | * mode is active | |
541 | */ | |
542 | struct omap_drm_private *priv = dev->dev_private; | |
543 | int ret; | |
544 | ||
545 | DBG("lastclose: dev=%p", dev); | |
546 | ||
c2a6a552 RC |
547 | if (priv->rotation_prop) { |
548 | /* need to restore default rotation state.. not sure | |
549 | * if there is a cleaner way to restore properties to | |
550 | * default state? Maybe a flag that properties should | |
551 | * automatically be restored to default state on | |
552 | * lastclose? | |
553 | */ | |
554 | for (i = 0; i < priv->num_crtcs; i++) { | |
555 | drm_object_property_set_value(&priv->crtcs[i]->base, | |
556 | priv->rotation_prop, 0); | |
557 | } | |
3c810c61 | 558 | |
c2a6a552 RC |
559 | for (i = 0; i < priv->num_planes; i++) { |
560 | drm_object_property_set_value(&priv->planes[i]->base, | |
561 | priv->rotation_prop, 0); | |
562 | } | |
3c810c61 RC |
563 | } |
564 | ||
d5d2636e | 565 | drm_modeset_lock_all(dev); |
cd5351f4 | 566 | ret = drm_fb_helper_restore_fbdev_mode(priv->fbdev); |
d5d2636e | 567 | drm_modeset_unlock_all(dev); |
cd5351f4 RC |
568 | if (ret) |
569 | DBG("failed to restore crtc mode"); | |
570 | } | |
571 | ||
572 | static void dev_preclose(struct drm_device *dev, struct drm_file *file) | |
573 | { | |
574 | DBG("preclose: dev=%p", dev); | |
575 | } | |
576 | ||
577 | static void dev_postclose(struct drm_device *dev, struct drm_file *file) | |
578 | { | |
579 | DBG("postclose: dev=%p, file=%p", dev, file); | |
580 | } | |
581 | ||
78b68556 | 582 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
583 | .fault = omap_gem_fault, |
584 | .open = drm_gem_vm_open, | |
585 | .close = drm_gem_vm_close, | |
586 | }; | |
587 | ||
ff4f3876 RC |
588 | static const struct file_operations omapdriver_fops = { |
589 | .owner = THIS_MODULE, | |
590 | .open = drm_open, | |
591 | .unlocked_ioctl = drm_ioctl, | |
592 | .release = drm_release, | |
593 | .mmap = omap_gem_mmap, | |
594 | .poll = drm_poll, | |
ff4f3876 RC |
595 | .read = drm_read, |
596 | .llseek = noop_llseek, | |
597 | }; | |
598 | ||
cd5351f4 RC |
599 | static struct drm_driver omap_drm_driver = { |
600 | .driver_features = | |
6ad11bc3 | 601 | DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
cd5351f4 RC |
602 | .load = dev_load, |
603 | .unload = dev_unload, | |
604 | .open = dev_open, | |
cd5351f4 RC |
605 | .lastclose = dev_lastclose, |
606 | .preclose = dev_preclose, | |
607 | .postclose = dev_postclose, | |
608 | .get_vblank_counter = drm_vblank_count, | |
f5f9454c RC |
609 | .enable_vblank = omap_irq_enable_vblank, |
610 | .disable_vblank = omap_irq_disable_vblank, | |
611 | .irq_preinstall = omap_irq_preinstall, | |
612 | .irq_postinstall = omap_irq_postinstall, | |
613 | .irq_uninstall = omap_irq_uninstall, | |
614 | .irq_handler = omap_irq_handler, | |
6169a148 AG |
615 | #ifdef CONFIG_DEBUG_FS |
616 | .debugfs_init = omap_debugfs_init, | |
617 | .debugfs_cleanup = omap_debugfs_cleanup, | |
618 | #endif | |
6ad11bc3 | 619 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
3080b838 | 620 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
6ad11bc3 | 621 | .gem_prime_export = omap_gem_prime_export, |
3080b838 | 622 | .gem_prime_import = omap_gem_prime_import, |
cd5351f4 RC |
623 | .gem_free_object = omap_gem_free_object, |
624 | .gem_vm_ops = &omap_gem_vm_ops, | |
625 | .dumb_create = omap_gem_dumb_create, | |
626 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
43387b37 | 627 | .dumb_destroy = drm_gem_dumb_destroy, |
cd5351f4 RC |
628 | .ioctls = ioctls, |
629 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
ff4f3876 | 630 | .fops = &omapdriver_fops, |
cd5351f4 RC |
631 | .name = DRIVER_NAME, |
632 | .desc = DRIVER_DESC, | |
633 | .date = DRIVER_DATE, | |
634 | .major = DRIVER_MAJOR, | |
635 | .minor = DRIVER_MINOR, | |
636 | .patchlevel = DRIVER_PATCHLEVEL, | |
637 | }; | |
638 | ||
639 | static int pdev_suspend(struct platform_device *pDevice, pm_message_t state) | |
640 | { | |
641 | DBG(""); | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static int pdev_resume(struct platform_device *device) | |
646 | { | |
647 | DBG(""); | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static void pdev_shutdown(struct platform_device *device) | |
652 | { | |
653 | DBG(""); | |
654 | } | |
655 | ||
656 | static int pdev_probe(struct platform_device *device) | |
657 | { | |
591a0ac7 TV |
658 | if (omapdss_is_initialized() == false) |
659 | return -EPROBE_DEFER; | |
660 | ||
cd5351f4 RC |
661 | DBG("%s", device->name); |
662 | return drm_platform_init(&omap_drm_driver, device); | |
663 | } | |
664 | ||
665 | static int pdev_remove(struct platform_device *device) | |
666 | { | |
667 | DBG(""); | |
668 | drm_platform_exit(&omap_drm_driver, device); | |
5c137797 AG |
669 | |
670 | platform_driver_unregister(&omap_dmm_driver); | |
cd5351f4 RC |
671 | return 0; |
672 | } | |
673 | ||
e78edba1 AG |
674 | #ifdef CONFIG_PM |
675 | static const struct dev_pm_ops omapdrm_pm_ops = { | |
676 | .resume = omap_gem_resume, | |
677 | }; | |
678 | #endif | |
679 | ||
6717cd29 | 680 | static struct platform_driver pdev = { |
cd5351f4 RC |
681 | .driver = { |
682 | .name = DRIVER_NAME, | |
683 | .owner = THIS_MODULE, | |
e78edba1 AG |
684 | #ifdef CONFIG_PM |
685 | .pm = &omapdrm_pm_ops, | |
686 | #endif | |
cd5351f4 RC |
687 | }, |
688 | .probe = pdev_probe, | |
689 | .remove = pdev_remove, | |
690 | .suspend = pdev_suspend, | |
691 | .resume = pdev_resume, | |
692 | .shutdown = pdev_shutdown, | |
693 | }; | |
694 | ||
695 | static int __init omap_drm_init(void) | |
696 | { | |
697 | DBG("init"); | |
be0775ac RC |
698 | if (platform_driver_register(&omap_dmm_driver)) { |
699 | /* we can continue on without DMM.. so not fatal */ | |
700 | dev_err(NULL, "DMM registration failed\n"); | |
701 | } | |
cd5351f4 RC |
702 | return platform_driver_register(&pdev); |
703 | } | |
704 | ||
705 | static void __exit omap_drm_fini(void) | |
706 | { | |
707 | DBG("fini"); | |
708 | platform_driver_unregister(&pdev); | |
709 | } | |
710 | ||
711 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
712 | late_initcall(omap_drm_init); | |
713 | module_exit(omap_drm_fini); | |
714 | ||
715 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
716 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
717 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
718 | MODULE_LICENSE("GPL v2"); |