Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.h |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __OMAP_DRV_H__ | |
21 | #define __OMAP_DRV_H__ | |
22 | ||
23 | #include <video/omapdss.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/types.h> | |
26 | #include <drm/drmP.h> | |
ae43d7ca | 27 | #include <drm/drm_crtc_helper.h> |
8bb0daff | 28 | #include <drm/omap_drm.h> |
d9fc9413 | 29 | #include <drm/drm_gem.h> |
e2fb5052 | 30 | #include <linux/platform_data/omap_drm.h> |
cd5351f4 | 31 | |
f5f9454c | 32 | |
cd5351f4 RC |
33 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
34 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt, ##__VA_ARGS__) /* verbose debug */ | |
35 | ||
36 | #define MODULE_NAME "omapdrm" | |
37 | ||
38 | /* max # of mapper-id's that can be assigned.. todo, come up with a better | |
39 | * (but still inexpensive) way to store/access per-buffer mapper private | |
40 | * data.. | |
41 | */ | |
42 | #define MAX_MAPPERS 2 | |
43 | ||
f5f9454c RC |
44 | /* parameters which describe (unrotated) coordinates of scanout within a fb: */ |
45 | struct omap_drm_window { | |
46 | uint32_t rotation; | |
47 | int32_t crtc_x, crtc_y; /* signed because can be offscreen */ | |
48 | uint32_t crtc_w, crtc_h; | |
49 | uint32_t src_x, src_y; | |
50 | uint32_t src_w, src_h; | |
51 | }; | |
52 | ||
f5f9454c RC |
53 | /* For transiently registering for different DSS irqs that various parts |
54 | * of the KMS code need during setup/configuration. We these are not | |
55 | * necessarily the same as what drm_vblank_get/put() are requesting, and | |
56 | * the hysteresis in drm_vblank_put() is not necessarily desirable for | |
57 | * internal housekeeping related irq usage. | |
58 | */ | |
59 | struct omap_drm_irq { | |
60 | struct list_head node; | |
61 | uint32_t irqmask; | |
62 | bool registered; | |
63 | void (*irq)(struct omap_drm_irq *irq, uint32_t irqstatus); | |
64 | }; | |
65 | ||
66 | /* For KMS code that needs to wait for a certain # of IRQs: | |
67 | */ | |
68 | struct omap_irq_wait; | |
69 | struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, | |
70 | uint32_t irqmask, int count); | |
71 | int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |
72 | unsigned long timeout); | |
73 | ||
cd5351f4 | 74 | struct omap_drm_private { |
5e3b0874 RC |
75 | uint32_t omaprev; |
76 | ||
cd5351f4 RC |
77 | unsigned int num_crtcs; |
78 | struct drm_crtc *crtcs[8]; | |
f6b6036e | 79 | |
bb5c2d9a RC |
80 | unsigned int num_planes; |
81 | struct drm_plane *planes[8]; | |
f6b6036e | 82 | |
cd5351f4 RC |
83 | unsigned int num_encoders; |
84 | struct drm_encoder *encoders[8]; | |
f6b6036e | 85 | |
cd5351f4 RC |
86 | unsigned int num_connectors; |
87 | struct drm_connector *connectors[8]; | |
88 | ||
89 | struct drm_fb_helper *fbdev; | |
a6a91827 | 90 | |
5609f7fe RC |
91 | struct workqueue_struct *wq; |
92 | ||
76c4055f TV |
93 | /* lock for obj_list below */ |
94 | spinlock_t list_lock; | |
95 | ||
f5f9454c | 96 | /* list of GEM objects: */ |
f6b6036e RC |
97 | struct list_head obj_list; |
98 | ||
a6a91827 | 99 | bool has_dmm; |
3c810c61 RC |
100 | |
101 | /* properties: */ | |
8451b5ad | 102 | struct drm_property *zorder_prop; |
f5f9454c RC |
103 | |
104 | /* irq handling: */ | |
105 | struct list_head irq_list; /* list of omap_drm_irq */ | |
106 | uint32_t vblank_mask; /* irq bits set for userspace vblank */ | |
107 | struct omap_drm_irq error_handler; | |
3c810c61 RC |
108 | }; |
109 | ||
3c810c61 | 110 | |
6169a148 AG |
111 | #ifdef CONFIG_DEBUG_FS |
112 | int omap_debugfs_init(struct drm_minor *minor); | |
113 | void omap_debugfs_cleanup(struct drm_minor *minor); | |
f6b6036e RC |
114 | void omap_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
115 | void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m); | |
116 | void omap_gem_describe_objects(struct list_head *list, struct seq_file *m); | |
6169a148 AG |
117 | #endif |
118 | ||
4836d157 AG |
119 | #ifdef CONFIG_PM |
120 | int omap_gem_resume(struct device *dev); | |
121 | #endif | |
122 | ||
0d8f371f AT |
123 | int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id); |
124 | void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id); | |
e9f0d76f | 125 | irqreturn_t omap_irq_handler(int irq, void *arg); |
f5f9454c RC |
126 | void omap_irq_preinstall(struct drm_device *dev); |
127 | int omap_irq_postinstall(struct drm_device *dev); | |
128 | void omap_irq_uninstall(struct drm_device *dev); | |
6da9f891 TV |
129 | void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); |
130 | void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); | |
f5f9454c RC |
131 | void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); |
132 | void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); | |
133 | int omap_drm_irq_uninstall(struct drm_device *dev); | |
134 | int omap_drm_irq_install(struct drm_device *dev); | |
135 | ||
cd5351f4 RC |
136 | struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev); |
137 | void omap_fbdev_free(struct drm_device *dev); | |
138 | ||
f5f9454c RC |
139 | const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc); |
140 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); | |
a42133a7 LP |
141 | int omap_crtc_flush(struct drm_crtc *crtc); |
142 | int omap_crtc_queue_unpin(struct drm_crtc *crtc, struct drm_framebuffer *fb); | |
04b1fc02 | 143 | void omap_crtc_pre_init(void); |
3a01ab25 | 144 | void omap_crtc_pre_uninit(void); |
cd5351f4 | 145 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, |
f5f9454c | 146 | struct drm_plane *plane, enum omap_channel channel, int id); |
bb5c2d9a RC |
147 | |
148 | struct drm_plane *omap_plane_init(struct drm_device *dev, | |
ef6b0e02 | 149 | int id, enum drm_plane_type type); |
2debab97 | 150 | int omap_plane_set_enable(struct drm_plane *plane, bool enable); |
2f53700d | 151 | int omap_plane_mode_set(struct drm_plane *plane, |
a350da8b LP |
152 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
153 | int crtc_x, int crtc_y, | |
154 | unsigned int crtc_w, unsigned int crtc_h, | |
155 | unsigned int src_x, unsigned int src_y, | |
a42133a7 | 156 | unsigned int src_w, unsigned int src_h); |
3c810c61 RC |
157 | void omap_plane_install_properties(struct drm_plane *plane, |
158 | struct drm_mode_object *obj); | |
159 | int omap_plane_set_property(struct drm_plane *plane, | |
160 | struct drm_property *property, uint64_t val); | |
cd5351f4 RC |
161 | |
162 | struct drm_encoder *omap_encoder_init(struct drm_device *dev, | |
f5f9454c RC |
163 | struct omap_dss_device *dssdev); |
164 | int omap_encoder_set_enabled(struct drm_encoder *encoder, bool enabled); | |
165 | int omap_encoder_update(struct drm_encoder *encoder, | |
166 | struct omap_overlay_manager *mgr, | |
167 | struct omap_video_timings *timings); | |
168 | ||
169 | struct drm_connector *omap_connector_init(struct drm_device *dev, | |
170 | int connector_type, struct omap_dss_device *dssdev, | |
cd5351f4 RC |
171 | struct drm_encoder *encoder); |
172 | struct drm_encoder *omap_connector_attached_encoder( | |
173 | struct drm_connector *connector); | |
4f930c0f | 174 | bool omap_connector_get_hdmi_mode(struct drm_connector *connector); |
cd5351f4 | 175 | |
f5f9454c RC |
176 | void copy_timings_omap_to_drm(struct drm_display_mode *mode, |
177 | struct omap_video_timings *timings); | |
178 | void copy_timings_drm_to_omap(struct omap_video_timings *timings, | |
179 | struct drm_display_mode *mode); | |
180 | ||
a890e662 RC |
181 | uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats, |
182 | uint32_t max_formats, enum omap_color_mode supported_modes); | |
cd5351f4 | 183 | struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, |
ae43d7ca | 184 | struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); |
cd5351f4 | 185 | struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, |
ae43d7ca | 186 | struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
9a0774e0 | 187 | struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p); |
5833bd2f RC |
188 | int omap_framebuffer_pin(struct drm_framebuffer *fb); |
189 | int omap_framebuffer_unpin(struct drm_framebuffer *fb); | |
3c810c61 RC |
190 | void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, |
191 | struct omap_drm_window *win, struct omap_overlay_info *info); | |
cd5351f4 RC |
192 | struct drm_connector *omap_framebuffer_get_next_connector( |
193 | struct drm_framebuffer *fb, struct drm_connector *from); | |
cd5351f4 | 194 | |
f7f9f453 RC |
195 | void omap_gem_init(struct drm_device *dev); |
196 | void omap_gem_deinit(struct drm_device *dev); | |
cd5351f4 RC |
197 | |
198 | struct drm_gem_object *omap_gem_new(struct drm_device *dev, | |
199 | union omap_gem_size gsize, uint32_t flags); | |
200 | int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file, | |
201 | union omap_gem_size gsize, uint32_t flags, uint32_t *handle); | |
202 | void omap_gem_free_object(struct drm_gem_object *obj); | |
cd5351f4 RC |
203 | void *omap_gem_vaddr(struct drm_gem_object *obj); |
204 | int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, | |
205 | uint32_t handle, uint64_t *offset); | |
cd5351f4 RC |
206 | int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
207 | struct drm_mode_create_dumb *args); | |
208 | int omap_gem_mmap(struct file *filp, struct vm_area_struct *vma); | |
8b6b569e RC |
209 | int omap_gem_mmap_obj(struct drm_gem_object *obj, |
210 | struct vm_area_struct *vma); | |
cd5351f4 RC |
211 | int omap_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
212 | int omap_gem_op_start(struct drm_gem_object *obj, enum omap_gem_op op); | |
213 | int omap_gem_op_finish(struct drm_gem_object *obj, enum omap_gem_op op); | |
214 | int omap_gem_op_sync(struct drm_gem_object *obj, enum omap_gem_op op); | |
215 | int omap_gem_op_async(struct drm_gem_object *obj, enum omap_gem_op op, | |
216 | void (*fxn)(void *arg), void *arg); | |
a6a91827 | 217 | int omap_gem_roll(struct drm_gem_object *obj, uint32_t roll); |
8b6b569e RC |
218 | void omap_gem_cpu_sync(struct drm_gem_object *obj, int pgoff); |
219 | void omap_gem_dma_sync(struct drm_gem_object *obj, | |
220 | enum dma_data_direction dir); | |
cd5351f4 RC |
221 | int omap_gem_get_paddr(struct drm_gem_object *obj, |
222 | dma_addr_t *paddr, bool remap); | |
223 | int omap_gem_put_paddr(struct drm_gem_object *obj); | |
6ad11bc3 RC |
224 | int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages, |
225 | bool remap); | |
226 | int omap_gem_put_pages(struct drm_gem_object *obj); | |
227 | uint32_t omap_gem_flags(struct drm_gem_object *obj); | |
3c810c61 RC |
228 | int omap_gem_rotated_paddr(struct drm_gem_object *obj, uint32_t orient, |
229 | int x, int y, dma_addr_t *paddr); | |
cd5351f4 | 230 | uint64_t omap_gem_mmap_offset(struct drm_gem_object *obj); |
f7f9f453 | 231 | size_t omap_gem_mmap_size(struct drm_gem_object *obj); |
3c810c61 RC |
232 | int omap_gem_tiled_size(struct drm_gem_object *obj, uint16_t *w, uint16_t *h); |
233 | int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient); | |
cd5351f4 | 234 | |
7ced63cf | 235 | struct dma_buf *omap_gem_prime_export(struct drm_device *dev, |
6ad11bc3 | 236 | struct drm_gem_object *obj, int flags); |
7ced63cf | 237 | struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev, |
3080b838 | 238 | struct dma_buf *buffer); |
6ad11bc3 | 239 | |
cd5351f4 RC |
240 | static inline int align_pitch(int pitch, int width, int bpp) |
241 | { | |
242 | int bytespp = (bpp + 7) / 8; | |
243 | /* in case someone tries to feed us a completely bogus stride: */ | |
244 | pitch = max(pitch, width * bytespp); | |
245 | /* PVR needs alignment to 8 pixels.. right now that is the most | |
246 | * restrictive stride requirement.. | |
247 | */ | |
248 | return ALIGN(pitch, 8 * bytespp); | |
249 | } | |
250 | ||
f5f9454c | 251 | /* map crtc to vblank mask */ |
0d8f371f AT |
252 | uint32_t pipe2vbl(struct drm_crtc *crtc); |
253 | struct omap_dss_device *omap_encoder_get_dssdev(struct drm_encoder *encoder); | |
f5f9454c | 254 | |
ae43d7ca RC |
255 | /* should these be made into common util helpers? |
256 | */ | |
257 | ||
258 | static inline int objects_lookup(struct drm_device *dev, | |
259 | struct drm_file *filp, uint32_t pixel_format, | |
260 | struct drm_gem_object **bos, uint32_t *handles) | |
261 | { | |
262 | int i, n = drm_format_num_planes(pixel_format); | |
263 | ||
264 | for (i = 0; i < n; i++) { | |
265 | bos[i] = drm_gem_object_lookup(dev, filp, handles[i]); | |
bc1e1581 | 266 | if (!bos[i]) |
ae43d7ca | 267 | goto fail; |
bc1e1581 | 268 | |
ae43d7ca RC |
269 | } |
270 | ||
271 | return 0; | |
272 | ||
273 | fail: | |
bc1e1581 | 274 | while (--i > 0) |
ae43d7ca | 275 | drm_gem_object_unreference_unlocked(bos[i]); |
bc1e1581 | 276 | |
ae43d7ca RC |
277 | return -ENOENT; |
278 | } | |
279 | ||
cd5351f4 | 280 | #endif /* __OMAP_DRV_H__ */ |