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drm/panel: simple: Remove useless drm_mode_set_name()
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
795f7ab3
BB		 73
74 u32 bus_format;
f0aa0838 75 u32 bus_flags;
280921de
TR		 76};
77
280921de
TR		 78struct panel_simple {
79 struct drm_panel base;
613a633e 80 bool prepared;
280921de
TR		 81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
cfdf0549 89 struct gpio_desc *enable_gpio;
280921de
TR		 90};
91
92static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93{
94 return container_of(panel, struct panel_simple, base);
95}
96
97static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98{
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
a5d3e625
PZ		 107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
123 if (panel->desc->num_modes == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
a5d3e625
PZ		 126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
280921de
TR		 130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
cda55372
BB		 140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
280921de
TR		 145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
0208d511 151 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
f0aa0838 157 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 158
159 return num;
160}
161
162static int panel_simple_disable(struct drm_panel *panel)
163{
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 backlight_update_status(p->backlight);
172 }
173
f673c37e
AK		 174 if (p->desc->delay.disable)
175 msleep(p->desc->delay.disable);
176
280921de
TR		 177 p->enabled = false;
178
179 return 0;
180}
181
c0e1d170
AK		 182static int panel_simple_unprepare(struct drm_panel *panel)
183{
613a633e
AK		 184 struct panel_simple *p = to_panel_simple(panel);
185
186 if (!p->prepared)
187 return 0;
188
189 if (p->enable_gpio)
190 gpiod_set_value_cansleep(p->enable_gpio, 0);
191
192 regulator_disable(p->supply);
193
f673c37e
AK		 194 if (p->desc->delay.unprepare)
195 msleep(p->desc->delay.unprepare);
196
613a633e 197 p->prepared = false;
c0e1d170 198
c0e1d170
AK		 199 return 0;
200}
201
613a633e 202static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 203{
204 struct panel_simple *p = to_panel_simple(panel);
205 int err;
206
613a633e 207 if (p->prepared)
280921de
TR		 208 return 0;
209
210 err = regulator_enable(p->supply);
211 if (err < 0) {
212 dev_err(panel->dev, "failed to enable supply: %d\n", err);
213 return err;
214 }
215
cfdf0549 216 if (p->enable_gpio)
15c1a919 217 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 218
f673c37e
AK		 219 if (p->desc->delay.prepare)
220 msleep(p->desc->delay.prepare);
221
613a633e
AK		 222 p->prepared = true;
223
224 return 0;
225}
226
227static int panel_simple_enable(struct drm_panel *panel)
228{
229 struct panel_simple *p = to_panel_simple(panel);
230
231 if (p->enabled)
232 return 0;
233
f673c37e
AK		 234 if (p->desc->delay.enable)
235 msleep(p->desc->delay.enable);
236
280921de
TR		 237 if (p->backlight) {
238 p->backlight->props.power = FB_BLANK_UNBLANK;
239 backlight_update_status(p->backlight);
240 }
241
242 p->enabled = true;
243
244 return 0;
245}
246
247static int panel_simple_get_modes(struct drm_panel *panel)
248{
249 struct panel_simple *p = to_panel_simple(panel);
250 int num = 0;
251
252 /* probe EDID if a DDC bus is available */
253 if (p->ddc) {
254 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 255 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 256 if (edid) {
257 num += drm_add_edid_modes(panel->connector, edid);
258 kfree(edid);
259 }
260 }
261
262 /* add hard-coded panel modes */
263 num += panel_simple_get_fixed_modes(p);
264
265 return num;
266}
267
a5d3e625
PZ		 268static int panel_simple_get_timings(struct drm_panel *panel,
269 unsigned int num_timings,
270 struct display_timing *timings)
271{
272 struct panel_simple *p = to_panel_simple(panel);
273 unsigned int i;
274
275 if (p->desc->num_timings < num_timings)
276 num_timings = p->desc->num_timings;
277
278 if (timings)
279 for (i = 0; i < num_timings; i++)
280 timings[i] = p->desc->timings[i];
281
282 return p->desc->num_timings;
283}
284
280921de
TR		 285static const struct drm_panel_funcs panel_simple_funcs = {
286 .disable = panel_simple_disable,
c0e1d170
AK		 287 .unprepare = panel_simple_unprepare,
288 .prepare = panel_simple_prepare,
280921de
TR		 289 .enable = panel_simple_enable,
290 .get_modes = panel_simple_get_modes,
a5d3e625 291 .get_timings = panel_simple_get_timings,
280921de
TR		 292};
293
294static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
295{
296 struct device_node *backlight, *ddc;
297 struct panel_simple *panel;
280921de
TR		 298 int err;
299
300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
301 if (!panel)
302 return -ENOMEM;
303
304 panel->enabled = false;
613a633e 305 panel->prepared = false;
280921de
TR		 306 panel->desc = desc;
307
308 panel->supply = devm_regulator_get(dev, "power");
309 if (IS_ERR(panel->supply))
310 return PTR_ERR(panel->supply);
311
a61400d8
AC		 312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
313 GPIOD_OUT_LOW);
cfdf0549
AC		 314 if (IS_ERR(panel->enable_gpio)) {
315 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 316 dev_err(dev, "failed to request GPIO: %d\n", err);
317 return err;
318 }
280921de 319
280921de
TR		 320 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
321 if (backlight) {
322 panel->backlight = of_find_backlight_by_node(backlight);
323 of_node_put(backlight);
324
cfdf0549
AC		 325 if (!panel->backlight)
326 return -EPROBE_DEFER;
280921de
TR		 327 }
328
329 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
330 if (ddc) {
331 panel->ddc = of_find_i2c_adapter_by_node(ddc);
332 of_node_put(ddc);
333
334 if (!panel->ddc) {
335 err = -EPROBE_DEFER;
336 goto free_backlight;
337 }
338 }
339
340 drm_panel_init(&panel->base);
341 panel->base.dev = dev;
342 panel->base.funcs = &panel_simple_funcs;
343
344 err = drm_panel_add(&panel->base);
345 if (err < 0)
346 goto free_ddc;
347
348 dev_set_drvdata(dev, panel);
349
350 return 0;
351
352free_ddc:
353 if (panel->ddc)
354 put_device(&panel->ddc->dev);
355free_backlight:
356 if (panel->backlight)
357 put_device(&panel->backlight->dev);
280921de
TR		 358
359 return err;
360}
361
362static int panel_simple_remove(struct device *dev)
363{
364 struct panel_simple *panel = dev_get_drvdata(dev);
365
366 drm_panel_detach(&panel->base);
367 drm_panel_remove(&panel->base);
368
369 panel_simple_disable(&panel->base);
370
371 if (panel->ddc)
372 put_device(&panel->ddc->dev);
373
374 if (panel->backlight)
375 put_device(&panel->backlight->dev);
376
280921de
TR		 377 return 0;
378}
379
d02fd93e
TR		 380static void panel_simple_shutdown(struct device *dev)
381{
382 struct panel_simple *panel = dev_get_drvdata(dev);
383
384 panel_simple_disable(&panel->base);
385}
386
1c550fa1
PZ		 387static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
388 .clock = 33333,
389 .hdisplay = 800,
390 .hsync_start = 800 + 0,
391 .hsync_end = 800 + 0 + 255,
392 .htotal = 800 + 0 + 255 + 0,
393 .vdisplay = 480,
394 .vsync_start = 480 + 2,
395 .vsync_end = 480 + 2 + 45,
396 .vtotal = 480 + 2 + 45 + 0,
397 .vrefresh = 60,
398 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
399};
400
401static const struct panel_desc ampire_am800480r3tmqwa1h = {
402 .modes = &ampire_am800480r3tmqwa1h_mode,
403 .num_modes = 1,
404 .bpc = 6,
405 .size = {
406 .width = 152,
407 .height = 91,
408 },
409 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
410};
411
280921de
TR		 412static const struct drm_display_mode auo_b101aw03_mode = {
413 .clock = 51450,
414 .hdisplay = 1024,
415 .hsync_start = 1024 + 156,
416 .hsync_end = 1024 + 156 + 8,
417 .htotal = 1024 + 156 + 8 + 156,
418 .vdisplay = 600,
419 .vsync_start = 600 + 16,
420 .vsync_end = 600 + 16 + 6,
421 .vtotal = 600 + 16 + 6 + 16,
422 .vrefresh = 60,
423};
424
425static const struct panel_desc auo_b101aw03 = {
426 .modes = &auo_b101aw03_mode,
427 .num_modes = 1,
0208d511 428 .bpc = 6,
280921de
TR		 429 .size = {
430 .width = 223,
431 .height = 125,
432 },
433};
434
a531bc3d
HL		 435static const struct drm_display_mode auo_b101ean01_mode = {
436 .clock = 72500,
437 .hdisplay = 1280,
438 .hsync_start = 1280 + 119,
439 .hsync_end = 1280 + 119 + 32,
440 .htotal = 1280 + 119 + 32 + 21,
441 .vdisplay = 800,
442 .vsync_start = 800 + 4,
443 .vsync_end = 800 + 4 + 20,
444 .vtotal = 800 + 4 + 20 + 8,
445 .vrefresh = 60,
446};
447
448static const struct panel_desc auo_b101ean01 = {
449 .modes = &auo_b101ean01_mode,
450 .num_modes = 1,
451 .bpc = 6,
452 .size = {
453 .width = 217,
454 .height = 136,
455 },
456};
457
dac746e0
RC		 458static const struct drm_display_mode auo_b101xtn01_mode = {
459 .clock = 72000,
460 .hdisplay = 1366,
461 .hsync_start = 1366 + 20,
462 .hsync_end = 1366 + 20 + 70,
463 .htotal = 1366 + 20 + 70,
464 .vdisplay = 768,
465 .vsync_start = 768 + 14,
466 .vsync_end = 768 + 14 + 42,
467 .vtotal = 768 + 14 + 42,
468 .vrefresh = 60,
469 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
470};
471
472static const struct panel_desc auo_b101xtn01 = {
473 .modes = &auo_b101xtn01_mode,
474 .num_modes = 1,
475 .bpc = 6,
476 .size = {
477 .width = 223,
478 .height = 125,
479 },
480};
481
e35e305e
AK		 482static const struct drm_display_mode auo_b116xw03_mode = {
483 .clock = 70589,
484 .hdisplay = 1366,
485 .hsync_start = 1366 + 40,
486 .hsync_end = 1366 + 40 + 40,
487 .htotal = 1366 + 40 + 40 + 32,
488 .vdisplay = 768,
489 .vsync_start = 768 + 10,
490 .vsync_end = 768 + 10 + 12,
491 .vtotal = 768 + 10 + 12 + 6,
492 .vrefresh = 60,
493};
494
495static const struct panel_desc auo_b116xw03 = {
496 .modes = &auo_b116xw03_mode,
497 .num_modes = 1,
498 .bpc = 6,
499 .size = {
500 .width = 256,
501 .height = 144,
502 },
503};
504
a333f7ad
SM		 505static const struct drm_display_mode auo_b133xtn01_mode = {
506 .clock = 69500,
507 .hdisplay = 1366,
508 .hsync_start = 1366 + 48,
509 .hsync_end = 1366 + 48 + 32,
510 .htotal = 1366 + 48 + 32 + 20,
511 .vdisplay = 768,
512 .vsync_start = 768 + 3,
513 .vsync_end = 768 + 3 + 6,
514 .vtotal = 768 + 3 + 6 + 13,
515 .vrefresh = 60,
516};
517
518static const struct panel_desc auo_b133xtn01 = {
519 .modes = &auo_b133xtn01_mode,
520 .num_modes = 1,
0208d511 521 .bpc = 6,
a333f7ad
SM		 522 .size = {
523 .width = 293,
524 .height = 165,
525 },
526};
527
3e51d609
AK		 528static const struct drm_display_mode auo_b133htn01_mode = {
529 .clock = 150660,
530 .hdisplay = 1920,
531 .hsync_start = 1920 + 172,
532 .hsync_end = 1920 + 172 + 80,
533 .htotal = 1920 + 172 + 80 + 60,
534 .vdisplay = 1080,
535 .vsync_start = 1080 + 25,
536 .vsync_end = 1080 + 25 + 10,
537 .vtotal = 1080 + 25 + 10 + 10,
538 .vrefresh = 60,
539};
540
541static const struct panel_desc auo_b133htn01 = {
542 .modes = &auo_b133htn01_mode,
543 .num_modes = 1,
d7a839cd 544 .bpc = 6,
3e51d609
AK		 545 .size = {
546 .width = 293,
547 .height = 165,
548 },
549 .delay = {
550 .prepare = 105,
551 .enable = 20,
552 .unprepare = 50,
553 },
554};
555
d47df633
PZ		 556static const struct drm_display_mode avic_tm070ddh03_mode = {
557 .clock = 51200,
558 .hdisplay = 1024,
559 .hsync_start = 1024 + 160,
560 .hsync_end = 1024 + 160 + 4,
561 .htotal = 1024 + 160 + 4 + 156,
562 .vdisplay = 600,
563 .vsync_start = 600 + 17,
564 .vsync_end = 600 + 17 + 1,
565 .vtotal = 600 + 17 + 1 + 17,
566 .vrefresh = 60,
567};
568
569static const struct panel_desc avic_tm070ddh03 = {
570 .modes = &avic_tm070ddh03_mode,
571 .num_modes = 1,
572 .bpc = 8,
573 .size = {
574 .width = 154,
575 .height = 90,
576 },
577 .delay = {
578 .prepare = 20,
579 .enable = 200,
580 .disable = 200,
581 },
582};
583
4c930757
SW		 584static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
585 .clock = 72070,
586 .hdisplay = 1366,
587 .hsync_start = 1366 + 58,
588 .hsync_end = 1366 + 58 + 58,
589 .htotal = 1366 + 58 + 58 + 58,
590 .vdisplay = 768,
591 .vsync_start = 768 + 4,
592 .vsync_end = 768 + 4 + 4,
593 .vtotal = 768 + 4 + 4 + 4,
594 .vrefresh = 60,
595};
596
597static const struct panel_desc chunghwa_claa101wa01a = {
598 .modes = &chunghwa_claa101wa01a_mode,
599 .num_modes = 1,
0208d511 600 .bpc = 6,
4c930757
SW		 601 .size = {
602 .width = 220,
603 .height = 120,
604 },
605};
606
280921de
TR		 607static const struct drm_display_mode chunghwa_claa101wb01_mode = {
608 .clock = 69300,
609 .hdisplay = 1366,
610 .hsync_start = 1366 + 48,
611 .hsync_end = 1366 + 48 + 32,
612 .htotal = 1366 + 48 + 32 + 20,
613 .vdisplay = 768,
614 .vsync_start = 768 + 16,
615 .vsync_end = 768 + 16 + 8,
616 .vtotal = 768 + 16 + 8 + 16,
617 .vrefresh = 60,
618};
619
620static const struct panel_desc chunghwa_claa101wb01 = {
621 .modes = &chunghwa_claa101wb01_mode,
622 .num_modes = 1,
0208d511 623 .bpc = 6,
280921de
TR		 624 .size = {
625 .width = 223,
626 .height = 125,
627 },
628};
629
26ab0065
SA		 630static const struct drm_display_mode edt_et057090dhu_mode = {
631 .clock = 25175,
632 .hdisplay = 640,
633 .hsync_start = 640 + 16,
634 .hsync_end = 640 + 16 + 30,
635 .htotal = 640 + 16 + 30 + 114,
636 .vdisplay = 480,
637 .vsync_start = 480 + 10,
638 .vsync_end = 480 + 10 + 3,
639 .vtotal = 480 + 10 + 3 + 32,
640 .vrefresh = 60,
641 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
642};
643
644static const struct panel_desc edt_et057090dhu = {
645 .modes = &edt_et057090dhu_mode,
646 .num_modes = 1,
0208d511 647 .bpc = 6,
26ab0065
SA		 648 .size = {
649 .width = 115,
650 .height = 86,
651 },
652};
653
fff5de45
PZ		 654static const struct drm_display_mode edt_etm0700g0dh6_mode = {
655 .clock = 33260,
656 .hdisplay = 800,
657 .hsync_start = 800 + 40,
658 .hsync_end = 800 + 40 + 128,
659 .htotal = 800 + 40 + 128 + 88,
660 .vdisplay = 480,
661 .vsync_start = 480 + 10,
662 .vsync_end = 480 + 10 + 2,
663 .vtotal = 480 + 10 + 2 + 33,
664 .vrefresh = 60,
665 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
666};
667
668static const struct panel_desc edt_etm0700g0dh6 = {
669 .modes = &edt_etm0700g0dh6_mode,
670 .num_modes = 1,
0208d511 671 .bpc = 6,
fff5de45
PZ		 672 .size = {
673 .width = 152,
674 .height = 91,
675 },
676};
677
102932b0
BB		 678static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
679 .clock = 32260,
680 .hdisplay = 800,
681 .hsync_start = 800 + 168,
682 .hsync_end = 800 + 168 + 64,
683 .htotal = 800 + 168 + 64 + 88,
684 .vdisplay = 480,
685 .vsync_start = 480 + 37,
686 .vsync_end = 480 + 37 + 2,
687 .vtotal = 480 + 37 + 2 + 8,
688 .vrefresh = 60,
689};
690
691static const struct panel_desc foxlink_fl500wvr00_a0t = {
692 .modes = &foxlink_fl500wvr00_a0t_mode,
693 .num_modes = 1,
d7a839cd 694 .bpc = 8,
102932b0
BB		 695 .size = {
696 .width = 108,
697 .height = 65,
698 },
bb276cb3 699 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 700};
701
d435a2af
PZ		 702static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
703 .clock = 9000,
704 .hdisplay = 480,
705 .hsync_start = 480 + 5,
706 .hsync_end = 480 + 5 + 1,
707 .htotal = 480 + 5 + 1 + 40,
708 .vdisplay = 272,
709 .vsync_start = 272 + 8,
710 .vsync_end = 272 + 8 + 1,
711 .vtotal = 272 + 8 + 1 + 8,
712 .vrefresh = 60,
713};
714
715static const struct panel_desc giantplus_gpg482739qs5 = {
716 .modes = &giantplus_gpg482739qs5_mode,
717 .num_modes = 1,
718 .bpc = 8,
719 .size = {
720 .width = 95,
721 .height = 54,
722 },
33536a09 723 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 724};
725
ab07725a
PZ		 726static const struct display_timing hannstar_hsd070pww1_timing = {
727 .pixelclock = { 64300000, 71100000, 82000000 },
728 .hactive = { 1280, 1280, 1280 },
729 .hfront_porch = { 1, 1, 10 },
730 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 731 /*
732 * According to the data sheet, the minimum horizontal blanking interval
733 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
734 * minimum working horizontal blanking interval to be 60 clocks.
735 */
736 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 737 .vactive = { 800, 800, 800 },
738 .vfront_porch = { 1, 1, 10 },
739 .vback_porch = { 1, 1, 10 },
740 .vsync_len = { 1, 21, 203 },
741 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 742};
743
744static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 745 .timings = &hannstar_hsd070pww1_timing,
746 .num_timings = 1,
a853205e
PZ		 747 .bpc = 6,
748 .size = {
749 .width = 151,
750 .height = 94,
751 },
58d6a7bc 752 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 753};
754
c0d607e5
EN		 755static const struct display_timing hannstar_hsd100pxn1_timing = {
756 .pixelclock = { 55000000, 65000000, 75000000 },
757 .hactive = { 1024, 1024, 1024 },
758 .hfront_porch = { 40, 40, 40 },
759 .hback_porch = { 220, 220, 220 },
760 .hsync_len = { 20, 60, 100 },
761 .vactive = { 768, 768, 768 },
762 .vfront_porch = { 7, 7, 7 },
763 .vback_porch = { 21, 21, 21 },
764 .vsync_len = { 10, 10, 10 },
765 .flags = DISPLAY_FLAGS_DE_HIGH,
766};
767
768static const struct panel_desc hannstar_hsd100pxn1 = {
769 .timings = &hannstar_hsd100pxn1_timing,
770 .num_timings = 1,
771 .bpc = 6,
772 .size = {
773 .width = 203,
774 .height = 152,
775 },
4946b043 776 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 777};
778
61ac0bf8
LS		 779static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
780 .clock = 33333,
781 .hdisplay = 800,
782 .hsync_start = 800 + 85,
783 .hsync_end = 800 + 85 + 86,
784 .htotal = 800 + 85 + 86 + 85,
785 .vdisplay = 480,
786 .vsync_start = 480 + 16,
787 .vsync_end = 480 + 16 + 13,
788 .vtotal = 480 + 16 + 13 + 16,
789 .vrefresh = 60,
790};
791
792static const struct panel_desc hitachi_tx23d38vm0caa = {
793 .modes = &hitachi_tx23d38vm0caa_mode,
794 .num_modes = 1,
795 .bpc = 6,
796 .size = {
797 .width = 195,
798 .height = 117,
799 },
800};
801
41bcceb4
NF		 802static const struct drm_display_mode innolux_at043tn24_mode = {
803 .clock = 9000,
804 .hdisplay = 480,
805 .hsync_start = 480 + 2,
806 .hsync_end = 480 + 2 + 41,
807 .htotal = 480 + 2 + 41 + 2,
808 .vdisplay = 272,
809 .vsync_start = 272 + 2,
810 .vsync_end = 272 + 2 + 11,
811 .vtotal = 272 + 2 + 11 + 2,
812 .vrefresh = 60,
813 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
814};
815
816static const struct panel_desc innolux_at043tn24 = {
817 .modes = &innolux_at043tn24_mode,
818 .num_modes = 1,
819 .bpc = 8,
820 .size = {
821 .width = 95,
822 .height = 54,
823 },
824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
825};
826
d731f661 827static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 828 .clock = 71000,
d731f661
LS		 829 .hdisplay = 1280,
830 .hsync_start = 1280 + 64,
831 .hsync_end = 1280 + 64 + 32,
832 .htotal = 1280 + 64 + 32 + 64,
833 .vdisplay = 800,
834 .vsync_start = 800 + 9,
835 .vsync_end = 800 + 9 + 6,
836 .vtotal = 800 + 9 + 6 + 9,
837 .vrefresh = 60,
838};
839
840static const struct panel_desc innolux_g121i1_l01 = {
841 .modes = &innolux_g121i1_l01_mode,
842 .num_modes = 1,
843 .bpc = 6,
844 .size = {
845 .width = 261,
846 .height = 163,
847 },
848};
849
f8fa17ba
AB		 850static const struct drm_display_mode innolux_g121x1_l03_mode = {
851 .clock = 65000,
852 .hdisplay = 1024,
853 .hsync_start = 1024 + 0,
854 .hsync_end = 1024 + 1,
855 .htotal = 1024 + 0 + 1 + 320,
856 .vdisplay = 768,
857 .vsync_start = 768 + 38,
858 .vsync_end = 768 + 38 + 1,
859 .vtotal = 768 + 38 + 1 + 0,
860 .vrefresh = 60,
2e8c5eb9 861 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 862};
863
864static const struct panel_desc innolux_g121x1_l03 = {
865 .modes = &innolux_g121x1_l03_mode,
866 .num_modes = 1,
867 .bpc = 6,
868 .size = {
869 .width = 246,
870 .height = 185,
871 },
872 .delay = {
873 .enable = 200,
874 .unprepare = 200,
875 .disable = 400,
876 },
877};
878
0a2288c0 879static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 880 .clock = 76420,
0a2288c0 881 .hdisplay = 1366,
7fe8c777
DK		 882 .hsync_start = 1366 + 136,
883 .hsync_end = 1366 + 136 + 30,
884 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 885 .vdisplay = 768,
886 .vsync_start = 768 + 8,
7fe8c777
DK		 887 .vsync_end = 768 + 8 + 12,
888 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 889 .vrefresh = 60,
890 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
891};
892
893static const struct panel_desc innolux_n116bge = {
894 .modes = &innolux_n116bge_mode,
895 .num_modes = 1,
896 .bpc = 6,
897 .size = {
898 .width = 256,
899 .height = 144,
900 },
901};
902
ea44739d
AB		 903static const struct drm_display_mode innolux_n156bge_l21_mode = {
904 .clock = 69300,
905 .hdisplay = 1366,
906 .hsync_start = 1366 + 16,
907 .hsync_end = 1366 + 16 + 34,
908 .htotal = 1366 + 16 + 34 + 50,
909 .vdisplay = 768,
910 .vsync_start = 768 + 2,
911 .vsync_end = 768 + 2 + 6,
912 .vtotal = 768 + 2 + 6 + 12,
913 .vrefresh = 60,
914};
915
916static const struct panel_desc innolux_n156bge_l21 = {
917 .modes = &innolux_n156bge_l21_mode,
918 .num_modes = 1,
0208d511 919 .bpc = 6,
ea44739d
AB		 920 .size = {
921 .width = 344,
922 .height = 193,
923 },
924};
925
bccac3f1
MG		 926static const struct drm_display_mode innolux_zj070na_01p_mode = {
927 .clock = 51501,
928 .hdisplay = 1024,
929 .hsync_start = 1024 + 128,
930 .hsync_end = 1024 + 128 + 64,
931 .htotal = 1024 + 128 + 64 + 128,
932 .vdisplay = 600,
933 .vsync_start = 600 + 16,
934 .vsync_end = 600 + 16 + 4,
935 .vtotal = 600 + 16 + 4 + 16,
936 .vrefresh = 60,
937};
938
939static const struct panel_desc innolux_zj070na_01p = {
940 .modes = &innolux_zj070na_01p_mode,
941 .num_modes = 1,
942 .bpc = 6,
943 .size = {
944 .width = 1024,
945 .height = 600,
946 },
947};
948
8def22e5
LS		 949static const struct display_timing kyo_tcg121xglp_timing = {
950 .pixelclock = { 52000000, 65000000, 71000000 },
951 .hactive = { 1024, 1024, 1024 },
952 .hfront_porch = { 2, 2, 2 },
953 .hback_porch = { 2, 2, 2 },
954 .hsync_len = { 86, 124, 244 },
955 .vactive = { 768, 768, 768 },
956 .vfront_porch = { 2, 2, 2 },
957 .vback_porch = { 2, 2, 2 },
958 .vsync_len = { 6, 34, 73 },
959 .flags = DISPLAY_FLAGS_DE_HIGH,
960};
961
962static const struct panel_desc kyo_tcg121xglp = {
963 .timings = &kyo_tcg121xglp_timing,
964 .num_timings = 1,
965 .bpc = 8,
966 .size = {
967 .width = 246,
968 .height = 184,
969 },
970 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
971};
972
dd015002
HS		 973static const struct drm_display_mode lg_lb070wv8_mode = {
974 .clock = 33246,
975 .hdisplay = 800,
976 .hsync_start = 800 + 88,
977 .hsync_end = 800 + 88 + 80,
978 .htotal = 800 + 88 + 80 + 88,
979 .vdisplay = 480,
980 .vsync_start = 480 + 10,
981 .vsync_end = 480 + 10 + 25,
982 .vtotal = 480 + 10 + 25 + 10,
983 .vrefresh = 60,
984};
985
986static const struct panel_desc lg_lb070wv8 = {
987 .modes = &lg_lb070wv8_mode,
988 .num_modes = 1,
989 .bpc = 16,
990 .size = {
991 .width = 151,
992 .height = 91,
993 },
994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
995};
996
690d8fa7
JS		 997static const struct drm_display_mode lg_lp120up1_mode = {
998 .clock = 162300,
999 .hdisplay = 1920,
1000 .hsync_start = 1920 + 40,
1001 .hsync_end = 1920 + 40 + 40,
1002 .htotal = 1920 + 40 + 40+ 80,
1003 .vdisplay = 1280,
1004 .vsync_start = 1280 + 4,
1005 .vsync_end = 1280 + 4 + 4,
1006 .vtotal = 1280 + 4 + 4 + 12,
1007 .vrefresh = 60,
1008};
1009
1010static const struct panel_desc lg_lp120up1 = {
1011 .modes = &lg_lp120up1_mode,
1012 .num_modes = 1,
1013 .bpc = 8,
1014 .size = {
1015 .width = 267,
1016 .height = 183,
1017 },
1018};
1019
ec7c5653
TR		 1020static const struct drm_display_mode lg_lp129qe_mode = {
1021 .clock = 285250,
1022 .hdisplay = 2560,
1023 .hsync_start = 2560 + 48,
1024 .hsync_end = 2560 + 48 + 32,
1025 .htotal = 2560 + 48 + 32 + 80,
1026 .vdisplay = 1700,
1027 .vsync_start = 1700 + 3,
1028 .vsync_end = 1700 + 3 + 10,
1029 .vtotal = 1700 + 3 + 10 + 36,
1030 .vrefresh = 60,
1031};
1032
1033static const struct panel_desc lg_lp129qe = {
1034 .modes = &lg_lp129qe_mode,
1035 .num_modes = 1,
0208d511 1036 .bpc = 8,
ec7c5653
TR		 1037 .size = {
1038 .width = 272,
1039 .height = 181,
1040 },
1041};
1042
c6e87f91 1043static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1044 .clock = 10870,
1045 .hdisplay = 480,
1046 .hsync_start = 480 + 2,
1047 .hsync_end = 480 + 2 + 41,
1048 .htotal = 480 + 2 + 41 + 2,
1049 .vdisplay = 272,
1050 .vsync_start = 272 + 2,
1051 .vsync_end = 272 + 2 + 4,
1052 .vtotal = 272 + 2 + 4 + 2,
1053 .vrefresh = 74,
4bc390c6 1054 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1055};
1056
1057static const struct panel_desc nec_nl4827hc19_05b = {
1058 .modes = &nec_nl4827hc19_05b_mode,
1059 .num_modes = 1,
1060 .bpc = 8,
1061 .size = {
1062 .width = 95,
1063 .height = 54,
1064 },
2c80661d
SA		 1065 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1066 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
c6e87f91 1067};
1068
a99fb626
GB		 1069static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1070 .pixelclock = { 30000000, 30000000, 40000000 },
1071 .hactive = { 800, 800, 800 },
1072 .hfront_porch = { 40, 40, 40 },
1073 .hback_porch = { 40, 40, 40 },
1074 .hsync_len = { 1, 48, 48 },
1075 .vactive = { 480, 480, 480 },
1076 .vfront_porch = { 13, 13, 13 },
1077 .vback_porch = { 29, 29, 29 },
1078 .vsync_len = { 3, 3, 3 },
1079 .flags = DISPLAY_FLAGS_DE_HIGH,
1080};
1081
1082static const struct panel_desc okaya_rs800480t_7x0gp = {
1083 .timings = &okaya_rs800480t_7x0gp_timing,
1084 .num_timings = 1,
1085 .bpc = 6,
1086 .size = {
1087 .width = 154,
1088 .height = 87,
1089 },
1090 .delay = {
1091 .prepare = 41,
1092 .enable = 50,
1093 .unprepare = 41,
1094 .disable = 50,
1095 },
1096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1097};
1098
cf5c9e6d
MR		 1099static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1100 .clock = 9000,
1101 .hdisplay = 480,
1102 .hsync_start = 480 + 5,
1103 .hsync_end = 480 + 5 + 30,
1104 .htotal = 480 + 5 + 30 + 10,
1105 .vdisplay = 272,
1106 .vsync_start = 272 + 8,
1107 .vsync_end = 272 + 8 + 5,
1108 .vtotal = 272 + 8 + 5 + 3,
1109 .vrefresh = 60,
1110};
1111
1112static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1113 .modes = &olimex_lcd_olinuxino_43ts_mode,
1114 .num_modes = 1,
1115 .size = {
1116 .width = 105,
1117 .height = 67,
1118 },
1119 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1120};
1121
e8b6f561
EA		 1122/*
1123 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1124 * pixel clocks, but this is the timing that was being used in the Adafruit
1125 * installation instructions.
1126 */
1127static const struct drm_display_mode ontat_yx700wv03_mode = {
1128 .clock = 29500,
1129 .hdisplay = 800,
1130 .hsync_start = 824,
1131 .hsync_end = 896,
1132 .htotal = 992,
1133 .vdisplay = 480,
1134 .vsync_start = 483,
1135 .vsync_end = 493,
1136 .vtotal = 500,
1137 .vrefresh = 60,
1138 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1139};
1140
1141/*
1142 * Specification at:
1143 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1144 */
1145static const struct panel_desc ontat_yx700wv03 = {
1146 .modes = &ontat_yx700wv03_mode,
1147 .num_modes = 1,
1148 .bpc = 8,
1149 .size = {
1150 .width = 154,
1151 .height = 83,
1152 },
1153 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1154};
1155
725c9d40
PZ		 1156static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1157 .clock = 25000,
1158 .hdisplay = 480,
1159 .hsync_start = 480 + 10,
1160 .hsync_end = 480 + 10 + 10,
1161 .htotal = 480 + 10 + 10 + 15,
1162 .vdisplay = 800,
1163 .vsync_start = 800 + 3,
1164 .vsync_end = 800 + 3 + 3,
1165 .vtotal = 800 + 3 + 3 + 3,
1166 .vrefresh = 60,
1167};
1168
1169static const struct panel_desc ortustech_com43h4m85ulc = {
1170 .modes = &ortustech_com43h4m85ulc_mode,
1171 .num_modes = 1,
1172 .bpc = 8,
1173 .size = {
1174 .width = 56,
1175 .height = 93,
1176 },
1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1178};
1179
d2a6f0f5
JW		 1180static const struct drm_display_mode qd43003c0_40_mode = {
1181 .clock = 9000,
1182 .hdisplay = 480,
1183 .hsync_start = 480 + 8,
1184 .hsync_end = 480 + 8 + 4,
1185 .htotal = 480 + 8 + 4 + 39,
1186 .vdisplay = 272,
1187 .vsync_start = 272 + 4,
1188 .vsync_end = 272 + 4 + 10,
1189 .vtotal = 272 + 4 + 10 + 2,
1190 .vrefresh = 60,
1191};
1192
1193static const struct panel_desc qd43003c0_40 = {
1194 .modes = &qd43003c0_40_mode,
1195 .num_modes = 1,
1196 .bpc = 8,
1197 .size = {
1198 .width = 95,
1199 .height = 53,
1200 },
1201 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1202};
1203
6d54e3d2
MD		 1204static const struct drm_display_mode samsung_ltn101nt05_mode = {
1205 .clock = 54030,
1206 .hdisplay = 1024,
1207 .hsync_start = 1024 + 24,
1208 .hsync_end = 1024 + 24 + 136,
1209 .htotal = 1024 + 24 + 136 + 160,
1210 .vdisplay = 600,
1211 .vsync_start = 600 + 3,
1212 .vsync_end = 600 + 3 + 6,
1213 .vtotal = 600 + 3 + 6 + 61,
1214 .vrefresh = 60,
1215};
1216
1217static const struct panel_desc samsung_ltn101nt05 = {
1218 .modes = &samsung_ltn101nt05_mode,
1219 .num_modes = 1,
0208d511 1220 .bpc = 6,
6d54e3d2
MD		 1221 .size = {
1222 .width = 1024,
1223 .height = 600,
1224 },
1225};
1226
0c934306
SM		 1227static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1228 .clock = 76300,
1229 .hdisplay = 1366,
1230 .hsync_start = 1366 + 64,
1231 .hsync_end = 1366 + 64 + 48,
1232 .htotal = 1366 + 64 + 48 + 128,
1233 .vdisplay = 768,
1234 .vsync_start = 768 + 2,
1235 .vsync_end = 768 + 2 + 5,
1236 .vtotal = 768 + 2 + 5 + 17,
1237 .vrefresh = 60,
1238};
1239
1240static const struct panel_desc samsung_ltn140at29_301 = {
1241 .modes = &samsung_ltn140at29_301_mode,
1242 .num_modes = 1,
1243 .bpc = 6,
1244 .size = {
1245 .width = 320,
1246 .height = 187,
1247 },
1248};
1249
9c6615bc
BB		 1250static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1251 .clock = 33300,
1252 .hdisplay = 800,
1253 .hsync_start = 800 + 1,
1254 .hsync_end = 800 + 1 + 64,
1255 .htotal = 800 + 1 + 64 + 64,
1256 .vdisplay = 480,
1257 .vsync_start = 480 + 1,
1258 .vsync_end = 480 + 1 + 23,
1259 .vtotal = 480 + 1 + 23 + 22,
1260 .vrefresh = 60,
1261};
1262
1263static const struct panel_desc shelly_sca07010_bfn_lnn = {
1264 .modes = &shelly_sca07010_bfn_lnn_mode,
1265 .num_modes = 1,
1266 .size = {
1267 .width = 152,
1268 .height = 91,
1269 },
1270 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1271};
1272
06a9dc65
MS		 1273static const struct display_timing urt_umsh_8596md_timing = {
1274 .pixelclock = { 33260000, 33260000, 33260000 },
1275 .hactive = { 800, 800, 800 },
1276 .hfront_porch = { 41, 41, 41 },
1277 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1278 .hsync_len = { 71, 128, 128 },
1279 .vactive = { 480, 480, 480 },
1280 .vfront_porch = { 10, 10, 10 },
1281 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1282 .vsync_len = { 2, 2, 2 },
1283 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1284 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1285};
1286
1287static const struct panel_desc urt_umsh_8596md_lvds = {
1288 .timings = &urt_umsh_8596md_timing,
1289 .num_timings = 1,
1290 .bpc = 6,
1291 .size = {
1292 .width = 152,
1293 .height = 91,
1294 },
1295 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1296};
1297
1298static const struct panel_desc urt_umsh_8596md_parallel = {
1299 .timings = &urt_umsh_8596md_timing,
1300 .num_timings = 1,
1301 .bpc = 6,
1302 .size = {
1303 .width = 152,
1304 .height = 91,
1305 },
1306 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1307};
1308
280921de
TR		 1309static const struct of_device_id platform_of_match[] = {
1310 {
1c550fa1
PZ		 1311 .compatible = "ampire,am800480r3tmqwa1h",
1312 .data = &ampire_am800480r3tmqwa1h,
1313 }, {
280921de
TR		 1314 .compatible = "auo,b101aw03",
1315 .data = &auo_b101aw03,
a531bc3d
HL		 1316 }, {
1317 .compatible = "auo,b101ean01",
1318 .data = &auo_b101ean01,
dac746e0
RC		 1319 }, {
1320 .compatible = "auo,b101xtn01",
1321 .data = &auo_b101xtn01,
e35e305e
AK		 1322 }, {
1323 .compatible = "auo,b116xw03",
1324 .data = &auo_b116xw03,
3e51d609
AK		 1325 }, {
1326 .compatible = "auo,b133htn01",
1327 .data = &auo_b133htn01,
a333f7ad
SM		 1328 }, {
1329 .compatible = "auo,b133xtn01",
1330 .data = &auo_b133xtn01,
d47df633
PZ		 1331 }, {
1332 .compatible = "avic,tm070ddh03",
1333 .data = &avic_tm070ddh03,
4c930757
SW		 1334 }, {
1335 .compatible = "chunghwa,claa101wa01a",
1336 .data = &chunghwa_claa101wa01a
280921de
TR		 1337 }, {
1338 .compatible = "chunghwa,claa101wb01",
1339 .data = &chunghwa_claa101wb01
26ab0065
SA		 1340 }, {
1341 .compatible = "edt,et057090dhu",
1342 .data = &edt_et057090dhu,
fff5de45
PZ		 1343 }, {
1344 .compatible = "edt,et070080dh6",
1345 .data = &edt_etm0700g0dh6,
1346 }, {
1347 .compatible = "edt,etm0700g0dh6",
1348 .data = &edt_etm0700g0dh6,
102932b0
BB		 1349 }, {
1350 .compatible = "foxlink,fl500wvr00-a0t",
1351 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1352 }, {
1353 .compatible = "giantplus,gpg482739qs5",
1354 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1355 }, {
1356 .compatible = "hannstar,hsd070pww1",
1357 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 1358 }, {
1359 .compatible = "hannstar,hsd100pxn1",
1360 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 1361 }, {
1362 .compatible = "hit,tx23d38vm0caa",
1363 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1364 }, {
1365 .compatible = "innolux,at043tn24",
1366 .data = &innolux_at043tn24,
d731f661
LS		 1367 }, {
1368 .compatible ="innolux,g121i1-l01",
1369 .data = &innolux_g121i1_l01
f8fa17ba
AB		 1370 }, {
1371 .compatible = "innolux,g121x1-l03",
1372 .data = &innolux_g121x1_l03,
0a2288c0
TR		 1373 }, {
1374 .compatible = "innolux,n116bge",
1375 .data = &innolux_n116bge,
ea44739d
AB		 1376 }, {
1377 .compatible = "innolux,n156bge-l21",
1378 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1379 }, {
1380 .compatible = "innolux,zj070na-01p",
1381 .data = &innolux_zj070na_01p,
8def22e5
LS		 1382 }, {
1383 .compatible = "kyo,tcg121xglp",
1384 .data = &kyo_tcg121xglp,
dd015002
HS		 1385 }, {
1386 .compatible = "lg,lb070wv8",
1387 .data = &lg_lb070wv8,
690d8fa7
JS		 1388 }, {
1389 .compatible = "lg,lp120up1",
1390 .data = &lg_lp120up1,
ec7c5653
TR		 1391 }, {
1392 .compatible = "lg,lp129qe",
1393 .data = &lg_lp129qe,
c6e87f91 1394 }, {
1395 .compatible = "nec,nl4827hc19-05b",
1396 .data = &nec_nl4827hc19_05b,
a99fb626
GB		 1397 }, {
1398 .compatible = "okaya,rs800480t-7x0gp",
1399 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 1400 }, {
1401 .compatible = "olimex,lcd-olinuxino-43-ts",
1402 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 1403 }, {
1404 .compatible = "ontat,yx700wv03",
1405 .data = &ontat_yx700wv03,
725c9d40
PZ		 1406 }, {
1407 .compatible = "ortustech,com43h4m85ulc",
1408 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 1409 }, {
1410 .compatible = "qiaodian,qd43003c0-40",
1411 .data = &qd43003c0_40,
6d54e3d2
MD		 1412 }, {
1413 .compatible = "samsung,ltn101nt05",
1414 .data = &samsung_ltn101nt05,
0c934306
SM		 1415 }, {
1416 .compatible = "samsung,ltn140at29-301",
1417 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 1418 }, {
1419 .compatible = "shelly,sca07010-bfn-lnn",
1420 .data = &shelly_sca07010_bfn_lnn,
06a9dc65
MS		 1421 }, {
1422 .compatible = "urt,umsh-8596md-t",
1423 .data = &urt_umsh_8596md_parallel,
1424 }, {
1425 .compatible = "urt,umsh-8596md-1t",
1426 .data = &urt_umsh_8596md_parallel,
1427 }, {
1428 .compatible = "urt,umsh-8596md-7t",
1429 .data = &urt_umsh_8596md_parallel,
1430 }, {
1431 .compatible = "urt,umsh-8596md-11t",
1432 .data = &urt_umsh_8596md_lvds,
1433 }, {
1434 .compatible = "urt,umsh-8596md-19t",
1435 .data = &urt_umsh_8596md_lvds,
1436 }, {
1437 .compatible = "urt,umsh-8596md-20t",
1438 .data = &urt_umsh_8596md_parallel,
280921de
TR		 1439 }, {
1440 /* sentinel */
1441 }
1442};
1443MODULE_DEVICE_TABLE(of, platform_of_match);
1444
1445static int panel_simple_platform_probe(struct platform_device *pdev)
1446{
1447 const struct of_device_id *id;
1448
1449 id = of_match_node(platform_of_match, pdev->dev.of_node);
1450 if (!id)
1451 return -ENODEV;
1452
1453 return panel_simple_probe(&pdev->dev, id->data);
1454}
1455
1456static int panel_simple_platform_remove(struct platform_device *pdev)
1457{
1458 return panel_simple_remove(&pdev->dev);
1459}
1460
d02fd93e
TR		 1461static void panel_simple_platform_shutdown(struct platform_device *pdev)
1462{
1463 panel_simple_shutdown(&pdev->dev);
1464}
1465
280921de
TR		 1466static struct platform_driver panel_simple_platform_driver = {
1467 .driver = {
1468 .name = "panel-simple",
280921de
TR		 1469 .of_match_table = platform_of_match,
1470 },
1471 .probe = panel_simple_platform_probe,
1472 .remove = panel_simple_platform_remove,
d02fd93e 1473 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1474};
1475
210fcd9d
TR		 1476struct panel_desc_dsi {
1477 struct panel_desc desc;
1478
462658b8 1479 unsigned long flags;
210fcd9d
TR		 1480 enum mipi_dsi_pixel_format format;
1481 unsigned int lanes;
1482};
1483
d718d79e
TR		 1484static const struct drm_display_mode auo_b080uan01_mode = {
1485 .clock = 154500,
1486 .hdisplay = 1200,
1487 .hsync_start = 1200 + 62,
1488 .hsync_end = 1200 + 62 + 4,
1489 .htotal = 1200 + 62 + 4 + 62,
1490 .vdisplay = 1920,
1491 .vsync_start = 1920 + 9,
1492 .vsync_end = 1920 + 9 + 2,
1493 .vtotal = 1920 + 9 + 2 + 8,
1494 .vrefresh = 60,
1495};
1496
1497static const struct panel_desc_dsi auo_b080uan01 = {
1498 .desc = {
1499 .modes = &auo_b080uan01_mode,
1500 .num_modes = 1,
1501 .bpc = 8,
1502 .size = {
1503 .width = 108,
1504 .height = 272,
1505 },
1506 },
1507 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1508 .format = MIPI_DSI_FMT_RGB888,
1509 .lanes = 4,
1510};
1511
c8521969
CZ		 1512static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1513 .clock = 160000,
1514 .hdisplay = 1200,
1515 .hsync_start = 1200 + 120,
1516 .hsync_end = 1200 + 120 + 20,
1517 .htotal = 1200 + 120 + 20 + 21,
1518 .vdisplay = 1920,
1519 .vsync_start = 1920 + 21,
1520 .vsync_end = 1920 + 21 + 3,
1521 .vtotal = 1920 + 21 + 3 + 18,
1522 .vrefresh = 60,
1523 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1524};
1525
1526static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1527 .desc = {
1528 .modes = &boe_tv080wum_nl0_mode,
1529 .num_modes = 1,
1530 .size = {
1531 .width = 107,
1532 .height = 172,
1533 },
1534 },
1535 .flags = MIPI_DSI_MODE_VIDEO |
1536 MIPI_DSI_MODE_VIDEO_BURST |
1537 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1538 .format = MIPI_DSI_FMT_RGB888,
1539 .lanes = 4,
1540};
1541
712ac1ba
AC		 1542static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1543 .clock = 71000,
1544 .hdisplay = 800,
1545 .hsync_start = 800 + 32,
1546 .hsync_end = 800 + 32 + 1,
1547 .htotal = 800 + 32 + 1 + 57,
1548 .vdisplay = 1280,
1549 .vsync_start = 1280 + 28,
1550 .vsync_end = 1280 + 28 + 1,
1551 .vtotal = 1280 + 28 + 1 + 14,
1552 .vrefresh = 60,
1553};
1554
1555static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1556 .desc = {
1557 .modes = &lg_ld070wx3_sl01_mode,
1558 .num_modes = 1,
d7a839cd 1559 .bpc = 8,
712ac1ba
AC		 1560 .size = {
1561 .width = 94,
1562 .height = 151,
1563 },
1564 },
5e4cc278 1565 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1566 .format = MIPI_DSI_FMT_RGB888,
1567 .lanes = 4,
1568};
1569
499ce85a
AC		 1570static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1571 .clock = 67000,
1572 .hdisplay = 720,
1573 .hsync_start = 720 + 12,
1574 .hsync_end = 720 + 12 + 4,
1575 .htotal = 720 + 12 + 4 + 112,
1576 .vdisplay = 1280,
1577 .vsync_start = 1280 + 8,
1578 .vsync_end = 1280 + 8 + 4,
1579 .vtotal = 1280 + 8 + 4 + 12,
1580 .vrefresh = 60,
1581};
1582
1583static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1584 .desc = {
1585 .modes = &lg_lh500wx1_sd03_mode,
1586 .num_modes = 1,
d7a839cd 1587 .bpc = 8,
499ce85a
AC		 1588 .size = {
1589 .width = 62,
1590 .height = 110,
1591 },
1592 },
1593 .flags = MIPI_DSI_MODE_VIDEO,
1594 .format = MIPI_DSI_FMT_RGB888,
1595 .lanes = 4,
1596};
1597
280921de
TR		 1598static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1599 .clock = 157200,
1600 .hdisplay = 1920,
1601 .hsync_start = 1920 + 154,
1602 .hsync_end = 1920 + 154 + 16,
1603 .htotal = 1920 + 154 + 16 + 32,
1604 .vdisplay = 1200,
1605 .vsync_start = 1200 + 17,
1606 .vsync_end = 1200 + 17 + 2,
1607 .vtotal = 1200 + 17 + 2 + 16,
1608 .vrefresh = 60,
1609};
1610
210fcd9d
TR		 1611static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1612 .desc = {
1613 .modes = &panasonic_vvx10f004b00_mode,
1614 .num_modes = 1,
d7a839cd 1615 .bpc = 8,
210fcd9d
TR		 1616 .size = {
1617 .width = 217,
1618 .height = 136,
1619 },
280921de 1620 },
5e4cc278
AC		 1621 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1622 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1623 .format = MIPI_DSI_FMT_RGB888,
1624 .lanes = 4,
1625};
1626
c8521969 1627
210fcd9d
TR		 1628static const struct of_device_id dsi_of_match[] = {
1629 {
d718d79e
TR		 1630 .compatible = "auo,b080uan01",
1631 .data = &auo_b080uan01
c8521969
CZ		 1632 }, {
1633 .compatible = "boe,tv080wum-nl0",
1634 .data = &boe_tv080wum_nl0
d718d79e 1635 }, {
712ac1ba
AC		 1636 .compatible = "lg,ld070wx3-sl01",
1637 .data = &lg_ld070wx3_sl01
1638 }, {
499ce85a
AC		 1639 .compatible = "lg,lh500wx1-sd03",
1640 .data = &lg_lh500wx1_sd03
1641 }, {
210fcd9d
TR		 1642 .compatible = "panasonic,vvx10f004b00",
1643 .data = &panasonic_vvx10f004b00
1644 }, {
1645 /* sentinel */
1646 }
1647};
1648MODULE_DEVICE_TABLE(of, dsi_of_match);
1649
1650static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1651{
1652 const struct panel_desc_dsi *desc;
1653 const struct of_device_id *id;
1654 int err;
1655
1656 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1657 if (!id)
1658 return -ENODEV;
1659
1660 desc = id->data;
1661
1662 err = panel_simple_probe(&dsi->dev, &desc->desc);
1663 if (err < 0)
1664 return err;
1665
462658b8 1666 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1667 dsi->format = desc->format;
1668 dsi->lanes = desc->lanes;
1669
1670 return mipi_dsi_attach(dsi);
1671}
1672
1673static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1674{
1675 int err;
1676
1677 err = mipi_dsi_detach(dsi);
1678 if (err < 0)
1679 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1680
1681 return panel_simple_remove(&dsi->dev);
1682}
1683
d02fd93e
TR		 1684static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1685{
1686 panel_simple_shutdown(&dsi->dev);
1687}
1688
210fcd9d
TR		 1689static struct mipi_dsi_driver panel_simple_dsi_driver = {
1690 .driver = {
1691 .name = "panel-simple-dsi",
210fcd9d
TR		 1692 .of_match_table = dsi_of_match,
1693 },
1694 .probe = panel_simple_dsi_probe,
1695 .remove = panel_simple_dsi_remove,
d02fd93e 1696 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1697};
1698
1699static int __init panel_simple_init(void)
1700{
210fcd9d
TR		 1701 int err;
1702
1703 err = platform_driver_register(&panel_simple_platform_driver);
1704 if (err < 0)
1705 return err;
1706
1707 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1708 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1709 if (err < 0)
1710 return err;
1711 }
1712
1713 return 0;
280921de
TR		 1714}
1715module_init(panel_simple_init);
1716
1717static void __exit panel_simple_exit(void)
1718{
210fcd9d
TR		 1719 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1720 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1721
280921de
TR		 1722 platform_driver_unregister(&panel_simple_platform_driver);
1723}
1724module_exit(panel_simple_exit);
1725
1726MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1727MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1728MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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