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dt-bindings: Add BOE TV080WUM-NL0 panel binding
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
280921de
TR		 47 struct {
48 unsigned int width;
49 unsigned int height;
50 } size;
f673c37e
AK		 51
52 /**
53 * @prepare: the time (in milliseconds) that it takes for the panel to
54 * become ready and start receiving video data
55 * @enable: the time (in milliseconds) that it takes for the panel to
56 * display the first valid frame after starting to receive
57 * video data
58 * @disable: the time (in milliseconds) that it takes for the panel to
59 * turn the display off (no content is visible)
60 * @unprepare: the time (in milliseconds) that it takes for the panel
61 * to power itself down completely
62 */
63 struct {
64 unsigned int prepare;
65 unsigned int enable;
66 unsigned int disable;
67 unsigned int unprepare;
68 } delay;
795f7ab3
BB		 69
70 u32 bus_format;
280921de
TR		 71};
72
280921de
TR		 73struct panel_simple {
74 struct drm_panel base;
613a633e 75 bool prepared;
280921de
TR		 76 bool enabled;
77
78 const struct panel_desc *desc;
79
80 struct backlight_device *backlight;
81 struct regulator *supply;
82 struct i2c_adapter *ddc;
83
cfdf0549 84 struct gpio_desc *enable_gpio;
280921de
TR		 85};
86
87static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
88{
89 return container_of(panel, struct panel_simple, base);
90}
91
92static int panel_simple_get_fixed_modes(struct panel_simple *panel)
93{
94 struct drm_connector *connector = panel->base.connector;
95 struct drm_device *drm = panel->base.drm;
96 struct drm_display_mode *mode;
97 unsigned int i, num = 0;
98
99 if (!panel->desc)
100 return 0;
101
a5d3e625
PZ		 102 for (i = 0; i < panel->desc->num_timings; i++) {
103 const struct display_timing *dt = &panel->desc->timings[i];
104 struct videomode vm;
105
106 videomode_from_timing(dt, &vm);
107 mode = drm_mode_create(drm);
108 if (!mode) {
109 dev_err(drm->dev, "failed to add mode %ux%u\n",
110 dt->hactive.typ, dt->vactive.typ);
111 continue;
112 }
113
114 drm_display_mode_from_videomode(&vm, mode);
115 drm_mode_set_name(mode);
116
117 drm_mode_probed_add(connector, mode);
118 num++;
119 }
120
280921de
TR		 121 for (i = 0; i < panel->desc->num_modes; i++) {
122 const struct drm_display_mode *m = &panel->desc->modes[i];
123
124 mode = drm_mode_duplicate(drm, m);
125 if (!mode) {
126 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
127 m->hdisplay, m->vdisplay, m->vrefresh);
128 continue;
129 }
130
131 drm_mode_set_name(mode);
132
133 drm_mode_probed_add(connector, mode);
134 num++;
135 }
136
0208d511 137 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 138 connector->display_info.width_mm = panel->desc->size.width;
139 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 140 if (panel->desc->bus_format)
141 drm_display_info_set_bus_formats(&connector->display_info,
142 &panel->desc->bus_format, 1);
280921de
TR		 143
144 return num;
145}
146
147static int panel_simple_disable(struct drm_panel *panel)
148{
149 struct panel_simple *p = to_panel_simple(panel);
150
151 if (!p->enabled)
152 return 0;
153
154 if (p->backlight) {
155 p->backlight->props.power = FB_BLANK_POWERDOWN;
156 backlight_update_status(p->backlight);
157 }
158
f673c37e
AK		 159 if (p->desc->delay.disable)
160 msleep(p->desc->delay.disable);
161
280921de
TR		 162 p->enabled = false;
163
164 return 0;
165}
166
c0e1d170
AK		 167static int panel_simple_unprepare(struct drm_panel *panel)
168{
613a633e
AK		 169 struct panel_simple *p = to_panel_simple(panel);
170
171 if (!p->prepared)
172 return 0;
173
174 if (p->enable_gpio)
175 gpiod_set_value_cansleep(p->enable_gpio, 0);
176
177 regulator_disable(p->supply);
178
f673c37e
AK		 179 if (p->desc->delay.unprepare)
180 msleep(p->desc->delay.unprepare);
181
613a633e 182 p->prepared = false;
c0e1d170 183
c0e1d170
AK		 184 return 0;
185}
186
613a633e 187static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 188{
189 struct panel_simple *p = to_panel_simple(panel);
190 int err;
191
613a633e 192 if (p->prepared)
280921de
TR		 193 return 0;
194
195 err = regulator_enable(p->supply);
196 if (err < 0) {
197 dev_err(panel->dev, "failed to enable supply: %d\n", err);
198 return err;
199 }
200
cfdf0549 201 if (p->enable_gpio)
15c1a919 202 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 203
f673c37e
AK		 204 if (p->desc->delay.prepare)
205 msleep(p->desc->delay.prepare);
206
613a633e
AK		 207 p->prepared = true;
208
209 return 0;
210}
211
212static int panel_simple_enable(struct drm_panel *panel)
213{
214 struct panel_simple *p = to_panel_simple(panel);
215
216 if (p->enabled)
217 return 0;
218
f673c37e
AK		 219 if (p->desc->delay.enable)
220 msleep(p->desc->delay.enable);
221
280921de
TR		 222 if (p->backlight) {
223 p->backlight->props.power = FB_BLANK_UNBLANK;
224 backlight_update_status(p->backlight);
225 }
226
227 p->enabled = true;
228
229 return 0;
230}
231
232static int panel_simple_get_modes(struct drm_panel *panel)
233{
234 struct panel_simple *p = to_panel_simple(panel);
235 int num = 0;
236
237 /* probe EDID if a DDC bus is available */
238 if (p->ddc) {
239 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 240 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 241 if (edid) {
242 num += drm_add_edid_modes(panel->connector, edid);
243 kfree(edid);
244 }
245 }
246
247 /* add hard-coded panel modes */
248 num += panel_simple_get_fixed_modes(p);
249
250 return num;
251}
252
a5d3e625
PZ		 253static int panel_simple_get_timings(struct drm_panel *panel,
254 unsigned int num_timings,
255 struct display_timing *timings)
256{
257 struct panel_simple *p = to_panel_simple(panel);
258 unsigned int i;
259
260 if (p->desc->num_timings < num_timings)
261 num_timings = p->desc->num_timings;
262
263 if (timings)
264 for (i = 0; i < num_timings; i++)
265 timings[i] = p->desc->timings[i];
266
267 return p->desc->num_timings;
268}
269
280921de
TR		 270static const struct drm_panel_funcs panel_simple_funcs = {
271 .disable = panel_simple_disable,
c0e1d170
AK		 272 .unprepare = panel_simple_unprepare,
273 .prepare = panel_simple_prepare,
280921de
TR		 274 .enable = panel_simple_enable,
275 .get_modes = panel_simple_get_modes,
a5d3e625 276 .get_timings = panel_simple_get_timings,
280921de
TR		 277};
278
279static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
280{
281 struct device_node *backlight, *ddc;
282 struct panel_simple *panel;
280921de
TR		 283 int err;
284
285 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
286 if (!panel)
287 return -ENOMEM;
288
289 panel->enabled = false;
613a633e 290 panel->prepared = false;
280921de
TR		 291 panel->desc = desc;
292
293 panel->supply = devm_regulator_get(dev, "power");
294 if (IS_ERR(panel->supply))
295 return PTR_ERR(panel->supply);
296
a61400d8
AC		 297 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
298 GPIOD_OUT_LOW);
cfdf0549
AC		 299 if (IS_ERR(panel->enable_gpio)) {
300 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 301 dev_err(dev, "failed to request GPIO: %d\n", err);
302 return err;
303 }
280921de 304
280921de
TR		 305 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
306 if (backlight) {
307 panel->backlight = of_find_backlight_by_node(backlight);
308 of_node_put(backlight);
309
cfdf0549
AC		 310 if (!panel->backlight)
311 return -EPROBE_DEFER;
280921de
TR		 312 }
313
314 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
315 if (ddc) {
316 panel->ddc = of_find_i2c_adapter_by_node(ddc);
317 of_node_put(ddc);
318
319 if (!panel->ddc) {
320 err = -EPROBE_DEFER;
321 goto free_backlight;
322 }
323 }
324
325 drm_panel_init(&panel->base);
326 panel->base.dev = dev;
327 panel->base.funcs = &panel_simple_funcs;
328
329 err = drm_panel_add(&panel->base);
330 if (err < 0)
331 goto free_ddc;
332
333 dev_set_drvdata(dev, panel);
334
335 return 0;
336
337free_ddc:
338 if (panel->ddc)
339 put_device(&panel->ddc->dev);
340free_backlight:
341 if (panel->backlight)
342 put_device(&panel->backlight->dev);
280921de
TR		 343
344 return err;
345}
346
347static int panel_simple_remove(struct device *dev)
348{
349 struct panel_simple *panel = dev_get_drvdata(dev);
350
351 drm_panel_detach(&panel->base);
352 drm_panel_remove(&panel->base);
353
354 panel_simple_disable(&panel->base);
355
356 if (panel->ddc)
357 put_device(&panel->ddc->dev);
358
359 if (panel->backlight)
360 put_device(&panel->backlight->dev);
361
280921de
TR		 362 return 0;
363}
364
d02fd93e
TR		 365static void panel_simple_shutdown(struct device *dev)
366{
367 struct panel_simple *panel = dev_get_drvdata(dev);
368
369 panel_simple_disable(&panel->base);
370}
371
1c550fa1
PZ		 372static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
373 .clock = 33333,
374 .hdisplay = 800,
375 .hsync_start = 800 + 0,
376 .hsync_end = 800 + 0 + 255,
377 .htotal = 800 + 0 + 255 + 0,
378 .vdisplay = 480,
379 .vsync_start = 480 + 2,
380 .vsync_end = 480 + 2 + 45,
381 .vtotal = 480 + 2 + 45 + 0,
382 .vrefresh = 60,
383 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
384};
385
386static const struct panel_desc ampire_am800480r3tmqwa1h = {
387 .modes = &ampire_am800480r3tmqwa1h_mode,
388 .num_modes = 1,
389 .bpc = 6,
390 .size = {
391 .width = 152,
392 .height = 91,
393 },
394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
395};
396
280921de
TR		 397static const struct drm_display_mode auo_b101aw03_mode = {
398 .clock = 51450,
399 .hdisplay = 1024,
400 .hsync_start = 1024 + 156,
401 .hsync_end = 1024 + 156 + 8,
402 .htotal = 1024 + 156 + 8 + 156,
403 .vdisplay = 600,
404 .vsync_start = 600 + 16,
405 .vsync_end = 600 + 16 + 6,
406 .vtotal = 600 + 16 + 6 + 16,
407 .vrefresh = 60,
408};
409
410static const struct panel_desc auo_b101aw03 = {
411 .modes = &auo_b101aw03_mode,
412 .num_modes = 1,
0208d511 413 .bpc = 6,
280921de
TR		 414 .size = {
415 .width = 223,
416 .height = 125,
417 },
418};
419
a531bc3d
HL		 420static const struct drm_display_mode auo_b101ean01_mode = {
421 .clock = 72500,
422 .hdisplay = 1280,
423 .hsync_start = 1280 + 119,
424 .hsync_end = 1280 + 119 + 32,
425 .htotal = 1280 + 119 + 32 + 21,
426 .vdisplay = 800,
427 .vsync_start = 800 + 4,
428 .vsync_end = 800 + 4 + 20,
429 .vtotal = 800 + 4 + 20 + 8,
430 .vrefresh = 60,
431};
432
433static const struct panel_desc auo_b101ean01 = {
434 .modes = &auo_b101ean01_mode,
435 .num_modes = 1,
436 .bpc = 6,
437 .size = {
438 .width = 217,
439 .height = 136,
440 },
441};
442
dac746e0
RC		 443static const struct drm_display_mode auo_b101xtn01_mode = {
444 .clock = 72000,
445 .hdisplay = 1366,
446 .hsync_start = 1366 + 20,
447 .hsync_end = 1366 + 20 + 70,
448 .htotal = 1366 + 20 + 70,
449 .vdisplay = 768,
450 .vsync_start = 768 + 14,
451 .vsync_end = 768 + 14 + 42,
452 .vtotal = 768 + 14 + 42,
453 .vrefresh = 60,
454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
455};
456
457static const struct panel_desc auo_b101xtn01 = {
458 .modes = &auo_b101xtn01_mode,
459 .num_modes = 1,
460 .bpc = 6,
461 .size = {
462 .width = 223,
463 .height = 125,
464 },
465};
466
e35e305e
AK		 467static const struct drm_display_mode auo_b116xw03_mode = {
468 .clock = 70589,
469 .hdisplay = 1366,
470 .hsync_start = 1366 + 40,
471 .hsync_end = 1366 + 40 + 40,
472 .htotal = 1366 + 40 + 40 + 32,
473 .vdisplay = 768,
474 .vsync_start = 768 + 10,
475 .vsync_end = 768 + 10 + 12,
476 .vtotal = 768 + 10 + 12 + 6,
477 .vrefresh = 60,
478};
479
480static const struct panel_desc auo_b116xw03 = {
481 .modes = &auo_b116xw03_mode,
482 .num_modes = 1,
483 .bpc = 6,
484 .size = {
485 .width = 256,
486 .height = 144,
487 },
488};
489
a333f7ad
SM		 490static const struct drm_display_mode auo_b133xtn01_mode = {
491 .clock = 69500,
492 .hdisplay = 1366,
493 .hsync_start = 1366 + 48,
494 .hsync_end = 1366 + 48 + 32,
495 .htotal = 1366 + 48 + 32 + 20,
496 .vdisplay = 768,
497 .vsync_start = 768 + 3,
498 .vsync_end = 768 + 3 + 6,
499 .vtotal = 768 + 3 + 6 + 13,
500 .vrefresh = 60,
501};
502
503static const struct panel_desc auo_b133xtn01 = {
504 .modes = &auo_b133xtn01_mode,
505 .num_modes = 1,
0208d511 506 .bpc = 6,
a333f7ad
SM		 507 .size = {
508 .width = 293,
509 .height = 165,
510 },
511};
512
3e51d609
AK		 513static const struct drm_display_mode auo_b133htn01_mode = {
514 .clock = 150660,
515 .hdisplay = 1920,
516 .hsync_start = 1920 + 172,
517 .hsync_end = 1920 + 172 + 80,
518 .htotal = 1920 + 172 + 80 + 60,
519 .vdisplay = 1080,
520 .vsync_start = 1080 + 25,
521 .vsync_end = 1080 + 25 + 10,
522 .vtotal = 1080 + 25 + 10 + 10,
523 .vrefresh = 60,
524};
525
526static const struct panel_desc auo_b133htn01 = {
527 .modes = &auo_b133htn01_mode,
528 .num_modes = 1,
d7a839cd 529 .bpc = 6,
3e51d609
AK		 530 .size = {
531 .width = 293,
532 .height = 165,
533 },
534 .delay = {
535 .prepare = 105,
536 .enable = 20,
537 .unprepare = 50,
538 },
539};
540
d47df633
PZ		 541static const struct drm_display_mode avic_tm070ddh03_mode = {
542 .clock = 51200,
543 .hdisplay = 1024,
544 .hsync_start = 1024 + 160,
545 .hsync_end = 1024 + 160 + 4,
546 .htotal = 1024 + 160 + 4 + 156,
547 .vdisplay = 600,
548 .vsync_start = 600 + 17,
549 .vsync_end = 600 + 17 + 1,
550 .vtotal = 600 + 17 + 1 + 17,
551 .vrefresh = 60,
552};
553
554static const struct panel_desc avic_tm070ddh03 = {
555 .modes = &avic_tm070ddh03_mode,
556 .num_modes = 1,
557 .bpc = 8,
558 .size = {
559 .width = 154,
560 .height = 90,
561 },
562 .delay = {
563 .prepare = 20,
564 .enable = 200,
565 .disable = 200,
566 },
567};
568
4c930757
SW		 569static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
570 .clock = 72070,
571 .hdisplay = 1366,
572 .hsync_start = 1366 + 58,
573 .hsync_end = 1366 + 58 + 58,
574 .htotal = 1366 + 58 + 58 + 58,
575 .vdisplay = 768,
576 .vsync_start = 768 + 4,
577 .vsync_end = 768 + 4 + 4,
578 .vtotal = 768 + 4 + 4 + 4,
579 .vrefresh = 60,
580};
581
582static const struct panel_desc chunghwa_claa101wa01a = {
583 .modes = &chunghwa_claa101wa01a_mode,
584 .num_modes = 1,
0208d511 585 .bpc = 6,
4c930757
SW		 586 .size = {
587 .width = 220,
588 .height = 120,
589 },
590};
591
280921de
TR		 592static const struct drm_display_mode chunghwa_claa101wb01_mode = {
593 .clock = 69300,
594 .hdisplay = 1366,
595 .hsync_start = 1366 + 48,
596 .hsync_end = 1366 + 48 + 32,
597 .htotal = 1366 + 48 + 32 + 20,
598 .vdisplay = 768,
599 .vsync_start = 768 + 16,
600 .vsync_end = 768 + 16 + 8,
601 .vtotal = 768 + 16 + 8 + 16,
602 .vrefresh = 60,
603};
604
605static const struct panel_desc chunghwa_claa101wb01 = {
606 .modes = &chunghwa_claa101wb01_mode,
607 .num_modes = 1,
0208d511 608 .bpc = 6,
280921de
TR		 609 .size = {
610 .width = 223,
611 .height = 125,
612 },
613};
614
26ab0065
SA		 615static const struct drm_display_mode edt_et057090dhu_mode = {
616 .clock = 25175,
617 .hdisplay = 640,
618 .hsync_start = 640 + 16,
619 .hsync_end = 640 + 16 + 30,
620 .htotal = 640 + 16 + 30 + 114,
621 .vdisplay = 480,
622 .vsync_start = 480 + 10,
623 .vsync_end = 480 + 10 + 3,
624 .vtotal = 480 + 10 + 3 + 32,
625 .vrefresh = 60,
626 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
627};
628
629static const struct panel_desc edt_et057090dhu = {
630 .modes = &edt_et057090dhu_mode,
631 .num_modes = 1,
0208d511 632 .bpc = 6,
26ab0065
SA		 633 .size = {
634 .width = 115,
635 .height = 86,
636 },
637};
638
fff5de45
PZ		 639static const struct drm_display_mode edt_etm0700g0dh6_mode = {
640 .clock = 33260,
641 .hdisplay = 800,
642 .hsync_start = 800 + 40,
643 .hsync_end = 800 + 40 + 128,
644 .htotal = 800 + 40 + 128 + 88,
645 .vdisplay = 480,
646 .vsync_start = 480 + 10,
647 .vsync_end = 480 + 10 + 2,
648 .vtotal = 480 + 10 + 2 + 33,
649 .vrefresh = 60,
650 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
651};
652
653static const struct panel_desc edt_etm0700g0dh6 = {
654 .modes = &edt_etm0700g0dh6_mode,
655 .num_modes = 1,
0208d511 656 .bpc = 6,
fff5de45
PZ		 657 .size = {
658 .width = 152,
659 .height = 91,
660 },
661};
662
102932b0
BB		 663static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
664 .clock = 32260,
665 .hdisplay = 800,
666 .hsync_start = 800 + 168,
667 .hsync_end = 800 + 168 + 64,
668 .htotal = 800 + 168 + 64 + 88,
669 .vdisplay = 480,
670 .vsync_start = 480 + 37,
671 .vsync_end = 480 + 37 + 2,
672 .vtotal = 480 + 37 + 2 + 8,
673 .vrefresh = 60,
674};
675
676static const struct panel_desc foxlink_fl500wvr00_a0t = {
677 .modes = &foxlink_fl500wvr00_a0t_mode,
678 .num_modes = 1,
d7a839cd 679 .bpc = 8,
102932b0
BB		 680 .size = {
681 .width = 108,
682 .height = 65,
683 },
bb276cb3 684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 685};
686
d435a2af
PZ		 687static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
688 .clock = 9000,
689 .hdisplay = 480,
690 .hsync_start = 480 + 5,
691 .hsync_end = 480 + 5 + 1,
692 .htotal = 480 + 5 + 1 + 40,
693 .vdisplay = 272,
694 .vsync_start = 272 + 8,
695 .vsync_end = 272 + 8 + 1,
696 .vtotal = 272 + 8 + 1 + 8,
697 .vrefresh = 60,
698};
699
700static const struct panel_desc giantplus_gpg482739qs5 = {
701 .modes = &giantplus_gpg482739qs5_mode,
702 .num_modes = 1,
703 .bpc = 8,
704 .size = {
705 .width = 95,
706 .height = 54,
707 },
33536a09 708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 709};
710
ab07725a
PZ		 711static const struct display_timing hannstar_hsd070pww1_timing = {
712 .pixelclock = { 64300000, 71100000, 82000000 },
713 .hactive = { 1280, 1280, 1280 },
714 .hfront_porch = { 1, 1, 10 },
715 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 716 /*
717 * According to the data sheet, the minimum horizontal blanking interval
718 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
719 * minimum working horizontal blanking interval to be 60 clocks.
720 */
721 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 722 .vactive = { 800, 800, 800 },
723 .vfront_porch = { 1, 1, 10 },
724 .vback_porch = { 1, 1, 10 },
725 .vsync_len = { 1, 21, 203 },
726 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 727};
728
729static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 730 .timings = &hannstar_hsd070pww1_timing,
731 .num_timings = 1,
a853205e
PZ		 732 .bpc = 6,
733 .size = {
734 .width = 151,
735 .height = 94,
736 },
58d6a7bc 737 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 738};
739
c0d607e5
EN		 740static const struct display_timing hannstar_hsd100pxn1_timing = {
741 .pixelclock = { 55000000, 65000000, 75000000 },
742 .hactive = { 1024, 1024, 1024 },
743 .hfront_porch = { 40, 40, 40 },
744 .hback_porch = { 220, 220, 220 },
745 .hsync_len = { 20, 60, 100 },
746 .vactive = { 768, 768, 768 },
747 .vfront_porch = { 7, 7, 7 },
748 .vback_porch = { 21, 21, 21 },
749 .vsync_len = { 10, 10, 10 },
750 .flags = DISPLAY_FLAGS_DE_HIGH,
751};
752
753static const struct panel_desc hannstar_hsd100pxn1 = {
754 .timings = &hannstar_hsd100pxn1_timing,
755 .num_timings = 1,
756 .bpc = 6,
757 .size = {
758 .width = 203,
759 .height = 152,
760 },
4946b043 761 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 762};
763
61ac0bf8
LS		 764static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
765 .clock = 33333,
766 .hdisplay = 800,
767 .hsync_start = 800 + 85,
768 .hsync_end = 800 + 85 + 86,
769 .htotal = 800 + 85 + 86 + 85,
770 .vdisplay = 480,
771 .vsync_start = 480 + 16,
772 .vsync_end = 480 + 16 + 13,
773 .vtotal = 480 + 16 + 13 + 16,
774 .vrefresh = 60,
775};
776
777static const struct panel_desc hitachi_tx23d38vm0caa = {
778 .modes = &hitachi_tx23d38vm0caa_mode,
779 .num_modes = 1,
780 .bpc = 6,
781 .size = {
782 .width = 195,
783 .height = 117,
784 },
785};
786
41bcceb4
NF		 787static const struct drm_display_mode innolux_at043tn24_mode = {
788 .clock = 9000,
789 .hdisplay = 480,
790 .hsync_start = 480 + 2,
791 .hsync_end = 480 + 2 + 41,
792 .htotal = 480 + 2 + 41 + 2,
793 .vdisplay = 272,
794 .vsync_start = 272 + 2,
795 .vsync_end = 272 + 2 + 11,
796 .vtotal = 272 + 2 + 11 + 2,
797 .vrefresh = 60,
798 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
799};
800
801static const struct panel_desc innolux_at043tn24 = {
802 .modes = &innolux_at043tn24_mode,
803 .num_modes = 1,
804 .bpc = 8,
805 .size = {
806 .width = 95,
807 .height = 54,
808 },
809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
810};
811
d731f661 812static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 813 .clock = 71000,
d731f661
LS		 814 .hdisplay = 1280,
815 .hsync_start = 1280 + 64,
816 .hsync_end = 1280 + 64 + 32,
817 .htotal = 1280 + 64 + 32 + 64,
818 .vdisplay = 800,
819 .vsync_start = 800 + 9,
820 .vsync_end = 800 + 9 + 6,
821 .vtotal = 800 + 9 + 6 + 9,
822 .vrefresh = 60,
823};
824
825static const struct panel_desc innolux_g121i1_l01 = {
826 .modes = &innolux_g121i1_l01_mode,
827 .num_modes = 1,
828 .bpc = 6,
829 .size = {
830 .width = 261,
831 .height = 163,
832 },
833};
834
0a2288c0 835static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 836 .clock = 76420,
0a2288c0 837 .hdisplay = 1366,
7fe8c777
DK		 838 .hsync_start = 1366 + 136,
839 .hsync_end = 1366 + 136 + 30,
840 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 841 .vdisplay = 768,
842 .vsync_start = 768 + 8,
7fe8c777
DK		 843 .vsync_end = 768 + 8 + 12,
844 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 845 .vrefresh = 60,
846 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
847};
848
849static const struct panel_desc innolux_n116bge = {
850 .modes = &innolux_n116bge_mode,
851 .num_modes = 1,
852 .bpc = 6,
853 .size = {
854 .width = 256,
855 .height = 144,
856 },
857};
858
ea44739d
AB		 859static const struct drm_display_mode innolux_n156bge_l21_mode = {
860 .clock = 69300,
861 .hdisplay = 1366,
862 .hsync_start = 1366 + 16,
863 .hsync_end = 1366 + 16 + 34,
864 .htotal = 1366 + 16 + 34 + 50,
865 .vdisplay = 768,
866 .vsync_start = 768 + 2,
867 .vsync_end = 768 + 2 + 6,
868 .vtotal = 768 + 2 + 6 + 12,
869 .vrefresh = 60,
870};
871
872static const struct panel_desc innolux_n156bge_l21 = {
873 .modes = &innolux_n156bge_l21_mode,
874 .num_modes = 1,
0208d511 875 .bpc = 6,
ea44739d
AB		 876 .size = {
877 .width = 344,
878 .height = 193,
879 },
880};
881
bccac3f1
MG		 882static const struct drm_display_mode innolux_zj070na_01p_mode = {
883 .clock = 51501,
884 .hdisplay = 1024,
885 .hsync_start = 1024 + 128,
886 .hsync_end = 1024 + 128 + 64,
887 .htotal = 1024 + 128 + 64 + 128,
888 .vdisplay = 600,
889 .vsync_start = 600 + 16,
890 .vsync_end = 600 + 16 + 4,
891 .vtotal = 600 + 16 + 4 + 16,
892 .vrefresh = 60,
893};
894
895static const struct panel_desc innolux_zj070na_01p = {
896 .modes = &innolux_zj070na_01p_mode,
897 .num_modes = 1,
898 .bpc = 6,
899 .size = {
900 .width = 1024,
901 .height = 600,
902 },
903};
904
dd015002
HS		 905static const struct drm_display_mode lg_lb070wv8_mode = {
906 .clock = 33246,
907 .hdisplay = 800,
908 .hsync_start = 800 + 88,
909 .hsync_end = 800 + 88 + 80,
910 .htotal = 800 + 88 + 80 + 88,
911 .vdisplay = 480,
912 .vsync_start = 480 + 10,
913 .vsync_end = 480 + 10 + 25,
914 .vtotal = 480 + 10 + 25 + 10,
915 .vrefresh = 60,
916};
917
918static const struct panel_desc lg_lb070wv8 = {
919 .modes = &lg_lb070wv8_mode,
920 .num_modes = 1,
921 .bpc = 16,
922 .size = {
923 .width = 151,
924 .height = 91,
925 },
926 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
927};
928
ec7c5653
TR		 929static const struct drm_display_mode lg_lp129qe_mode = {
930 .clock = 285250,
931 .hdisplay = 2560,
932 .hsync_start = 2560 + 48,
933 .hsync_end = 2560 + 48 + 32,
934 .htotal = 2560 + 48 + 32 + 80,
935 .vdisplay = 1700,
936 .vsync_start = 1700 + 3,
937 .vsync_end = 1700 + 3 + 10,
938 .vtotal = 1700 + 3 + 10 + 36,
939 .vrefresh = 60,
940};
941
942static const struct panel_desc lg_lp129qe = {
943 .modes = &lg_lp129qe_mode,
944 .num_modes = 1,
0208d511 945 .bpc = 8,
ec7c5653
TR		 946 .size = {
947 .width = 272,
948 .height = 181,
949 },
950};
951
c6e87f91 952static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
953 .clock = 10870,
954 .hdisplay = 480,
955 .hsync_start = 480 + 2,
956 .hsync_end = 480 + 2 + 41,
957 .htotal = 480 + 2 + 41 + 2,
958 .vdisplay = 272,
959 .vsync_start = 272 + 2,
960 .vsync_end = 272 + 2 + 4,
961 .vtotal = 272 + 2 + 4 + 2,
962 .vrefresh = 74,
963};
964
965static const struct panel_desc nec_nl4827hc19_05b = {
966 .modes = &nec_nl4827hc19_05b_mode,
967 .num_modes = 1,
968 .bpc = 8,
969 .size = {
970 .width = 95,
971 .height = 54,
972 },
973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
974};
975
a99fb626
GB		 976static const struct display_timing okaya_rs800480t_7x0gp_timing = {
977 .pixelclock = { 30000000, 30000000, 40000000 },
978 .hactive = { 800, 800, 800 },
979 .hfront_porch = { 40, 40, 40 },
980 .hback_porch = { 40, 40, 40 },
981 .hsync_len = { 1, 48, 48 },
982 .vactive = { 480, 480, 480 },
983 .vfront_porch = { 13, 13, 13 },
984 .vback_porch = { 29, 29, 29 },
985 .vsync_len = { 3, 3, 3 },
986 .flags = DISPLAY_FLAGS_DE_HIGH,
987};
988
989static const struct panel_desc okaya_rs800480t_7x0gp = {
990 .timings = &okaya_rs800480t_7x0gp_timing,
991 .num_timings = 1,
992 .bpc = 6,
993 .size = {
994 .width = 154,
995 .height = 87,
996 },
997 .delay = {
998 .prepare = 41,
999 .enable = 50,
1000 .unprepare = 41,
1001 .disable = 50,
1002 },
1003 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1004};
1005
725c9d40
PZ		 1006static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1007 .clock = 25000,
1008 .hdisplay = 480,
1009 .hsync_start = 480 + 10,
1010 .hsync_end = 480 + 10 + 10,
1011 .htotal = 480 + 10 + 10 + 15,
1012 .vdisplay = 800,
1013 .vsync_start = 800 + 3,
1014 .vsync_end = 800 + 3 + 3,
1015 .vtotal = 800 + 3 + 3 + 3,
1016 .vrefresh = 60,
1017};
1018
1019static const struct panel_desc ortustech_com43h4m85ulc = {
1020 .modes = &ortustech_com43h4m85ulc_mode,
1021 .num_modes = 1,
1022 .bpc = 8,
1023 .size = {
1024 .width = 56,
1025 .height = 93,
1026 },
1027 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1028};
1029
6d54e3d2
MD		 1030static const struct drm_display_mode samsung_ltn101nt05_mode = {
1031 .clock = 54030,
1032 .hdisplay = 1024,
1033 .hsync_start = 1024 + 24,
1034 .hsync_end = 1024 + 24 + 136,
1035 .htotal = 1024 + 24 + 136 + 160,
1036 .vdisplay = 600,
1037 .vsync_start = 600 + 3,
1038 .vsync_end = 600 + 3 + 6,
1039 .vtotal = 600 + 3 + 6 + 61,
1040 .vrefresh = 60,
1041};
1042
1043static const struct panel_desc samsung_ltn101nt05 = {
1044 .modes = &samsung_ltn101nt05_mode,
1045 .num_modes = 1,
0208d511 1046 .bpc = 6,
6d54e3d2
MD		 1047 .size = {
1048 .width = 1024,
1049 .height = 600,
1050 },
1051};
1052
0c934306
SM		 1053static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1054 .clock = 76300,
1055 .hdisplay = 1366,
1056 .hsync_start = 1366 + 64,
1057 .hsync_end = 1366 + 64 + 48,
1058 .htotal = 1366 + 64 + 48 + 128,
1059 .vdisplay = 768,
1060 .vsync_start = 768 + 2,
1061 .vsync_end = 768 + 2 + 5,
1062 .vtotal = 768 + 2 + 5 + 17,
1063 .vrefresh = 60,
1064};
1065
1066static const struct panel_desc samsung_ltn140at29_301 = {
1067 .modes = &samsung_ltn140at29_301_mode,
1068 .num_modes = 1,
1069 .bpc = 6,
1070 .size = {
1071 .width = 320,
1072 .height = 187,
1073 },
1074};
1075
9c6615bc
BB		 1076static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1077 .clock = 33300,
1078 .hdisplay = 800,
1079 .hsync_start = 800 + 1,
1080 .hsync_end = 800 + 1 + 64,
1081 .htotal = 800 + 1 + 64 + 64,
1082 .vdisplay = 480,
1083 .vsync_start = 480 + 1,
1084 .vsync_end = 480 + 1 + 23,
1085 .vtotal = 480 + 1 + 23 + 22,
1086 .vrefresh = 60,
1087};
1088
1089static const struct panel_desc shelly_sca07010_bfn_lnn = {
1090 .modes = &shelly_sca07010_bfn_lnn_mode,
1091 .num_modes = 1,
1092 .size = {
1093 .width = 152,
1094 .height = 91,
1095 },
1096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1097};
1098
280921de
TR		 1099static const struct of_device_id platform_of_match[] = {
1100 {
1c550fa1
PZ		 1101 .compatible = "ampire,am800480r3tmqwa1h",
1102 .data = &ampire_am800480r3tmqwa1h,
1103 }, {
280921de
TR		 1104 .compatible = "auo,b101aw03",
1105 .data = &auo_b101aw03,
a531bc3d
HL		 1106 }, {
1107 .compatible = "auo,b101ean01",
1108 .data = &auo_b101ean01,
dac746e0
RC		 1109 }, {
1110 .compatible = "auo,b101xtn01",
1111 .data = &auo_b101xtn01,
e35e305e
AK		 1112 }, {
1113 .compatible = "auo,b116xw03",
1114 .data = &auo_b116xw03,
3e51d609
AK		 1115 }, {
1116 .compatible = "auo,b133htn01",
1117 .data = &auo_b133htn01,
a333f7ad
SM		 1118 }, {
1119 .compatible = "auo,b133xtn01",
1120 .data = &auo_b133xtn01,
d47df633
PZ		 1121 }, {
1122 .compatible = "avic,tm070ddh03",
1123 .data = &avic_tm070ddh03,
4c930757
SW		 1124 }, {
1125 .compatible = "chunghwa,claa101wa01a",
1126 .data = &chunghwa_claa101wa01a
280921de
TR		 1127 }, {
1128 .compatible = "chunghwa,claa101wb01",
1129 .data = &chunghwa_claa101wb01
26ab0065
SA		 1130 }, {
1131 .compatible = "edt,et057090dhu",
1132 .data = &edt_et057090dhu,
fff5de45
PZ		 1133 }, {
1134 .compatible = "edt,et070080dh6",
1135 .data = &edt_etm0700g0dh6,
1136 }, {
1137 .compatible = "edt,etm0700g0dh6",
1138 .data = &edt_etm0700g0dh6,
102932b0
BB		 1139 }, {
1140 .compatible = "foxlink,fl500wvr00-a0t",
1141 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1142 }, {
1143 .compatible = "giantplus,gpg482739qs5",
1144 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1145 }, {
1146 .compatible = "hannstar,hsd070pww1",
1147 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 1148 }, {
1149 .compatible = "hannstar,hsd100pxn1",
1150 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 1151 }, {
1152 .compatible = "hit,tx23d38vm0caa",
1153 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1154 }, {
1155 .compatible = "innolux,at043tn24",
1156 .data = &innolux_at043tn24,
d731f661
LS		 1157 }, {
1158 .compatible ="innolux,g121i1-l01",
1159 .data = &innolux_g121i1_l01
0a2288c0
TR		 1160 }, {
1161 .compatible = "innolux,n116bge",
1162 .data = &innolux_n116bge,
ea44739d
AB		 1163 }, {
1164 .compatible = "innolux,n156bge-l21",
1165 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1166 }, {
1167 .compatible = "innolux,zj070na-01p",
1168 .data = &innolux_zj070na_01p,
dd015002
HS		 1169 }, {
1170 .compatible = "lg,lb070wv8",
1171 .data = &lg_lb070wv8,
ec7c5653
TR		 1172 }, {
1173 .compatible = "lg,lp129qe",
1174 .data = &lg_lp129qe,
c6e87f91 1175 }, {
1176 .compatible = "nec,nl4827hc19-05b",
1177 .data = &nec_nl4827hc19_05b,
a99fb626
GB		 1178 }, {
1179 .compatible = "okaya,rs800480t-7x0gp",
1180 .data = &okaya_rs800480t_7x0gp,
725c9d40
PZ		 1181 }, {
1182 .compatible = "ortustech,com43h4m85ulc",
1183 .data = &ortustech_com43h4m85ulc,
6d54e3d2
MD		 1184 }, {
1185 .compatible = "samsung,ltn101nt05",
1186 .data = &samsung_ltn101nt05,
0c934306
SM		 1187 }, {
1188 .compatible = "samsung,ltn140at29-301",
1189 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 1190 }, {
1191 .compatible = "shelly,sca07010-bfn-lnn",
1192 .data = &shelly_sca07010_bfn_lnn,
280921de
TR		 1193 }, {
1194 /* sentinel */
1195 }
1196};
1197MODULE_DEVICE_TABLE(of, platform_of_match);
1198
1199static int panel_simple_platform_probe(struct platform_device *pdev)
1200{
1201 const struct of_device_id *id;
1202
1203 id = of_match_node(platform_of_match, pdev->dev.of_node);
1204 if (!id)
1205 return -ENODEV;
1206
1207 return panel_simple_probe(&pdev->dev, id->data);
1208}
1209
1210static int panel_simple_platform_remove(struct platform_device *pdev)
1211{
1212 return panel_simple_remove(&pdev->dev);
1213}
1214
d02fd93e
TR		 1215static void panel_simple_platform_shutdown(struct platform_device *pdev)
1216{
1217 panel_simple_shutdown(&pdev->dev);
1218}
1219
280921de
TR		 1220static struct platform_driver panel_simple_platform_driver = {
1221 .driver = {
1222 .name = "panel-simple",
280921de
TR		 1223 .of_match_table = platform_of_match,
1224 },
1225 .probe = panel_simple_platform_probe,
1226 .remove = panel_simple_platform_remove,
d02fd93e 1227 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1228};
1229
210fcd9d
TR		 1230struct panel_desc_dsi {
1231 struct panel_desc desc;
1232
462658b8 1233 unsigned long flags;
210fcd9d
TR		 1234 enum mipi_dsi_pixel_format format;
1235 unsigned int lanes;
1236};
1237
d718d79e
TR		 1238static const struct drm_display_mode auo_b080uan01_mode = {
1239 .clock = 154500,
1240 .hdisplay = 1200,
1241 .hsync_start = 1200 + 62,
1242 .hsync_end = 1200 + 62 + 4,
1243 .htotal = 1200 + 62 + 4 + 62,
1244 .vdisplay = 1920,
1245 .vsync_start = 1920 + 9,
1246 .vsync_end = 1920 + 9 + 2,
1247 .vtotal = 1920 + 9 + 2 + 8,
1248 .vrefresh = 60,
1249};
1250
1251static const struct panel_desc_dsi auo_b080uan01 = {
1252 .desc = {
1253 .modes = &auo_b080uan01_mode,
1254 .num_modes = 1,
1255 .bpc = 8,
1256 .size = {
1257 .width = 108,
1258 .height = 272,
1259 },
1260 },
1261 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1262 .format = MIPI_DSI_FMT_RGB888,
1263 .lanes = 4,
1264};
1265
712ac1ba
AC		 1266static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1267 .clock = 71000,
1268 .hdisplay = 800,
1269 .hsync_start = 800 + 32,
1270 .hsync_end = 800 + 32 + 1,
1271 .htotal = 800 + 32 + 1 + 57,
1272 .vdisplay = 1280,
1273 .vsync_start = 1280 + 28,
1274 .vsync_end = 1280 + 28 + 1,
1275 .vtotal = 1280 + 28 + 1 + 14,
1276 .vrefresh = 60,
1277};
1278
1279static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1280 .desc = {
1281 .modes = &lg_ld070wx3_sl01_mode,
1282 .num_modes = 1,
d7a839cd 1283 .bpc = 8,
712ac1ba
AC		 1284 .size = {
1285 .width = 94,
1286 .height = 151,
1287 },
1288 },
5e4cc278 1289 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1290 .format = MIPI_DSI_FMT_RGB888,
1291 .lanes = 4,
1292};
1293
499ce85a
AC		 1294static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1295 .clock = 67000,
1296 .hdisplay = 720,
1297 .hsync_start = 720 + 12,
1298 .hsync_end = 720 + 12 + 4,
1299 .htotal = 720 + 12 + 4 + 112,
1300 .vdisplay = 1280,
1301 .vsync_start = 1280 + 8,
1302 .vsync_end = 1280 + 8 + 4,
1303 .vtotal = 1280 + 8 + 4 + 12,
1304 .vrefresh = 60,
1305};
1306
1307static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1308 .desc = {
1309 .modes = &lg_lh500wx1_sd03_mode,
1310 .num_modes = 1,
d7a839cd 1311 .bpc = 8,
499ce85a
AC		 1312 .size = {
1313 .width = 62,
1314 .height = 110,
1315 },
1316 },
1317 .flags = MIPI_DSI_MODE_VIDEO,
1318 .format = MIPI_DSI_FMT_RGB888,
1319 .lanes = 4,
1320};
1321
280921de
TR		 1322static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1323 .clock = 157200,
1324 .hdisplay = 1920,
1325 .hsync_start = 1920 + 154,
1326 .hsync_end = 1920 + 154 + 16,
1327 .htotal = 1920 + 154 + 16 + 32,
1328 .vdisplay = 1200,
1329 .vsync_start = 1200 + 17,
1330 .vsync_end = 1200 + 17 + 2,
1331 .vtotal = 1200 + 17 + 2 + 16,
1332 .vrefresh = 60,
1333};
1334
210fcd9d
TR		 1335static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1336 .desc = {
1337 .modes = &panasonic_vvx10f004b00_mode,
1338 .num_modes = 1,
d7a839cd 1339 .bpc = 8,
210fcd9d
TR		 1340 .size = {
1341 .width = 217,
1342 .height = 136,
1343 },
280921de 1344 },
5e4cc278
AC		 1345 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1346 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1347 .format = MIPI_DSI_FMT_RGB888,
1348 .lanes = 4,
1349};
1350
1351static const struct of_device_id dsi_of_match[] = {
1352 {
d718d79e
TR		 1353 .compatible = "auo,b080uan01",
1354 .data = &auo_b080uan01
1355 }, {
712ac1ba
AC		 1356 .compatible = "lg,ld070wx3-sl01",
1357 .data = &lg_ld070wx3_sl01
1358 }, {
499ce85a
AC		 1359 .compatible = "lg,lh500wx1-sd03",
1360 .data = &lg_lh500wx1_sd03
1361 }, {
210fcd9d
TR		 1362 .compatible = "panasonic,vvx10f004b00",
1363 .data = &panasonic_vvx10f004b00
1364 }, {
1365 /* sentinel */
1366 }
1367};
1368MODULE_DEVICE_TABLE(of, dsi_of_match);
1369
1370static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1371{
1372 const struct panel_desc_dsi *desc;
1373 const struct of_device_id *id;
1374 int err;
1375
1376 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1377 if (!id)
1378 return -ENODEV;
1379
1380 desc = id->data;
1381
1382 err = panel_simple_probe(&dsi->dev, &desc->desc);
1383 if (err < 0)
1384 return err;
1385
462658b8 1386 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1387 dsi->format = desc->format;
1388 dsi->lanes = desc->lanes;
1389
1390 return mipi_dsi_attach(dsi);
1391}
1392
1393static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1394{
1395 int err;
1396
1397 err = mipi_dsi_detach(dsi);
1398 if (err < 0)
1399 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1400
1401 return panel_simple_remove(&dsi->dev);
1402}
1403
d02fd93e
TR		 1404static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1405{
1406 panel_simple_shutdown(&dsi->dev);
1407}
1408
210fcd9d
TR		 1409static struct mipi_dsi_driver panel_simple_dsi_driver = {
1410 .driver = {
1411 .name = "panel-simple-dsi",
210fcd9d
TR		 1412 .of_match_table = dsi_of_match,
1413 },
1414 .probe = panel_simple_dsi_probe,
1415 .remove = panel_simple_dsi_remove,
d02fd93e 1416 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1417};
1418
1419static int __init panel_simple_init(void)
1420{
210fcd9d
TR		 1421 int err;
1422
1423 err = platform_driver_register(&panel_simple_platform_driver);
1424 if (err < 0)
1425 return err;
1426
1427 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1428 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1429 if (err < 0)
1430 return err;
1431 }
1432
1433 return 0;
280921de
TR		 1434}
1435module_init(panel_simple_init);
1436
1437static void __exit panel_simple_exit(void)
1438{
210fcd9d
TR		 1439 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1440 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1441
280921de
TR		 1442 platform_driver_unregister(&panel_simple_platform_driver);
1443}
1444module_exit(panel_simple_exit);
1445
1446MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1447MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1448MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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