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drm/panel: simple: Add support for Kyocera TCG121XGLP panel
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
280921de
TR		 47 struct {
48 unsigned int width;
49 unsigned int height;
50 } size;
f673c37e
AK		 51
52 /**
53 * @prepare: the time (in milliseconds) that it takes for the panel to
54 * become ready and start receiving video data
55 * @enable: the time (in milliseconds) that it takes for the panel to
56 * display the first valid frame after starting to receive
57 * video data
58 * @disable: the time (in milliseconds) that it takes for the panel to
59 * turn the display off (no content is visible)
60 * @unprepare: the time (in milliseconds) that it takes for the panel
61 * to power itself down completely
62 */
63 struct {
64 unsigned int prepare;
65 unsigned int enable;
66 unsigned int disable;
67 unsigned int unprepare;
68 } delay;
795f7ab3
BB		 69
70 u32 bus_format;
280921de
TR		 71};
72
280921de
TR		 73struct panel_simple {
74 struct drm_panel base;
613a633e 75 bool prepared;
280921de
TR		 76 bool enabled;
77
78 const struct panel_desc *desc;
79
80 struct backlight_device *backlight;
81 struct regulator *supply;
82 struct i2c_adapter *ddc;
83
cfdf0549 84 struct gpio_desc *enable_gpio;
280921de
TR		 85};
86
87static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
88{
89 return container_of(panel, struct panel_simple, base);
90}
91
92static int panel_simple_get_fixed_modes(struct panel_simple *panel)
93{
94 struct drm_connector *connector = panel->base.connector;
95 struct drm_device *drm = panel->base.drm;
96 struct drm_display_mode *mode;
97 unsigned int i, num = 0;
98
99 if (!panel->desc)
100 return 0;
101
a5d3e625
PZ		 102 for (i = 0; i < panel->desc->num_timings; i++) {
103 const struct display_timing *dt = &panel->desc->timings[i];
104 struct videomode vm;
105
106 videomode_from_timing(dt, &vm);
107 mode = drm_mode_create(drm);
108 if (!mode) {
109 dev_err(drm->dev, "failed to add mode %ux%u\n",
110 dt->hactive.typ, dt->vactive.typ);
111 continue;
112 }
113
114 drm_display_mode_from_videomode(&vm, mode);
115 drm_mode_set_name(mode);
116
117 drm_mode_probed_add(connector, mode);
118 num++;
119 }
120
280921de
TR		 121 for (i = 0; i < panel->desc->num_modes; i++) {
122 const struct drm_display_mode *m = &panel->desc->modes[i];
123
124 mode = drm_mode_duplicate(drm, m);
125 if (!mode) {
126 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
127 m->hdisplay, m->vdisplay, m->vrefresh);
128 continue;
129 }
130
131 drm_mode_set_name(mode);
132
133 drm_mode_probed_add(connector, mode);
134 num++;
135 }
136
0208d511 137 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 138 connector->display_info.width_mm = panel->desc->size.width;
139 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 140 if (panel->desc->bus_format)
141 drm_display_info_set_bus_formats(&connector->display_info,
142 &panel->desc->bus_format, 1);
280921de
TR		 143
144 return num;
145}
146
147static int panel_simple_disable(struct drm_panel *panel)
148{
149 struct panel_simple *p = to_panel_simple(panel);
150
151 if (!p->enabled)
152 return 0;
153
154 if (p->backlight) {
155 p->backlight->props.power = FB_BLANK_POWERDOWN;
156 backlight_update_status(p->backlight);
157 }
158
f673c37e
AK		 159 if (p->desc->delay.disable)
160 msleep(p->desc->delay.disable);
161
280921de
TR		 162 p->enabled = false;
163
164 return 0;
165}
166
c0e1d170
AK		 167static int panel_simple_unprepare(struct drm_panel *panel)
168{
613a633e
AK		 169 struct panel_simple *p = to_panel_simple(panel);
170
171 if (!p->prepared)
172 return 0;
173
174 if (p->enable_gpio)
175 gpiod_set_value_cansleep(p->enable_gpio, 0);
176
177 regulator_disable(p->supply);
178
f673c37e
AK		 179 if (p->desc->delay.unprepare)
180 msleep(p->desc->delay.unprepare);
181
613a633e 182 p->prepared = false;
c0e1d170 183
c0e1d170
AK		 184 return 0;
185}
186
613a633e 187static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 188{
189 struct panel_simple *p = to_panel_simple(panel);
190 int err;
191
613a633e 192 if (p->prepared)
280921de
TR		 193 return 0;
194
195 err = regulator_enable(p->supply);
196 if (err < 0) {
197 dev_err(panel->dev, "failed to enable supply: %d\n", err);
198 return err;
199 }
200
cfdf0549 201 if (p->enable_gpio)
15c1a919 202 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 203
f673c37e
AK		 204 if (p->desc->delay.prepare)
205 msleep(p->desc->delay.prepare);
206
613a633e
AK		 207 p->prepared = true;
208
209 return 0;
210}
211
212static int panel_simple_enable(struct drm_panel *panel)
213{
214 struct panel_simple *p = to_panel_simple(panel);
215
216 if (p->enabled)
217 return 0;
218
f673c37e
AK		 219 if (p->desc->delay.enable)
220 msleep(p->desc->delay.enable);
221
280921de
TR		 222 if (p->backlight) {
223 p->backlight->props.power = FB_BLANK_UNBLANK;
224 backlight_update_status(p->backlight);
225 }
226
227 p->enabled = true;
228
229 return 0;
230}
231
232static int panel_simple_get_modes(struct drm_panel *panel)
233{
234 struct panel_simple *p = to_panel_simple(panel);
235 int num = 0;
236
237 /* probe EDID if a DDC bus is available */
238 if (p->ddc) {
239 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 240 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 241 if (edid) {
242 num += drm_add_edid_modes(panel->connector, edid);
243 kfree(edid);
244 }
245 }
246
247 /* add hard-coded panel modes */
248 num += panel_simple_get_fixed_modes(p);
249
250 return num;
251}
252
a5d3e625
PZ		 253static int panel_simple_get_timings(struct drm_panel *panel,
254 unsigned int num_timings,
255 struct display_timing *timings)
256{
257 struct panel_simple *p = to_panel_simple(panel);
258 unsigned int i;
259
260 if (p->desc->num_timings < num_timings)
261 num_timings = p->desc->num_timings;
262
263 if (timings)
264 for (i = 0; i < num_timings; i++)
265 timings[i] = p->desc->timings[i];
266
267 return p->desc->num_timings;
268}
269
280921de
TR		 270static const struct drm_panel_funcs panel_simple_funcs = {
271 .disable = panel_simple_disable,
c0e1d170
AK		 272 .unprepare = panel_simple_unprepare,
273 .prepare = panel_simple_prepare,
280921de
TR		 274 .enable = panel_simple_enable,
275 .get_modes = panel_simple_get_modes,
a5d3e625 276 .get_timings = panel_simple_get_timings,
280921de
TR		 277};
278
279static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
280{
281 struct device_node *backlight, *ddc;
282 struct panel_simple *panel;
280921de
TR		 283 int err;
284
285 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
286 if (!panel)
287 return -ENOMEM;
288
289 panel->enabled = false;
613a633e 290 panel->prepared = false;
280921de
TR		 291 panel->desc = desc;
292
293 panel->supply = devm_regulator_get(dev, "power");
294 if (IS_ERR(panel->supply))
295 return PTR_ERR(panel->supply);
296
a61400d8
AC		 297 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
298 GPIOD_OUT_LOW);
cfdf0549
AC		 299 if (IS_ERR(panel->enable_gpio)) {
300 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 301 dev_err(dev, "failed to request GPIO: %d\n", err);
302 return err;
303 }
280921de 304
280921de
TR		 305 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
306 if (backlight) {
307 panel->backlight = of_find_backlight_by_node(backlight);
308 of_node_put(backlight);
309
cfdf0549
AC		 310 if (!panel->backlight)
311 return -EPROBE_DEFER;
280921de
TR		 312 }
313
314 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
315 if (ddc) {
316 panel->ddc = of_find_i2c_adapter_by_node(ddc);
317 of_node_put(ddc);
318
319 if (!panel->ddc) {
320 err = -EPROBE_DEFER;
321 goto free_backlight;
322 }
323 }
324
325 drm_panel_init(&panel->base);
326 panel->base.dev = dev;
327 panel->base.funcs = &panel_simple_funcs;
328
329 err = drm_panel_add(&panel->base);
330 if (err < 0)
331 goto free_ddc;
332
333 dev_set_drvdata(dev, panel);
334
335 return 0;
336
337free_ddc:
338 if (panel->ddc)
339 put_device(&panel->ddc->dev);
340free_backlight:
341 if (panel->backlight)
342 put_device(&panel->backlight->dev);
280921de
TR		 343
344 return err;
345}
346
347static int panel_simple_remove(struct device *dev)
348{
349 struct panel_simple *panel = dev_get_drvdata(dev);
350
351 drm_panel_detach(&panel->base);
352 drm_panel_remove(&panel->base);
353
354 panel_simple_disable(&panel->base);
355
356 if (panel->ddc)
357 put_device(&panel->ddc->dev);
358
359 if (panel->backlight)
360 put_device(&panel->backlight->dev);
361
280921de
TR		 362 return 0;
363}
364
d02fd93e
TR		 365static void panel_simple_shutdown(struct device *dev)
366{
367 struct panel_simple *panel = dev_get_drvdata(dev);
368
369 panel_simple_disable(&panel->base);
370}
371
1c550fa1
PZ		 372static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
373 .clock = 33333,
374 .hdisplay = 800,
375 .hsync_start = 800 + 0,
376 .hsync_end = 800 + 0 + 255,
377 .htotal = 800 + 0 + 255 + 0,
378 .vdisplay = 480,
379 .vsync_start = 480 + 2,
380 .vsync_end = 480 + 2 + 45,
381 .vtotal = 480 + 2 + 45 + 0,
382 .vrefresh = 60,
383 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
384};
385
386static const struct panel_desc ampire_am800480r3tmqwa1h = {
387 .modes = &ampire_am800480r3tmqwa1h_mode,
388 .num_modes = 1,
389 .bpc = 6,
390 .size = {
391 .width = 152,
392 .height = 91,
393 },
394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
395};
396
280921de
TR		 397static const struct drm_display_mode auo_b101aw03_mode = {
398 .clock = 51450,
399 .hdisplay = 1024,
400 .hsync_start = 1024 + 156,
401 .hsync_end = 1024 + 156 + 8,
402 .htotal = 1024 + 156 + 8 + 156,
403 .vdisplay = 600,
404 .vsync_start = 600 + 16,
405 .vsync_end = 600 + 16 + 6,
406 .vtotal = 600 + 16 + 6 + 16,
407 .vrefresh = 60,
408};
409
410static const struct panel_desc auo_b101aw03 = {
411 .modes = &auo_b101aw03_mode,
412 .num_modes = 1,
0208d511 413 .bpc = 6,
280921de
TR		 414 .size = {
415 .width = 223,
416 .height = 125,
417 },
418};
419
a531bc3d
HL		 420static const struct drm_display_mode auo_b101ean01_mode = {
421 .clock = 72500,
422 .hdisplay = 1280,
423 .hsync_start = 1280 + 119,
424 .hsync_end = 1280 + 119 + 32,
425 .htotal = 1280 + 119 + 32 + 21,
426 .vdisplay = 800,
427 .vsync_start = 800 + 4,
428 .vsync_end = 800 + 4 + 20,
429 .vtotal = 800 + 4 + 20 + 8,
430 .vrefresh = 60,
431};
432
433static const struct panel_desc auo_b101ean01 = {
434 .modes = &auo_b101ean01_mode,
435 .num_modes = 1,
436 .bpc = 6,
437 .size = {
438 .width = 217,
439 .height = 136,
440 },
441};
442
dac746e0
RC		 443static const struct drm_display_mode auo_b101xtn01_mode = {
444 .clock = 72000,
445 .hdisplay = 1366,
446 .hsync_start = 1366 + 20,
447 .hsync_end = 1366 + 20 + 70,
448 .htotal = 1366 + 20 + 70,
449 .vdisplay = 768,
450 .vsync_start = 768 + 14,
451 .vsync_end = 768 + 14 + 42,
452 .vtotal = 768 + 14 + 42,
453 .vrefresh = 60,
454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
455};
456
457static const struct panel_desc auo_b101xtn01 = {
458 .modes = &auo_b101xtn01_mode,
459 .num_modes = 1,
460 .bpc = 6,
461 .size = {
462 .width = 223,
463 .height = 125,
464 },
465};
466
e35e305e
AK		 467static const struct drm_display_mode auo_b116xw03_mode = {
468 .clock = 70589,
469 .hdisplay = 1366,
470 .hsync_start = 1366 + 40,
471 .hsync_end = 1366 + 40 + 40,
472 .htotal = 1366 + 40 + 40 + 32,
473 .vdisplay = 768,
474 .vsync_start = 768 + 10,
475 .vsync_end = 768 + 10 + 12,
476 .vtotal = 768 + 10 + 12 + 6,
477 .vrefresh = 60,
478};
479
480static const struct panel_desc auo_b116xw03 = {
481 .modes = &auo_b116xw03_mode,
482 .num_modes = 1,
483 .bpc = 6,
484 .size = {
485 .width = 256,
486 .height = 144,
487 },
488};
489
a333f7ad
SM		 490static const struct drm_display_mode auo_b133xtn01_mode = {
491 .clock = 69500,
492 .hdisplay = 1366,
493 .hsync_start = 1366 + 48,
494 .hsync_end = 1366 + 48 + 32,
495 .htotal = 1366 + 48 + 32 + 20,
496 .vdisplay = 768,
497 .vsync_start = 768 + 3,
498 .vsync_end = 768 + 3 + 6,
499 .vtotal = 768 + 3 + 6 + 13,
500 .vrefresh = 60,
501};
502
503static const struct panel_desc auo_b133xtn01 = {
504 .modes = &auo_b133xtn01_mode,
505 .num_modes = 1,
0208d511 506 .bpc = 6,
a333f7ad
SM		 507 .size = {
508 .width = 293,
509 .height = 165,
510 },
511};
512
3e51d609
AK		 513static const struct drm_display_mode auo_b133htn01_mode = {
514 .clock = 150660,
515 .hdisplay = 1920,
516 .hsync_start = 1920 + 172,
517 .hsync_end = 1920 + 172 + 80,
518 .htotal = 1920 + 172 + 80 + 60,
519 .vdisplay = 1080,
520 .vsync_start = 1080 + 25,
521 .vsync_end = 1080 + 25 + 10,
522 .vtotal = 1080 + 25 + 10 + 10,
523 .vrefresh = 60,
524};
525
526static const struct panel_desc auo_b133htn01 = {
527 .modes = &auo_b133htn01_mode,
528 .num_modes = 1,
d7a839cd 529 .bpc = 6,
3e51d609
AK		 530 .size = {
531 .width = 293,
532 .height = 165,
533 },
534 .delay = {
535 .prepare = 105,
536 .enable = 20,
537 .unprepare = 50,
538 },
539};
540
d47df633
PZ		 541static const struct drm_display_mode avic_tm070ddh03_mode = {
542 .clock = 51200,
543 .hdisplay = 1024,
544 .hsync_start = 1024 + 160,
545 .hsync_end = 1024 + 160 + 4,
546 .htotal = 1024 + 160 + 4 + 156,
547 .vdisplay = 600,
548 .vsync_start = 600 + 17,
549 .vsync_end = 600 + 17 + 1,
550 .vtotal = 600 + 17 + 1 + 17,
551 .vrefresh = 60,
552};
553
554static const struct panel_desc avic_tm070ddh03 = {
555 .modes = &avic_tm070ddh03_mode,
556 .num_modes = 1,
557 .bpc = 8,
558 .size = {
559 .width = 154,
560 .height = 90,
561 },
562 .delay = {
563 .prepare = 20,
564 .enable = 200,
565 .disable = 200,
566 },
567};
568
4c930757
SW		 569static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
570 .clock = 72070,
571 .hdisplay = 1366,
572 .hsync_start = 1366 + 58,
573 .hsync_end = 1366 + 58 + 58,
574 .htotal = 1366 + 58 + 58 + 58,
575 .vdisplay = 768,
576 .vsync_start = 768 + 4,
577 .vsync_end = 768 + 4 + 4,
578 .vtotal = 768 + 4 + 4 + 4,
579 .vrefresh = 60,
580};
581
582static const struct panel_desc chunghwa_claa101wa01a = {
583 .modes = &chunghwa_claa101wa01a_mode,
584 .num_modes = 1,
0208d511 585 .bpc = 6,
4c930757
SW		 586 .size = {
587 .width = 220,
588 .height = 120,
589 },
590};
591
280921de
TR		 592static const struct drm_display_mode chunghwa_claa101wb01_mode = {
593 .clock = 69300,
594 .hdisplay = 1366,
595 .hsync_start = 1366 + 48,
596 .hsync_end = 1366 + 48 + 32,
597 .htotal = 1366 + 48 + 32 + 20,
598 .vdisplay = 768,
599 .vsync_start = 768 + 16,
600 .vsync_end = 768 + 16 + 8,
601 .vtotal = 768 + 16 + 8 + 16,
602 .vrefresh = 60,
603};
604
605static const struct panel_desc chunghwa_claa101wb01 = {
606 .modes = &chunghwa_claa101wb01_mode,
607 .num_modes = 1,
0208d511 608 .bpc = 6,
280921de
TR		 609 .size = {
610 .width = 223,
611 .height = 125,
612 },
613};
614
26ab0065
SA		 615static const struct drm_display_mode edt_et057090dhu_mode = {
616 .clock = 25175,
617 .hdisplay = 640,
618 .hsync_start = 640 + 16,
619 .hsync_end = 640 + 16 + 30,
620 .htotal = 640 + 16 + 30 + 114,
621 .vdisplay = 480,
622 .vsync_start = 480 + 10,
623 .vsync_end = 480 + 10 + 3,
624 .vtotal = 480 + 10 + 3 + 32,
625 .vrefresh = 60,
626 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
627};
628
629static const struct panel_desc edt_et057090dhu = {
630 .modes = &edt_et057090dhu_mode,
631 .num_modes = 1,
0208d511 632 .bpc = 6,
26ab0065
SA		 633 .size = {
634 .width = 115,
635 .height = 86,
636 },
637};
638
fff5de45
PZ		 639static const struct drm_display_mode edt_etm0700g0dh6_mode = {
640 .clock = 33260,
641 .hdisplay = 800,
642 .hsync_start = 800 + 40,
643 .hsync_end = 800 + 40 + 128,
644 .htotal = 800 + 40 + 128 + 88,
645 .vdisplay = 480,
646 .vsync_start = 480 + 10,
647 .vsync_end = 480 + 10 + 2,
648 .vtotal = 480 + 10 + 2 + 33,
649 .vrefresh = 60,
650 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
651};
652
653static const struct panel_desc edt_etm0700g0dh6 = {
654 .modes = &edt_etm0700g0dh6_mode,
655 .num_modes = 1,
0208d511 656 .bpc = 6,
fff5de45
PZ		 657 .size = {
658 .width = 152,
659 .height = 91,
660 },
661};
662
102932b0
BB		 663static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
664 .clock = 32260,
665 .hdisplay = 800,
666 .hsync_start = 800 + 168,
667 .hsync_end = 800 + 168 + 64,
668 .htotal = 800 + 168 + 64 + 88,
669 .vdisplay = 480,
670 .vsync_start = 480 + 37,
671 .vsync_end = 480 + 37 + 2,
672 .vtotal = 480 + 37 + 2 + 8,
673 .vrefresh = 60,
674};
675
676static const struct panel_desc foxlink_fl500wvr00_a0t = {
677 .modes = &foxlink_fl500wvr00_a0t_mode,
678 .num_modes = 1,
d7a839cd 679 .bpc = 8,
102932b0
BB		 680 .size = {
681 .width = 108,
682 .height = 65,
683 },
bb276cb3 684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 685};
686
d435a2af
PZ		 687static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
688 .clock = 9000,
689 .hdisplay = 480,
690 .hsync_start = 480 + 5,
691 .hsync_end = 480 + 5 + 1,
692 .htotal = 480 + 5 + 1 + 40,
693 .vdisplay = 272,
694 .vsync_start = 272 + 8,
695 .vsync_end = 272 + 8 + 1,
696 .vtotal = 272 + 8 + 1 + 8,
697 .vrefresh = 60,
698};
699
700static const struct panel_desc giantplus_gpg482739qs5 = {
701 .modes = &giantplus_gpg482739qs5_mode,
702 .num_modes = 1,
703 .bpc = 8,
704 .size = {
705 .width = 95,
706 .height = 54,
707 },
33536a09 708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 709};
710
ab07725a
PZ		 711static const struct display_timing hannstar_hsd070pww1_timing = {
712 .pixelclock = { 64300000, 71100000, 82000000 },
713 .hactive = { 1280, 1280, 1280 },
714 .hfront_porch = { 1, 1, 10 },
715 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 716 /*
717 * According to the data sheet, the minimum horizontal blanking interval
718 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
719 * minimum working horizontal blanking interval to be 60 clocks.
720 */
721 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 722 .vactive = { 800, 800, 800 },
723 .vfront_porch = { 1, 1, 10 },
724 .vback_porch = { 1, 1, 10 },
725 .vsync_len = { 1, 21, 203 },
726 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 727};
728
729static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 730 .timings = &hannstar_hsd070pww1_timing,
731 .num_timings = 1,
a853205e
PZ		 732 .bpc = 6,
733 .size = {
734 .width = 151,
735 .height = 94,
736 },
58d6a7bc 737 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 738};
739
c0d607e5
EN		 740static const struct display_timing hannstar_hsd100pxn1_timing = {
741 .pixelclock = { 55000000, 65000000, 75000000 },
742 .hactive = { 1024, 1024, 1024 },
743 .hfront_porch = { 40, 40, 40 },
744 .hback_porch = { 220, 220, 220 },
745 .hsync_len = { 20, 60, 100 },
746 .vactive = { 768, 768, 768 },
747 .vfront_porch = { 7, 7, 7 },
748 .vback_porch = { 21, 21, 21 },
749 .vsync_len = { 10, 10, 10 },
750 .flags = DISPLAY_FLAGS_DE_HIGH,
751};
752
753static const struct panel_desc hannstar_hsd100pxn1 = {
754 .timings = &hannstar_hsd100pxn1_timing,
755 .num_timings = 1,
756 .bpc = 6,
757 .size = {
758 .width = 203,
759 .height = 152,
760 },
4946b043 761 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 762};
763
61ac0bf8
LS		 764static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
765 .clock = 33333,
766 .hdisplay = 800,
767 .hsync_start = 800 + 85,
768 .hsync_end = 800 + 85 + 86,
769 .htotal = 800 + 85 + 86 + 85,
770 .vdisplay = 480,
771 .vsync_start = 480 + 16,
772 .vsync_end = 480 + 16 + 13,
773 .vtotal = 480 + 16 + 13 + 16,
774 .vrefresh = 60,
775};
776
777static const struct panel_desc hitachi_tx23d38vm0caa = {
778 .modes = &hitachi_tx23d38vm0caa_mode,
779 .num_modes = 1,
780 .bpc = 6,
781 .size = {
782 .width = 195,
783 .height = 117,
784 },
785};
786
41bcceb4
NF		 787static const struct drm_display_mode innolux_at043tn24_mode = {
788 .clock = 9000,
789 .hdisplay = 480,
790 .hsync_start = 480 + 2,
791 .hsync_end = 480 + 2 + 41,
792 .htotal = 480 + 2 + 41 + 2,
793 .vdisplay = 272,
794 .vsync_start = 272 + 2,
795 .vsync_end = 272 + 2 + 11,
796 .vtotal = 272 + 2 + 11 + 2,
797 .vrefresh = 60,
798 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
799};
800
801static const struct panel_desc innolux_at043tn24 = {
802 .modes = &innolux_at043tn24_mode,
803 .num_modes = 1,
804 .bpc = 8,
805 .size = {
806 .width = 95,
807 .height = 54,
808 },
809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
810};
811
d731f661 812static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 813 .clock = 71000,
d731f661
LS		 814 .hdisplay = 1280,
815 .hsync_start = 1280 + 64,
816 .hsync_end = 1280 + 64 + 32,
817 .htotal = 1280 + 64 + 32 + 64,
818 .vdisplay = 800,
819 .vsync_start = 800 + 9,
820 .vsync_end = 800 + 9 + 6,
821 .vtotal = 800 + 9 + 6 + 9,
822 .vrefresh = 60,
823};
824
825static const struct panel_desc innolux_g121i1_l01 = {
826 .modes = &innolux_g121i1_l01_mode,
827 .num_modes = 1,
828 .bpc = 6,
829 .size = {
830 .width = 261,
831 .height = 163,
832 },
833};
834
f8fa17ba
AB		 835static const struct drm_display_mode innolux_g121x1_l03_mode = {
836 .clock = 65000,
837 .hdisplay = 1024,
838 .hsync_start = 1024 + 0,
839 .hsync_end = 1024 + 1,
840 .htotal = 1024 + 0 + 1 + 320,
841 .vdisplay = 768,
842 .vsync_start = 768 + 38,
843 .vsync_end = 768 + 38 + 1,
844 .vtotal = 768 + 38 + 1 + 0,
845 .vrefresh = 60,
846};
847
848static const struct panel_desc innolux_g121x1_l03 = {
849 .modes = &innolux_g121x1_l03_mode,
850 .num_modes = 1,
851 .bpc = 6,
852 .size = {
853 .width = 246,
854 .height = 185,
855 },
856 .delay = {
857 .enable = 200,
858 .unprepare = 200,
859 .disable = 400,
860 },
861};
862
0a2288c0 863static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 864 .clock = 76420,
0a2288c0 865 .hdisplay = 1366,
7fe8c777
DK		 866 .hsync_start = 1366 + 136,
867 .hsync_end = 1366 + 136 + 30,
868 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 869 .vdisplay = 768,
870 .vsync_start = 768 + 8,
7fe8c777
DK		 871 .vsync_end = 768 + 8 + 12,
872 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 873 .vrefresh = 60,
874 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
875};
876
877static const struct panel_desc innolux_n116bge = {
878 .modes = &innolux_n116bge_mode,
879 .num_modes = 1,
880 .bpc = 6,
881 .size = {
882 .width = 256,
883 .height = 144,
884 },
885};
886
ea44739d
AB		 887static const struct drm_display_mode innolux_n156bge_l21_mode = {
888 .clock = 69300,
889 .hdisplay = 1366,
890 .hsync_start = 1366 + 16,
891 .hsync_end = 1366 + 16 + 34,
892 .htotal = 1366 + 16 + 34 + 50,
893 .vdisplay = 768,
894 .vsync_start = 768 + 2,
895 .vsync_end = 768 + 2 + 6,
896 .vtotal = 768 + 2 + 6 + 12,
897 .vrefresh = 60,
898};
899
900static const struct panel_desc innolux_n156bge_l21 = {
901 .modes = &innolux_n156bge_l21_mode,
902 .num_modes = 1,
0208d511 903 .bpc = 6,
ea44739d
AB		 904 .size = {
905 .width = 344,
906 .height = 193,
907 },
908};
909
bccac3f1
MG		 910static const struct drm_display_mode innolux_zj070na_01p_mode = {
911 .clock = 51501,
912 .hdisplay = 1024,
913 .hsync_start = 1024 + 128,
914 .hsync_end = 1024 + 128 + 64,
915 .htotal = 1024 + 128 + 64 + 128,
916 .vdisplay = 600,
917 .vsync_start = 600 + 16,
918 .vsync_end = 600 + 16 + 4,
919 .vtotal = 600 + 16 + 4 + 16,
920 .vrefresh = 60,
921};
922
923static const struct panel_desc innolux_zj070na_01p = {
924 .modes = &innolux_zj070na_01p_mode,
925 .num_modes = 1,
926 .bpc = 6,
927 .size = {
928 .width = 1024,
929 .height = 600,
930 },
931};
932
8def22e5
LS		 933static const struct display_timing kyo_tcg121xglp_timing = {
934 .pixelclock = { 52000000, 65000000, 71000000 },
935 .hactive = { 1024, 1024, 1024 },
936 .hfront_porch = { 2, 2, 2 },
937 .hback_porch = { 2, 2, 2 },
938 .hsync_len = { 86, 124, 244 },
939 .vactive = { 768, 768, 768 },
940 .vfront_porch = { 2, 2, 2 },
941 .vback_porch = { 2, 2, 2 },
942 .vsync_len = { 6, 34, 73 },
943 .flags = DISPLAY_FLAGS_DE_HIGH,
944};
945
946static const struct panel_desc kyo_tcg121xglp = {
947 .timings = &kyo_tcg121xglp_timing,
948 .num_timings = 1,
949 .bpc = 8,
950 .size = {
951 .width = 246,
952 .height = 184,
953 },
954 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
955};
956
dd015002
HS		 957static const struct drm_display_mode lg_lb070wv8_mode = {
958 .clock = 33246,
959 .hdisplay = 800,
960 .hsync_start = 800 + 88,
961 .hsync_end = 800 + 88 + 80,
962 .htotal = 800 + 88 + 80 + 88,
963 .vdisplay = 480,
964 .vsync_start = 480 + 10,
965 .vsync_end = 480 + 10 + 25,
966 .vtotal = 480 + 10 + 25 + 10,
967 .vrefresh = 60,
968};
969
970static const struct panel_desc lg_lb070wv8 = {
971 .modes = &lg_lb070wv8_mode,
972 .num_modes = 1,
973 .bpc = 16,
974 .size = {
975 .width = 151,
976 .height = 91,
977 },
978 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
979};
980
ec7c5653
TR		 981static const struct drm_display_mode lg_lp129qe_mode = {
982 .clock = 285250,
983 .hdisplay = 2560,
984 .hsync_start = 2560 + 48,
985 .hsync_end = 2560 + 48 + 32,
986 .htotal = 2560 + 48 + 32 + 80,
987 .vdisplay = 1700,
988 .vsync_start = 1700 + 3,
989 .vsync_end = 1700 + 3 + 10,
990 .vtotal = 1700 + 3 + 10 + 36,
991 .vrefresh = 60,
992};
993
994static const struct panel_desc lg_lp129qe = {
995 .modes = &lg_lp129qe_mode,
996 .num_modes = 1,
0208d511 997 .bpc = 8,
ec7c5653
TR		 998 .size = {
999 .width = 272,
1000 .height = 181,
1001 },
1002};
1003
c6e87f91 1004static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1005 .clock = 10870,
1006 .hdisplay = 480,
1007 .hsync_start = 480 + 2,
1008 .hsync_end = 480 + 2 + 41,
1009 .htotal = 480 + 2 + 41 + 2,
1010 .vdisplay = 272,
1011 .vsync_start = 272 + 2,
1012 .vsync_end = 272 + 2 + 4,
1013 .vtotal = 272 + 2 + 4 + 2,
1014 .vrefresh = 74,
1015};
1016
1017static const struct panel_desc nec_nl4827hc19_05b = {
1018 .modes = &nec_nl4827hc19_05b_mode,
1019 .num_modes = 1,
1020 .bpc = 8,
1021 .size = {
1022 .width = 95,
1023 .height = 54,
1024 },
1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1026};
1027
a99fb626
GB		 1028static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1029 .pixelclock = { 30000000, 30000000, 40000000 },
1030 .hactive = { 800, 800, 800 },
1031 .hfront_porch = { 40, 40, 40 },
1032 .hback_porch = { 40, 40, 40 },
1033 .hsync_len = { 1, 48, 48 },
1034 .vactive = { 480, 480, 480 },
1035 .vfront_porch = { 13, 13, 13 },
1036 .vback_porch = { 29, 29, 29 },
1037 .vsync_len = { 3, 3, 3 },
1038 .flags = DISPLAY_FLAGS_DE_HIGH,
1039};
1040
1041static const struct panel_desc okaya_rs800480t_7x0gp = {
1042 .timings = &okaya_rs800480t_7x0gp_timing,
1043 .num_timings = 1,
1044 .bpc = 6,
1045 .size = {
1046 .width = 154,
1047 .height = 87,
1048 },
1049 .delay = {
1050 .prepare = 41,
1051 .enable = 50,
1052 .unprepare = 41,
1053 .disable = 50,
1054 },
1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1056};
1057
725c9d40
PZ		 1058static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1059 .clock = 25000,
1060 .hdisplay = 480,
1061 .hsync_start = 480 + 10,
1062 .hsync_end = 480 + 10 + 10,
1063 .htotal = 480 + 10 + 10 + 15,
1064 .vdisplay = 800,
1065 .vsync_start = 800 + 3,
1066 .vsync_end = 800 + 3 + 3,
1067 .vtotal = 800 + 3 + 3 + 3,
1068 .vrefresh = 60,
1069};
1070
1071static const struct panel_desc ortustech_com43h4m85ulc = {
1072 .modes = &ortustech_com43h4m85ulc_mode,
1073 .num_modes = 1,
1074 .bpc = 8,
1075 .size = {
1076 .width = 56,
1077 .height = 93,
1078 },
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1080};
1081
6d54e3d2
MD		 1082static const struct drm_display_mode samsung_ltn101nt05_mode = {
1083 .clock = 54030,
1084 .hdisplay = 1024,
1085 .hsync_start = 1024 + 24,
1086 .hsync_end = 1024 + 24 + 136,
1087 .htotal = 1024 + 24 + 136 + 160,
1088 .vdisplay = 600,
1089 .vsync_start = 600 + 3,
1090 .vsync_end = 600 + 3 + 6,
1091 .vtotal = 600 + 3 + 6 + 61,
1092 .vrefresh = 60,
1093};
1094
1095static const struct panel_desc samsung_ltn101nt05 = {
1096 .modes = &samsung_ltn101nt05_mode,
1097 .num_modes = 1,
0208d511 1098 .bpc = 6,
6d54e3d2
MD		 1099 .size = {
1100 .width = 1024,
1101 .height = 600,
1102 },
1103};
1104
0c934306
SM		 1105static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1106 .clock = 76300,
1107 .hdisplay = 1366,
1108 .hsync_start = 1366 + 64,
1109 .hsync_end = 1366 + 64 + 48,
1110 .htotal = 1366 + 64 + 48 + 128,
1111 .vdisplay = 768,
1112 .vsync_start = 768 + 2,
1113 .vsync_end = 768 + 2 + 5,
1114 .vtotal = 768 + 2 + 5 + 17,
1115 .vrefresh = 60,
1116};
1117
1118static const struct panel_desc samsung_ltn140at29_301 = {
1119 .modes = &samsung_ltn140at29_301_mode,
1120 .num_modes = 1,
1121 .bpc = 6,
1122 .size = {
1123 .width = 320,
1124 .height = 187,
1125 },
1126};
1127
9c6615bc
BB		 1128static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1129 .clock = 33300,
1130 .hdisplay = 800,
1131 .hsync_start = 800 + 1,
1132 .hsync_end = 800 + 1 + 64,
1133 .htotal = 800 + 1 + 64 + 64,
1134 .vdisplay = 480,
1135 .vsync_start = 480 + 1,
1136 .vsync_end = 480 + 1 + 23,
1137 .vtotal = 480 + 1 + 23 + 22,
1138 .vrefresh = 60,
1139};
1140
1141static const struct panel_desc shelly_sca07010_bfn_lnn = {
1142 .modes = &shelly_sca07010_bfn_lnn_mode,
1143 .num_modes = 1,
1144 .size = {
1145 .width = 152,
1146 .height = 91,
1147 },
1148 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1149};
1150
280921de
TR		 1151static const struct of_device_id platform_of_match[] = {
1152 {
1c550fa1
PZ		 1153 .compatible = "ampire,am800480r3tmqwa1h",
1154 .data = &ampire_am800480r3tmqwa1h,
1155 }, {
280921de
TR		 1156 .compatible = "auo,b101aw03",
1157 .data = &auo_b101aw03,
a531bc3d
HL		 1158 }, {
1159 .compatible = "auo,b101ean01",
1160 .data = &auo_b101ean01,
dac746e0
RC		 1161 }, {
1162 .compatible = "auo,b101xtn01",
1163 .data = &auo_b101xtn01,
e35e305e
AK		 1164 }, {
1165 .compatible = "auo,b116xw03",
1166 .data = &auo_b116xw03,
3e51d609
AK		 1167 }, {
1168 .compatible = "auo,b133htn01",
1169 .data = &auo_b133htn01,
a333f7ad
SM		 1170 }, {
1171 .compatible = "auo,b133xtn01",
1172 .data = &auo_b133xtn01,
d47df633
PZ		 1173 }, {
1174 .compatible = "avic,tm070ddh03",
1175 .data = &avic_tm070ddh03,
4c930757
SW		 1176 }, {
1177 .compatible = "chunghwa,claa101wa01a",
1178 .data = &chunghwa_claa101wa01a
280921de
TR		 1179 }, {
1180 .compatible = "chunghwa,claa101wb01",
1181 .data = &chunghwa_claa101wb01
26ab0065
SA		 1182 }, {
1183 .compatible = "edt,et057090dhu",
1184 .data = &edt_et057090dhu,
fff5de45
PZ		 1185 }, {
1186 .compatible = "edt,et070080dh6",
1187 .data = &edt_etm0700g0dh6,
1188 }, {
1189 .compatible = "edt,etm0700g0dh6",
1190 .data = &edt_etm0700g0dh6,
102932b0
BB		 1191 }, {
1192 .compatible = "foxlink,fl500wvr00-a0t",
1193 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1194 }, {
1195 .compatible = "giantplus,gpg482739qs5",
1196 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1197 }, {
1198 .compatible = "hannstar,hsd070pww1",
1199 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 1200 }, {
1201 .compatible = "hannstar,hsd100pxn1",
1202 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 1203 }, {
1204 .compatible = "hit,tx23d38vm0caa",
1205 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1206 }, {
1207 .compatible = "innolux,at043tn24",
1208 .data = &innolux_at043tn24,
d731f661
LS		 1209 }, {
1210 .compatible ="innolux,g121i1-l01",
1211 .data = &innolux_g121i1_l01
f8fa17ba
AB		 1212 }, {
1213 .compatible = "innolux,g121x1-l03",
1214 .data = &innolux_g121x1_l03,
0a2288c0
TR		 1215 }, {
1216 .compatible = "innolux,n116bge",
1217 .data = &innolux_n116bge,
ea44739d
AB		 1218 }, {
1219 .compatible = "innolux,n156bge-l21",
1220 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1221 }, {
1222 .compatible = "innolux,zj070na-01p",
1223 .data = &innolux_zj070na_01p,
8def22e5
LS		 1224 }, {
1225 .compatible = "kyo,tcg121xglp",
1226 .data = &kyo_tcg121xglp,
dd015002
HS		 1227 }, {
1228 .compatible = "lg,lb070wv8",
1229 .data = &lg_lb070wv8,
ec7c5653
TR		 1230 }, {
1231 .compatible = "lg,lp129qe",
1232 .data = &lg_lp129qe,
c6e87f91 1233 }, {
1234 .compatible = "nec,nl4827hc19-05b",
1235 .data = &nec_nl4827hc19_05b,
a99fb626
GB		 1236 }, {
1237 .compatible = "okaya,rs800480t-7x0gp",
1238 .data = &okaya_rs800480t_7x0gp,
725c9d40
PZ		 1239 }, {
1240 .compatible = "ortustech,com43h4m85ulc",
1241 .data = &ortustech_com43h4m85ulc,
6d54e3d2
MD		 1242 }, {
1243 .compatible = "samsung,ltn101nt05",
1244 .data = &samsung_ltn101nt05,
0c934306
SM		 1245 }, {
1246 .compatible = "samsung,ltn140at29-301",
1247 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 1248 }, {
1249 .compatible = "shelly,sca07010-bfn-lnn",
1250 .data = &shelly_sca07010_bfn_lnn,
280921de
TR		 1251 }, {
1252 /* sentinel */
1253 }
1254};
1255MODULE_DEVICE_TABLE(of, platform_of_match);
1256
1257static int panel_simple_platform_probe(struct platform_device *pdev)
1258{
1259 const struct of_device_id *id;
1260
1261 id = of_match_node(platform_of_match, pdev->dev.of_node);
1262 if (!id)
1263 return -ENODEV;
1264
1265 return panel_simple_probe(&pdev->dev, id->data);
1266}
1267
1268static int panel_simple_platform_remove(struct platform_device *pdev)
1269{
1270 return panel_simple_remove(&pdev->dev);
1271}
1272
d02fd93e
TR		 1273static void panel_simple_platform_shutdown(struct platform_device *pdev)
1274{
1275 panel_simple_shutdown(&pdev->dev);
1276}
1277
280921de
TR		 1278static struct platform_driver panel_simple_platform_driver = {
1279 .driver = {
1280 .name = "panel-simple",
280921de
TR		 1281 .of_match_table = platform_of_match,
1282 },
1283 .probe = panel_simple_platform_probe,
1284 .remove = panel_simple_platform_remove,
d02fd93e 1285 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1286};
1287
210fcd9d
TR		 1288struct panel_desc_dsi {
1289 struct panel_desc desc;
1290
462658b8 1291 unsigned long flags;
210fcd9d
TR		 1292 enum mipi_dsi_pixel_format format;
1293 unsigned int lanes;
1294};
1295
d718d79e
TR		 1296static const struct drm_display_mode auo_b080uan01_mode = {
1297 .clock = 154500,
1298 .hdisplay = 1200,
1299 .hsync_start = 1200 + 62,
1300 .hsync_end = 1200 + 62 + 4,
1301 .htotal = 1200 + 62 + 4 + 62,
1302 .vdisplay = 1920,
1303 .vsync_start = 1920 + 9,
1304 .vsync_end = 1920 + 9 + 2,
1305 .vtotal = 1920 + 9 + 2 + 8,
1306 .vrefresh = 60,
1307};
1308
1309static const struct panel_desc_dsi auo_b080uan01 = {
1310 .desc = {
1311 .modes = &auo_b080uan01_mode,
1312 .num_modes = 1,
1313 .bpc = 8,
1314 .size = {
1315 .width = 108,
1316 .height = 272,
1317 },
1318 },
1319 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1320 .format = MIPI_DSI_FMT_RGB888,
1321 .lanes = 4,
1322};
1323
c8521969
CZ		 1324static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1325 .clock = 160000,
1326 .hdisplay = 1200,
1327 .hsync_start = 1200 + 120,
1328 .hsync_end = 1200 + 120 + 20,
1329 .htotal = 1200 + 120 + 20 + 21,
1330 .vdisplay = 1920,
1331 .vsync_start = 1920 + 21,
1332 .vsync_end = 1920 + 21 + 3,
1333 .vtotal = 1920 + 21 + 3 + 18,
1334 .vrefresh = 60,
1335 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1336};
1337
1338static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1339 .desc = {
1340 .modes = &boe_tv080wum_nl0_mode,
1341 .num_modes = 1,
1342 .size = {
1343 .width = 107,
1344 .height = 172,
1345 },
1346 },
1347 .flags = MIPI_DSI_MODE_VIDEO |
1348 MIPI_DSI_MODE_VIDEO_BURST |
1349 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1350 .format = MIPI_DSI_FMT_RGB888,
1351 .lanes = 4,
1352};
1353
712ac1ba
AC		 1354static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1355 .clock = 71000,
1356 .hdisplay = 800,
1357 .hsync_start = 800 + 32,
1358 .hsync_end = 800 + 32 + 1,
1359 .htotal = 800 + 32 + 1 + 57,
1360 .vdisplay = 1280,
1361 .vsync_start = 1280 + 28,
1362 .vsync_end = 1280 + 28 + 1,
1363 .vtotal = 1280 + 28 + 1 + 14,
1364 .vrefresh = 60,
1365};
1366
1367static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1368 .desc = {
1369 .modes = &lg_ld070wx3_sl01_mode,
1370 .num_modes = 1,
d7a839cd 1371 .bpc = 8,
712ac1ba
AC		 1372 .size = {
1373 .width = 94,
1374 .height = 151,
1375 },
1376 },
5e4cc278 1377 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1378 .format = MIPI_DSI_FMT_RGB888,
1379 .lanes = 4,
1380};
1381
499ce85a
AC		 1382static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1383 .clock = 67000,
1384 .hdisplay = 720,
1385 .hsync_start = 720 + 12,
1386 .hsync_end = 720 + 12 + 4,
1387 .htotal = 720 + 12 + 4 + 112,
1388 .vdisplay = 1280,
1389 .vsync_start = 1280 + 8,
1390 .vsync_end = 1280 + 8 + 4,
1391 .vtotal = 1280 + 8 + 4 + 12,
1392 .vrefresh = 60,
1393};
1394
1395static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1396 .desc = {
1397 .modes = &lg_lh500wx1_sd03_mode,
1398 .num_modes = 1,
d7a839cd 1399 .bpc = 8,
499ce85a
AC		 1400 .size = {
1401 .width = 62,
1402 .height = 110,
1403 },
1404 },
1405 .flags = MIPI_DSI_MODE_VIDEO,
1406 .format = MIPI_DSI_FMT_RGB888,
1407 .lanes = 4,
1408};
1409
280921de
TR		 1410static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1411 .clock = 157200,
1412 .hdisplay = 1920,
1413 .hsync_start = 1920 + 154,
1414 .hsync_end = 1920 + 154 + 16,
1415 .htotal = 1920 + 154 + 16 + 32,
1416 .vdisplay = 1200,
1417 .vsync_start = 1200 + 17,
1418 .vsync_end = 1200 + 17 + 2,
1419 .vtotal = 1200 + 17 + 2 + 16,
1420 .vrefresh = 60,
1421};
1422
210fcd9d
TR		 1423static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1424 .desc = {
1425 .modes = &panasonic_vvx10f004b00_mode,
1426 .num_modes = 1,
d7a839cd 1427 .bpc = 8,
210fcd9d
TR		 1428 .size = {
1429 .width = 217,
1430 .height = 136,
1431 },
280921de 1432 },
5e4cc278
AC		 1433 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1434 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1435 .format = MIPI_DSI_FMT_RGB888,
1436 .lanes = 4,
1437};
1438
c8521969 1439
210fcd9d
TR		 1440static const struct of_device_id dsi_of_match[] = {
1441 {
d718d79e
TR		 1442 .compatible = "auo,b080uan01",
1443 .data = &auo_b080uan01
c8521969
CZ		 1444 }, {
1445 .compatible = "boe,tv080wum-nl0",
1446 .data = &boe_tv080wum_nl0
d718d79e 1447 }, {
712ac1ba
AC		 1448 .compatible = "lg,ld070wx3-sl01",
1449 .data = &lg_ld070wx3_sl01
1450 }, {
499ce85a
AC		 1451 .compatible = "lg,lh500wx1-sd03",
1452 .data = &lg_lh500wx1_sd03
1453 }, {
210fcd9d
TR		 1454 .compatible = "panasonic,vvx10f004b00",
1455 .data = &panasonic_vvx10f004b00
1456 }, {
1457 /* sentinel */
1458 }
1459};
1460MODULE_DEVICE_TABLE(of, dsi_of_match);
1461
1462static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1463{
1464 const struct panel_desc_dsi *desc;
1465 const struct of_device_id *id;
1466 int err;
1467
1468 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1469 if (!id)
1470 return -ENODEV;
1471
1472 desc = id->data;
1473
1474 err = panel_simple_probe(&dsi->dev, &desc->desc);
1475 if (err < 0)
1476 return err;
1477
462658b8 1478 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1479 dsi->format = desc->format;
1480 dsi->lanes = desc->lanes;
1481
1482 return mipi_dsi_attach(dsi);
1483}
1484
1485static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1486{
1487 int err;
1488
1489 err = mipi_dsi_detach(dsi);
1490 if (err < 0)
1491 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1492
1493 return panel_simple_remove(&dsi->dev);
1494}
1495
d02fd93e
TR		 1496static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1497{
1498 panel_simple_shutdown(&dsi->dev);
1499}
1500
210fcd9d
TR		 1501static struct mipi_dsi_driver panel_simple_dsi_driver = {
1502 .driver = {
1503 .name = "panel-simple-dsi",
210fcd9d
TR		 1504 .of_match_table = dsi_of_match,
1505 },
1506 .probe = panel_simple_dsi_probe,
1507 .remove = panel_simple_dsi_remove,
d02fd93e 1508 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1509};
1510
1511static int __init panel_simple_init(void)
1512{
210fcd9d
TR		 1513 int err;
1514
1515 err = platform_driver_register(&panel_simple_platform_driver);
1516 if (err < 0)
1517 return err;
1518
1519 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1520 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1521 if (err < 0)
1522 return err;
1523 }
1524
1525 return 0;
280921de
TR		 1526}
1527module_init(panel_simple_init);
1528
1529static void __exit panel_simple_exit(void)
1530{
210fcd9d
TR		 1531 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1532 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1533
280921de
TR		 1534 platform_driver_unregister(&panel_simple_platform_driver);
1535}
1536module_exit(panel_simple_exit);
1537
1538MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1539MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1540MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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