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drm/panel: simple: Add display timing support
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
280921de
TR		 47 struct {
48 unsigned int width;
49 unsigned int height;
50 } size;
f673c37e
AK		 51
52 /**
53 * @prepare: the time (in milliseconds) that it takes for the panel to
54 * become ready and start receiving video data
55 * @enable: the time (in milliseconds) that it takes for the panel to
56 * display the first valid frame after starting to receive
57 * video data
58 * @disable: the time (in milliseconds) that it takes for the panel to
59 * turn the display off (no content is visible)
60 * @unprepare: the time (in milliseconds) that it takes for the panel
61 * to power itself down completely
62 */
63 struct {
64 unsigned int prepare;
65 unsigned int enable;
66 unsigned int disable;
67 unsigned int unprepare;
68 } delay;
795f7ab3
BB		 69
70 u32 bus_format;
280921de
TR		 71};
72
280921de
TR		 73struct panel_simple {
74 struct drm_panel base;
613a633e 75 bool prepared;
280921de
TR		 76 bool enabled;
77
78 const struct panel_desc *desc;
79
80 struct backlight_device *backlight;
81 struct regulator *supply;
82 struct i2c_adapter *ddc;
83
cfdf0549 84 struct gpio_desc *enable_gpio;
280921de
TR		 85};
86
87static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
88{
89 return container_of(panel, struct panel_simple, base);
90}
91
92static int panel_simple_get_fixed_modes(struct panel_simple *panel)
93{
94 struct drm_connector *connector = panel->base.connector;
95 struct drm_device *drm = panel->base.drm;
96 struct drm_display_mode *mode;
97 unsigned int i, num = 0;
98
99 if (!panel->desc)
100 return 0;
101
a5d3e625
PZ		 102 for (i = 0; i < panel->desc->num_timings; i++) {
103 const struct display_timing *dt = &panel->desc->timings[i];
104 struct videomode vm;
105
106 videomode_from_timing(dt, &vm);
107 mode = drm_mode_create(drm);
108 if (!mode) {
109 dev_err(drm->dev, "failed to add mode %ux%u\n",
110 dt->hactive.typ, dt->vactive.typ);
111 continue;
112 }
113
114 drm_display_mode_from_videomode(&vm, mode);
115 drm_mode_set_name(mode);
116
117 drm_mode_probed_add(connector, mode);
118 num++;
119 }
120
280921de
TR		 121 for (i = 0; i < panel->desc->num_modes; i++) {
122 const struct drm_display_mode *m = &panel->desc->modes[i];
123
124 mode = drm_mode_duplicate(drm, m);
125 if (!mode) {
126 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
127 m->hdisplay, m->vdisplay, m->vrefresh);
128 continue;
129 }
130
131 drm_mode_set_name(mode);
132
133 drm_mode_probed_add(connector, mode);
134 num++;
135 }
136
0208d511 137 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 138 connector->display_info.width_mm = panel->desc->size.width;
139 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 140 if (panel->desc->bus_format)
141 drm_display_info_set_bus_formats(&connector->display_info,
142 &panel->desc->bus_format, 1);
280921de
TR		 143
144 return num;
145}
146
147static int panel_simple_disable(struct drm_panel *panel)
148{
149 struct panel_simple *p = to_panel_simple(panel);
150
151 if (!p->enabled)
152 return 0;
153
154 if (p->backlight) {
155 p->backlight->props.power = FB_BLANK_POWERDOWN;
156 backlight_update_status(p->backlight);
157 }
158
f673c37e
AK		 159 if (p->desc->delay.disable)
160 msleep(p->desc->delay.disable);
161
280921de
TR		 162 p->enabled = false;
163
164 return 0;
165}
166
c0e1d170
AK		 167static int panel_simple_unprepare(struct drm_panel *panel)
168{
613a633e
AK		 169 struct panel_simple *p = to_panel_simple(panel);
170
171 if (!p->prepared)
172 return 0;
173
174 if (p->enable_gpio)
175 gpiod_set_value_cansleep(p->enable_gpio, 0);
176
177 regulator_disable(p->supply);
178
f673c37e
AK		 179 if (p->desc->delay.unprepare)
180 msleep(p->desc->delay.unprepare);
181
613a633e 182 p->prepared = false;
c0e1d170 183
c0e1d170
AK		 184 return 0;
185}
186
613a633e 187static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 188{
189 struct panel_simple *p = to_panel_simple(panel);
190 int err;
191
613a633e 192 if (p->prepared)
280921de
TR		 193 return 0;
194
195 err = regulator_enable(p->supply);
196 if (err < 0) {
197 dev_err(panel->dev, "failed to enable supply: %d\n", err);
198 return err;
199 }
200
cfdf0549 201 if (p->enable_gpio)
15c1a919 202 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 203
f673c37e
AK		 204 if (p->desc->delay.prepare)
205 msleep(p->desc->delay.prepare);
206
613a633e
AK		 207 p->prepared = true;
208
209 return 0;
210}
211
212static int panel_simple_enable(struct drm_panel *panel)
213{
214 struct panel_simple *p = to_panel_simple(panel);
215
216 if (p->enabled)
217 return 0;
218
f673c37e
AK		 219 if (p->desc->delay.enable)
220 msleep(p->desc->delay.enable);
221
280921de
TR		 222 if (p->backlight) {
223 p->backlight->props.power = FB_BLANK_UNBLANK;
224 backlight_update_status(p->backlight);
225 }
226
227 p->enabled = true;
228
229 return 0;
230}
231
232static int panel_simple_get_modes(struct drm_panel *panel)
233{
234 struct panel_simple *p = to_panel_simple(panel);
235 int num = 0;
236
237 /* probe EDID if a DDC bus is available */
238 if (p->ddc) {
239 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 240 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 241 if (edid) {
242 num += drm_add_edid_modes(panel->connector, edid);
243 kfree(edid);
244 }
245 }
246
247 /* add hard-coded panel modes */
248 num += panel_simple_get_fixed_modes(p);
249
250 return num;
251}
252
a5d3e625
PZ		 253static int panel_simple_get_timings(struct drm_panel *panel,
254 unsigned int num_timings,
255 struct display_timing *timings)
256{
257 struct panel_simple *p = to_panel_simple(panel);
258 unsigned int i;
259
260 if (p->desc->num_timings < num_timings)
261 num_timings = p->desc->num_timings;
262
263 if (timings)
264 for (i = 0; i < num_timings; i++)
265 timings[i] = p->desc->timings[i];
266
267 return p->desc->num_timings;
268}
269
280921de
TR		 270static const struct drm_panel_funcs panel_simple_funcs = {
271 .disable = panel_simple_disable,
c0e1d170
AK		 272 .unprepare = panel_simple_unprepare,
273 .prepare = panel_simple_prepare,
280921de
TR		 274 .enable = panel_simple_enable,
275 .get_modes = panel_simple_get_modes,
a5d3e625 276 .get_timings = panel_simple_get_timings,
280921de
TR		 277};
278
279static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
280{
281 struct device_node *backlight, *ddc;
282 struct panel_simple *panel;
280921de
TR		 283 int err;
284
285 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
286 if (!panel)
287 return -ENOMEM;
288
289 panel->enabled = false;
613a633e 290 panel->prepared = false;
280921de
TR		 291 panel->desc = desc;
292
293 panel->supply = devm_regulator_get(dev, "power");
294 if (IS_ERR(panel->supply))
295 return PTR_ERR(panel->supply);
296
a61400d8
AC		 297 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
298 GPIOD_OUT_LOW);
cfdf0549
AC		 299 if (IS_ERR(panel->enable_gpio)) {
300 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 301 dev_err(dev, "failed to request GPIO: %d\n", err);
302 return err;
303 }
280921de 304
280921de
TR		 305 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
306 if (backlight) {
307 panel->backlight = of_find_backlight_by_node(backlight);
308 of_node_put(backlight);
309
cfdf0549
AC		 310 if (!panel->backlight)
311 return -EPROBE_DEFER;
280921de
TR		 312 }
313
314 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
315 if (ddc) {
316 panel->ddc = of_find_i2c_adapter_by_node(ddc);
317 of_node_put(ddc);
318
319 if (!panel->ddc) {
320 err = -EPROBE_DEFER;
321 goto free_backlight;
322 }
323 }
324
325 drm_panel_init(&panel->base);
326 panel->base.dev = dev;
327 panel->base.funcs = &panel_simple_funcs;
328
329 err = drm_panel_add(&panel->base);
330 if (err < 0)
331 goto free_ddc;
332
333 dev_set_drvdata(dev, panel);
334
335 return 0;
336
337free_ddc:
338 if (panel->ddc)
339 put_device(&panel->ddc->dev);
340free_backlight:
341 if (panel->backlight)
342 put_device(&panel->backlight->dev);
280921de
TR		 343
344 return err;
345}
346
347static int panel_simple_remove(struct device *dev)
348{
349 struct panel_simple *panel = dev_get_drvdata(dev);
350
351 drm_panel_detach(&panel->base);
352 drm_panel_remove(&panel->base);
353
354 panel_simple_disable(&panel->base);
355
356 if (panel->ddc)
357 put_device(&panel->ddc->dev);
358
359 if (panel->backlight)
360 put_device(&panel->backlight->dev);
361
280921de
TR		 362 return 0;
363}
364
d02fd93e
TR		 365static void panel_simple_shutdown(struct device *dev)
366{
367 struct panel_simple *panel = dev_get_drvdata(dev);
368
369 panel_simple_disable(&panel->base);
370}
371
280921de
TR		 372static const struct drm_display_mode auo_b101aw03_mode = {
373 .clock = 51450,
374 .hdisplay = 1024,
375 .hsync_start = 1024 + 156,
376 .hsync_end = 1024 + 156 + 8,
377 .htotal = 1024 + 156 + 8 + 156,
378 .vdisplay = 600,
379 .vsync_start = 600 + 16,
380 .vsync_end = 600 + 16 + 6,
381 .vtotal = 600 + 16 + 6 + 16,
382 .vrefresh = 60,
383};
384
385static const struct panel_desc auo_b101aw03 = {
386 .modes = &auo_b101aw03_mode,
387 .num_modes = 1,
0208d511 388 .bpc = 6,
280921de
TR		 389 .size = {
390 .width = 223,
391 .height = 125,
392 },
393};
394
a531bc3d
HL		 395static const struct drm_display_mode auo_b101ean01_mode = {
396 .clock = 72500,
397 .hdisplay = 1280,
398 .hsync_start = 1280 + 119,
399 .hsync_end = 1280 + 119 + 32,
400 .htotal = 1280 + 119 + 32 + 21,
401 .vdisplay = 800,
402 .vsync_start = 800 + 4,
403 .vsync_end = 800 + 4 + 20,
404 .vtotal = 800 + 4 + 20 + 8,
405 .vrefresh = 60,
406};
407
408static const struct panel_desc auo_b101ean01 = {
409 .modes = &auo_b101ean01_mode,
410 .num_modes = 1,
411 .bpc = 6,
412 .size = {
413 .width = 217,
414 .height = 136,
415 },
416};
417
dac746e0
RC		 418static const struct drm_display_mode auo_b101xtn01_mode = {
419 .clock = 72000,
420 .hdisplay = 1366,
421 .hsync_start = 1366 + 20,
422 .hsync_end = 1366 + 20 + 70,
423 .htotal = 1366 + 20 + 70,
424 .vdisplay = 768,
425 .vsync_start = 768 + 14,
426 .vsync_end = 768 + 14 + 42,
427 .vtotal = 768 + 14 + 42,
428 .vrefresh = 60,
429 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
430};
431
432static const struct panel_desc auo_b101xtn01 = {
433 .modes = &auo_b101xtn01_mode,
434 .num_modes = 1,
435 .bpc = 6,
436 .size = {
437 .width = 223,
438 .height = 125,
439 },
440};
441
e35e305e
AK		 442static const struct drm_display_mode auo_b116xw03_mode = {
443 .clock = 70589,
444 .hdisplay = 1366,
445 .hsync_start = 1366 + 40,
446 .hsync_end = 1366 + 40 + 40,
447 .htotal = 1366 + 40 + 40 + 32,
448 .vdisplay = 768,
449 .vsync_start = 768 + 10,
450 .vsync_end = 768 + 10 + 12,
451 .vtotal = 768 + 10 + 12 + 6,
452 .vrefresh = 60,
453};
454
455static const struct panel_desc auo_b116xw03 = {
456 .modes = &auo_b116xw03_mode,
457 .num_modes = 1,
458 .bpc = 6,
459 .size = {
460 .width = 256,
461 .height = 144,
462 },
463};
464
a333f7ad
SM		 465static const struct drm_display_mode auo_b133xtn01_mode = {
466 .clock = 69500,
467 .hdisplay = 1366,
468 .hsync_start = 1366 + 48,
469 .hsync_end = 1366 + 48 + 32,
470 .htotal = 1366 + 48 + 32 + 20,
471 .vdisplay = 768,
472 .vsync_start = 768 + 3,
473 .vsync_end = 768 + 3 + 6,
474 .vtotal = 768 + 3 + 6 + 13,
475 .vrefresh = 60,
476};
477
478static const struct panel_desc auo_b133xtn01 = {
479 .modes = &auo_b133xtn01_mode,
480 .num_modes = 1,
0208d511 481 .bpc = 6,
a333f7ad
SM		 482 .size = {
483 .width = 293,
484 .height = 165,
485 },
486};
487
3e51d609
AK		 488static const struct drm_display_mode auo_b133htn01_mode = {
489 .clock = 150660,
490 .hdisplay = 1920,
491 .hsync_start = 1920 + 172,
492 .hsync_end = 1920 + 172 + 80,
493 .htotal = 1920 + 172 + 80 + 60,
494 .vdisplay = 1080,
495 .vsync_start = 1080 + 25,
496 .vsync_end = 1080 + 25 + 10,
497 .vtotal = 1080 + 25 + 10 + 10,
498 .vrefresh = 60,
499};
500
501static const struct panel_desc auo_b133htn01 = {
502 .modes = &auo_b133htn01_mode,
503 .num_modes = 1,
d7a839cd 504 .bpc = 6,
3e51d609
AK		 505 .size = {
506 .width = 293,
507 .height = 165,
508 },
509 .delay = {
510 .prepare = 105,
511 .enable = 20,
512 .unprepare = 50,
513 },
514};
515
d47df633
PZ		 516static const struct drm_display_mode avic_tm070ddh03_mode = {
517 .clock = 51200,
518 .hdisplay = 1024,
519 .hsync_start = 1024 + 160,
520 .hsync_end = 1024 + 160 + 4,
521 .htotal = 1024 + 160 + 4 + 156,
522 .vdisplay = 600,
523 .vsync_start = 600 + 17,
524 .vsync_end = 600 + 17 + 1,
525 .vtotal = 600 + 17 + 1 + 17,
526 .vrefresh = 60,
527};
528
529static const struct panel_desc avic_tm070ddh03 = {
530 .modes = &avic_tm070ddh03_mode,
531 .num_modes = 1,
532 .bpc = 8,
533 .size = {
534 .width = 154,
535 .height = 90,
536 },
537 .delay = {
538 .prepare = 20,
539 .enable = 200,
540 .disable = 200,
541 },
542};
543
4c930757
SW		 544static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
545 .clock = 72070,
546 .hdisplay = 1366,
547 .hsync_start = 1366 + 58,
548 .hsync_end = 1366 + 58 + 58,
549 .htotal = 1366 + 58 + 58 + 58,
550 .vdisplay = 768,
551 .vsync_start = 768 + 4,
552 .vsync_end = 768 + 4 + 4,
553 .vtotal = 768 + 4 + 4 + 4,
554 .vrefresh = 60,
555};
556
557static const struct panel_desc chunghwa_claa101wa01a = {
558 .modes = &chunghwa_claa101wa01a_mode,
559 .num_modes = 1,
0208d511 560 .bpc = 6,
4c930757
SW		 561 .size = {
562 .width = 220,
563 .height = 120,
564 },
565};
566
280921de
TR		 567static const struct drm_display_mode chunghwa_claa101wb01_mode = {
568 .clock = 69300,
569 .hdisplay = 1366,
570 .hsync_start = 1366 + 48,
571 .hsync_end = 1366 + 48 + 32,
572 .htotal = 1366 + 48 + 32 + 20,
573 .vdisplay = 768,
574 .vsync_start = 768 + 16,
575 .vsync_end = 768 + 16 + 8,
576 .vtotal = 768 + 16 + 8 + 16,
577 .vrefresh = 60,
578};
579
580static const struct panel_desc chunghwa_claa101wb01 = {
581 .modes = &chunghwa_claa101wb01_mode,
582 .num_modes = 1,
0208d511 583 .bpc = 6,
280921de
TR		 584 .size = {
585 .width = 223,
586 .height = 125,
587 },
588};
589
26ab0065
SA		 590static const struct drm_display_mode edt_et057090dhu_mode = {
591 .clock = 25175,
592 .hdisplay = 640,
593 .hsync_start = 640 + 16,
594 .hsync_end = 640 + 16 + 30,
595 .htotal = 640 + 16 + 30 + 114,
596 .vdisplay = 480,
597 .vsync_start = 480 + 10,
598 .vsync_end = 480 + 10 + 3,
599 .vtotal = 480 + 10 + 3 + 32,
600 .vrefresh = 60,
601 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
602};
603
604static const struct panel_desc edt_et057090dhu = {
605 .modes = &edt_et057090dhu_mode,
606 .num_modes = 1,
0208d511 607 .bpc = 6,
26ab0065
SA		 608 .size = {
609 .width = 115,
610 .height = 86,
611 },
612};
613
fff5de45
PZ		 614static const struct drm_display_mode edt_etm0700g0dh6_mode = {
615 .clock = 33260,
616 .hdisplay = 800,
617 .hsync_start = 800 + 40,
618 .hsync_end = 800 + 40 + 128,
619 .htotal = 800 + 40 + 128 + 88,
620 .vdisplay = 480,
621 .vsync_start = 480 + 10,
622 .vsync_end = 480 + 10 + 2,
623 .vtotal = 480 + 10 + 2 + 33,
624 .vrefresh = 60,
625 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
626};
627
628static const struct panel_desc edt_etm0700g0dh6 = {
629 .modes = &edt_etm0700g0dh6_mode,
630 .num_modes = 1,
0208d511 631 .bpc = 6,
fff5de45
PZ		 632 .size = {
633 .width = 152,
634 .height = 91,
635 },
636};
637
102932b0
BB		 638static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
639 .clock = 32260,
640 .hdisplay = 800,
641 .hsync_start = 800 + 168,
642 .hsync_end = 800 + 168 + 64,
643 .htotal = 800 + 168 + 64 + 88,
644 .vdisplay = 480,
645 .vsync_start = 480 + 37,
646 .vsync_end = 480 + 37 + 2,
647 .vtotal = 480 + 37 + 2 + 8,
648 .vrefresh = 60,
649};
650
651static const struct panel_desc foxlink_fl500wvr00_a0t = {
652 .modes = &foxlink_fl500wvr00_a0t_mode,
653 .num_modes = 1,
d7a839cd 654 .bpc = 8,
102932b0
BB		 655 .size = {
656 .width = 108,
657 .height = 65,
658 },
bb276cb3 659 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 660};
661
d435a2af
PZ		 662static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
663 .clock = 9000,
664 .hdisplay = 480,
665 .hsync_start = 480 + 5,
666 .hsync_end = 480 + 5 + 1,
667 .htotal = 480 + 5 + 1 + 40,
668 .vdisplay = 272,
669 .vsync_start = 272 + 8,
670 .vsync_end = 272 + 8 + 1,
671 .vtotal = 272 + 8 + 1 + 8,
672 .vrefresh = 60,
673};
674
675static const struct panel_desc giantplus_gpg482739qs5 = {
676 .modes = &giantplus_gpg482739qs5_mode,
677 .num_modes = 1,
678 .bpc = 8,
679 .size = {
680 .width = 95,
681 .height = 54,
682 },
33536a09 683 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 684};
685
a853205e
PZ		 686static const struct drm_display_mode hannstar_hsd070pww1_mode = {
687 .clock = 71100,
688 .hdisplay = 1280,
689 .hsync_start = 1280 + 1,
690 .hsync_end = 1280 + 1 + 158,
691 .htotal = 1280 + 1 + 158 + 1,
692 .vdisplay = 800,
693 .vsync_start = 800 + 1,
694 .vsync_end = 800 + 1 + 21,
695 .vtotal = 800 + 1 + 21 + 1,
696 .vrefresh = 60,
697};
698
699static const struct panel_desc hannstar_hsd070pww1 = {
700 .modes = &hannstar_hsd070pww1_mode,
701 .num_modes = 1,
702 .bpc = 6,
703 .size = {
704 .width = 151,
705 .height = 94,
706 },
707};
708
61ac0bf8
LS		 709static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
710 .clock = 33333,
711 .hdisplay = 800,
712 .hsync_start = 800 + 85,
713 .hsync_end = 800 + 85 + 86,
714 .htotal = 800 + 85 + 86 + 85,
715 .vdisplay = 480,
716 .vsync_start = 480 + 16,
717 .vsync_end = 480 + 16 + 13,
718 .vtotal = 480 + 16 + 13 + 16,
719 .vrefresh = 60,
720};
721
722static const struct panel_desc hitachi_tx23d38vm0caa = {
723 .modes = &hitachi_tx23d38vm0caa_mode,
724 .num_modes = 1,
725 .bpc = 6,
726 .size = {
727 .width = 195,
728 .height = 117,
729 },
730};
731
41bcceb4
NF		 732static const struct drm_display_mode innolux_at043tn24_mode = {
733 .clock = 9000,
734 .hdisplay = 480,
735 .hsync_start = 480 + 2,
736 .hsync_end = 480 + 2 + 41,
737 .htotal = 480 + 2 + 41 + 2,
738 .vdisplay = 272,
739 .vsync_start = 272 + 2,
740 .vsync_end = 272 + 2 + 11,
741 .vtotal = 272 + 2 + 11 + 2,
742 .vrefresh = 60,
743 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
744};
745
746static const struct panel_desc innolux_at043tn24 = {
747 .modes = &innolux_at043tn24_mode,
748 .num_modes = 1,
749 .bpc = 8,
750 .size = {
751 .width = 95,
752 .height = 54,
753 },
754 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
755};
756
d731f661 757static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 758 .clock = 71000,
d731f661
LS		 759 .hdisplay = 1280,
760 .hsync_start = 1280 + 64,
761 .hsync_end = 1280 + 64 + 32,
762 .htotal = 1280 + 64 + 32 + 64,
763 .vdisplay = 800,
764 .vsync_start = 800 + 9,
765 .vsync_end = 800 + 9 + 6,
766 .vtotal = 800 + 9 + 6 + 9,
767 .vrefresh = 60,
768};
769
770static const struct panel_desc innolux_g121i1_l01 = {
771 .modes = &innolux_g121i1_l01_mode,
772 .num_modes = 1,
773 .bpc = 6,
774 .size = {
775 .width = 261,
776 .height = 163,
777 },
778};
779
0a2288c0 780static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 781 .clock = 76420,
0a2288c0 782 .hdisplay = 1366,
7fe8c777
DK		 783 .hsync_start = 1366 + 136,
784 .hsync_end = 1366 + 136 + 30,
785 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 786 .vdisplay = 768,
787 .vsync_start = 768 + 8,
7fe8c777
DK		 788 .vsync_end = 768 + 8 + 12,
789 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 790 .vrefresh = 60,
791 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
792};
793
794static const struct panel_desc innolux_n116bge = {
795 .modes = &innolux_n116bge_mode,
796 .num_modes = 1,
797 .bpc = 6,
798 .size = {
799 .width = 256,
800 .height = 144,
801 },
802};
803
ea44739d
AB		 804static const struct drm_display_mode innolux_n156bge_l21_mode = {
805 .clock = 69300,
806 .hdisplay = 1366,
807 .hsync_start = 1366 + 16,
808 .hsync_end = 1366 + 16 + 34,
809 .htotal = 1366 + 16 + 34 + 50,
810 .vdisplay = 768,
811 .vsync_start = 768 + 2,
812 .vsync_end = 768 + 2 + 6,
813 .vtotal = 768 + 2 + 6 + 12,
814 .vrefresh = 60,
815};
816
817static const struct panel_desc innolux_n156bge_l21 = {
818 .modes = &innolux_n156bge_l21_mode,
819 .num_modes = 1,
0208d511 820 .bpc = 6,
ea44739d
AB		 821 .size = {
822 .width = 344,
823 .height = 193,
824 },
825};
826
bccac3f1
MG		 827static const struct drm_display_mode innolux_zj070na_01p_mode = {
828 .clock = 51501,
829 .hdisplay = 1024,
830 .hsync_start = 1024 + 128,
831 .hsync_end = 1024 + 128 + 64,
832 .htotal = 1024 + 128 + 64 + 128,
833 .vdisplay = 600,
834 .vsync_start = 600 + 16,
835 .vsync_end = 600 + 16 + 4,
836 .vtotal = 600 + 16 + 4 + 16,
837 .vrefresh = 60,
838};
839
840static const struct panel_desc innolux_zj070na_01p = {
841 .modes = &innolux_zj070na_01p_mode,
842 .num_modes = 1,
843 .bpc = 6,
844 .size = {
845 .width = 1024,
846 .height = 600,
847 },
848};
849
ec7c5653
TR		 850static const struct drm_display_mode lg_lp129qe_mode = {
851 .clock = 285250,
852 .hdisplay = 2560,
853 .hsync_start = 2560 + 48,
854 .hsync_end = 2560 + 48 + 32,
855 .htotal = 2560 + 48 + 32 + 80,
856 .vdisplay = 1700,
857 .vsync_start = 1700 + 3,
858 .vsync_end = 1700 + 3 + 10,
859 .vtotal = 1700 + 3 + 10 + 36,
860 .vrefresh = 60,
861};
862
863static const struct panel_desc lg_lp129qe = {
864 .modes = &lg_lp129qe_mode,
865 .num_modes = 1,
0208d511 866 .bpc = 8,
ec7c5653
TR		 867 .size = {
868 .width = 272,
869 .height = 181,
870 },
871};
872
725c9d40
PZ		 873static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
874 .clock = 25000,
875 .hdisplay = 480,
876 .hsync_start = 480 + 10,
877 .hsync_end = 480 + 10 + 10,
878 .htotal = 480 + 10 + 10 + 15,
879 .vdisplay = 800,
880 .vsync_start = 800 + 3,
881 .vsync_end = 800 + 3 + 3,
882 .vtotal = 800 + 3 + 3 + 3,
883 .vrefresh = 60,
884};
885
886static const struct panel_desc ortustech_com43h4m85ulc = {
887 .modes = &ortustech_com43h4m85ulc_mode,
888 .num_modes = 1,
889 .bpc = 8,
890 .size = {
891 .width = 56,
892 .height = 93,
893 },
894 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
895};
896
6d54e3d2
MD		 897static const struct drm_display_mode samsung_ltn101nt05_mode = {
898 .clock = 54030,
899 .hdisplay = 1024,
900 .hsync_start = 1024 + 24,
901 .hsync_end = 1024 + 24 + 136,
902 .htotal = 1024 + 24 + 136 + 160,
903 .vdisplay = 600,
904 .vsync_start = 600 + 3,
905 .vsync_end = 600 + 3 + 6,
906 .vtotal = 600 + 3 + 6 + 61,
907 .vrefresh = 60,
908};
909
910static const struct panel_desc samsung_ltn101nt05 = {
911 .modes = &samsung_ltn101nt05_mode,
912 .num_modes = 1,
0208d511 913 .bpc = 6,
6d54e3d2
MD		 914 .size = {
915 .width = 1024,
916 .height = 600,
917 },
918};
919
0c934306
SM		 920static const struct drm_display_mode samsung_ltn140at29_301_mode = {
921 .clock = 76300,
922 .hdisplay = 1366,
923 .hsync_start = 1366 + 64,
924 .hsync_end = 1366 + 64 + 48,
925 .htotal = 1366 + 64 + 48 + 128,
926 .vdisplay = 768,
927 .vsync_start = 768 + 2,
928 .vsync_end = 768 + 2 + 5,
929 .vtotal = 768 + 2 + 5 + 17,
930 .vrefresh = 60,
931};
932
933static const struct panel_desc samsung_ltn140at29_301 = {
934 .modes = &samsung_ltn140at29_301_mode,
935 .num_modes = 1,
936 .bpc = 6,
937 .size = {
938 .width = 320,
939 .height = 187,
940 },
941};
942
9c6615bc
BB		 943static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
944 .clock = 33300,
945 .hdisplay = 800,
946 .hsync_start = 800 + 1,
947 .hsync_end = 800 + 1 + 64,
948 .htotal = 800 + 1 + 64 + 64,
949 .vdisplay = 480,
950 .vsync_start = 480 + 1,
951 .vsync_end = 480 + 1 + 23,
952 .vtotal = 480 + 1 + 23 + 22,
953 .vrefresh = 60,
954};
955
956static const struct panel_desc shelly_sca07010_bfn_lnn = {
957 .modes = &shelly_sca07010_bfn_lnn_mode,
958 .num_modes = 1,
959 .size = {
960 .width = 152,
961 .height = 91,
962 },
963 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
964};
965
280921de
TR		 966static const struct of_device_id platform_of_match[] = {
967 {
968 .compatible = "auo,b101aw03",
969 .data = &auo_b101aw03,
a531bc3d
HL		 970 }, {
971 .compatible = "auo,b101ean01",
972 .data = &auo_b101ean01,
dac746e0
RC		 973 }, {
974 .compatible = "auo,b101xtn01",
975 .data = &auo_b101xtn01,
e35e305e
AK		 976 }, {
977 .compatible = "auo,b116xw03",
978 .data = &auo_b116xw03,
3e51d609
AK		 979 }, {
980 .compatible = "auo,b133htn01",
981 .data = &auo_b133htn01,
a333f7ad
SM		 982 }, {
983 .compatible = "auo,b133xtn01",
984 .data = &auo_b133xtn01,
d47df633
PZ		 985 }, {
986 .compatible = "avic,tm070ddh03",
987 .data = &avic_tm070ddh03,
4c930757
SW		 988 }, {
989 .compatible = "chunghwa,claa101wa01a",
990 .data = &chunghwa_claa101wa01a
280921de
TR		 991 }, {
992 .compatible = "chunghwa,claa101wb01",
993 .data = &chunghwa_claa101wb01
26ab0065
SA		 994 }, {
995 .compatible = "edt,et057090dhu",
996 .data = &edt_et057090dhu,
fff5de45
PZ		 997 }, {
998 .compatible = "edt,et070080dh6",
999 .data = &edt_etm0700g0dh6,
1000 }, {
1001 .compatible = "edt,etm0700g0dh6",
1002 .data = &edt_etm0700g0dh6,
102932b0
BB		 1003 }, {
1004 .compatible = "foxlink,fl500wvr00-a0t",
1005 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1006 }, {
1007 .compatible = "giantplus,gpg482739qs5",
1008 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1009 }, {
1010 .compatible = "hannstar,hsd070pww1",
1011 .data = &hannstar_hsd070pww1,
61ac0bf8
LS		 1012 }, {
1013 .compatible = "hit,tx23d38vm0caa",
1014 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1015 }, {
1016 .compatible = "innolux,at043tn24",
1017 .data = &innolux_at043tn24,
d731f661
LS		 1018 }, {
1019 .compatible ="innolux,g121i1-l01",
1020 .data = &innolux_g121i1_l01
0a2288c0
TR		 1021 }, {
1022 .compatible = "innolux,n116bge",
1023 .data = &innolux_n116bge,
ea44739d
AB		 1024 }, {
1025 .compatible = "innolux,n156bge-l21",
1026 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1027 }, {
1028 .compatible = "innolux,zj070na-01p",
1029 .data = &innolux_zj070na_01p,
ec7c5653
TR		 1030 }, {
1031 .compatible = "lg,lp129qe",
1032 .data = &lg_lp129qe,
725c9d40
PZ		 1033 }, {
1034 .compatible = "ortustech,com43h4m85ulc",
1035 .data = &ortustech_com43h4m85ulc,
6d54e3d2
MD		 1036 }, {
1037 .compatible = "samsung,ltn101nt05",
1038 .data = &samsung_ltn101nt05,
0c934306
SM		 1039 }, {
1040 .compatible = "samsung,ltn140at29-301",
1041 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 1042 }, {
1043 .compatible = "shelly,sca07010-bfn-lnn",
1044 .data = &shelly_sca07010_bfn_lnn,
280921de
TR		 1045 }, {
1046 /* sentinel */
1047 }
1048};
1049MODULE_DEVICE_TABLE(of, platform_of_match);
1050
1051static int panel_simple_platform_probe(struct platform_device *pdev)
1052{
1053 const struct of_device_id *id;
1054
1055 id = of_match_node(platform_of_match, pdev->dev.of_node);
1056 if (!id)
1057 return -ENODEV;
1058
1059 return panel_simple_probe(&pdev->dev, id->data);
1060}
1061
1062static int panel_simple_platform_remove(struct platform_device *pdev)
1063{
1064 return panel_simple_remove(&pdev->dev);
1065}
1066
d02fd93e
TR		 1067static void panel_simple_platform_shutdown(struct platform_device *pdev)
1068{
1069 panel_simple_shutdown(&pdev->dev);
1070}
1071
280921de
TR		 1072static struct platform_driver panel_simple_platform_driver = {
1073 .driver = {
1074 .name = "panel-simple",
280921de
TR		 1075 .of_match_table = platform_of_match,
1076 },
1077 .probe = panel_simple_platform_probe,
1078 .remove = panel_simple_platform_remove,
d02fd93e 1079 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1080};
1081
210fcd9d
TR		 1082struct panel_desc_dsi {
1083 struct panel_desc desc;
1084
462658b8 1085 unsigned long flags;
210fcd9d
TR		 1086 enum mipi_dsi_pixel_format format;
1087 unsigned int lanes;
1088};
1089
712ac1ba
AC		 1090static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1091 .clock = 71000,
1092 .hdisplay = 800,
1093 .hsync_start = 800 + 32,
1094 .hsync_end = 800 + 32 + 1,
1095 .htotal = 800 + 32 + 1 + 57,
1096 .vdisplay = 1280,
1097 .vsync_start = 1280 + 28,
1098 .vsync_end = 1280 + 28 + 1,
1099 .vtotal = 1280 + 28 + 1 + 14,
1100 .vrefresh = 60,
1101};
1102
1103static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1104 .desc = {
1105 .modes = &lg_ld070wx3_sl01_mode,
1106 .num_modes = 1,
d7a839cd 1107 .bpc = 8,
712ac1ba
AC		 1108 .size = {
1109 .width = 94,
1110 .height = 151,
1111 },
1112 },
5e4cc278 1113 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1114 .format = MIPI_DSI_FMT_RGB888,
1115 .lanes = 4,
1116};
1117
499ce85a
AC		 1118static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1119 .clock = 67000,
1120 .hdisplay = 720,
1121 .hsync_start = 720 + 12,
1122 .hsync_end = 720 + 12 + 4,
1123 .htotal = 720 + 12 + 4 + 112,
1124 .vdisplay = 1280,
1125 .vsync_start = 1280 + 8,
1126 .vsync_end = 1280 + 8 + 4,
1127 .vtotal = 1280 + 8 + 4 + 12,
1128 .vrefresh = 60,
1129};
1130
1131static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1132 .desc = {
1133 .modes = &lg_lh500wx1_sd03_mode,
1134 .num_modes = 1,
d7a839cd 1135 .bpc = 8,
499ce85a
AC		 1136 .size = {
1137 .width = 62,
1138 .height = 110,
1139 },
1140 },
1141 .flags = MIPI_DSI_MODE_VIDEO,
1142 .format = MIPI_DSI_FMT_RGB888,
1143 .lanes = 4,
1144};
1145
280921de
TR		 1146static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1147 .clock = 157200,
1148 .hdisplay = 1920,
1149 .hsync_start = 1920 + 154,
1150 .hsync_end = 1920 + 154 + 16,
1151 .htotal = 1920 + 154 + 16 + 32,
1152 .vdisplay = 1200,
1153 .vsync_start = 1200 + 17,
1154 .vsync_end = 1200 + 17 + 2,
1155 .vtotal = 1200 + 17 + 2 + 16,
1156 .vrefresh = 60,
1157};
1158
210fcd9d
TR		 1159static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1160 .desc = {
1161 .modes = &panasonic_vvx10f004b00_mode,
1162 .num_modes = 1,
d7a839cd 1163 .bpc = 8,
210fcd9d
TR		 1164 .size = {
1165 .width = 217,
1166 .height = 136,
1167 },
280921de 1168 },
5e4cc278
AC		 1169 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1170 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1171 .format = MIPI_DSI_FMT_RGB888,
1172 .lanes = 4,
1173};
1174
1175static const struct of_device_id dsi_of_match[] = {
1176 {
712ac1ba
AC		 1177 .compatible = "lg,ld070wx3-sl01",
1178 .data = &lg_ld070wx3_sl01
1179 }, {
499ce85a
AC		 1180 .compatible = "lg,lh500wx1-sd03",
1181 .data = &lg_lh500wx1_sd03
1182 }, {
210fcd9d
TR		 1183 .compatible = "panasonic,vvx10f004b00",
1184 .data = &panasonic_vvx10f004b00
1185 }, {
1186 /* sentinel */
1187 }
1188};
1189MODULE_DEVICE_TABLE(of, dsi_of_match);
1190
1191static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1192{
1193 const struct panel_desc_dsi *desc;
1194 const struct of_device_id *id;
1195 int err;
1196
1197 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1198 if (!id)
1199 return -ENODEV;
1200
1201 desc = id->data;
1202
1203 err = panel_simple_probe(&dsi->dev, &desc->desc);
1204 if (err < 0)
1205 return err;
1206
462658b8 1207 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1208 dsi->format = desc->format;
1209 dsi->lanes = desc->lanes;
1210
1211 return mipi_dsi_attach(dsi);
1212}
1213
1214static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1215{
1216 int err;
1217
1218 err = mipi_dsi_detach(dsi);
1219 if (err < 0)
1220 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1221
1222 return panel_simple_remove(&dsi->dev);
1223}
1224
d02fd93e
TR		 1225static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1226{
1227 panel_simple_shutdown(&dsi->dev);
1228}
1229
210fcd9d
TR		 1230static struct mipi_dsi_driver panel_simple_dsi_driver = {
1231 .driver = {
1232 .name = "panel-simple-dsi",
210fcd9d
TR		 1233 .of_match_table = dsi_of_match,
1234 },
1235 .probe = panel_simple_dsi_probe,
1236 .remove = panel_simple_dsi_remove,
d02fd93e 1237 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1238};
1239
1240static int __init panel_simple_init(void)
1241{
210fcd9d
TR		 1242 int err;
1243
1244 err = platform_driver_register(&panel_simple_platform_driver);
1245 if (err < 0)
1246 return err;
1247
1248 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1249 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1250 if (err < 0)
1251 return err;
1252 }
1253
1254 return 0;
280921de
TR		 1255}
1256module_init(panel_simple_init);
1257
1258static void __exit panel_simple_exit(void)
1259{
210fcd9d
TR		 1260 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1261 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1262
280921de
TR		 1263 platform_driver_unregister(&panel_simple_platform_driver);
1264}
1265module_exit(panel_simple_exit);
1266
1267MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1268MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1269MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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