Commit | Line | Data |
---|---|---|
280921de TR |
1 | /* |
2 | * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the | |
12 | * next paragraph) shall be included in all copies or substantial portions | |
13 | * of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/backlight.h> | |
cfdf0549 | 25 | #include <linux/gpio/consumer.h> |
280921de | 26 | #include <linux/module.h> |
280921de TR |
27 | #include <linux/of_platform.h> |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/regulator/consumer.h> | |
30 | ||
31 | #include <drm/drmP.h> | |
32 | #include <drm/drm_crtc.h> | |
210fcd9d | 33 | #include <drm/drm_mipi_dsi.h> |
280921de TR |
34 | #include <drm/drm_panel.h> |
35 | ||
a5d3e625 PZ |
36 | #include <video/display_timing.h> |
37 | #include <video/videomode.h> | |
38 | ||
280921de TR |
39 | struct panel_desc { |
40 | const struct drm_display_mode *modes; | |
41 | unsigned int num_modes; | |
a5d3e625 PZ |
42 | const struct display_timing *timings; |
43 | unsigned int num_timings; | |
280921de | 44 | |
0208d511 SM |
45 | unsigned int bpc; |
46 | ||
85533e3b UÖ |
47 | /** |
48 | * @width: width (in millimeters) of the panel's active display area | |
49 | * @height: height (in millimeters) of the panel's active display area | |
50 | */ | |
280921de TR |
51 | struct { |
52 | unsigned int width; | |
53 | unsigned int height; | |
54 | } size; | |
f673c37e AK |
55 | |
56 | /** | |
57 | * @prepare: the time (in milliseconds) that it takes for the panel to | |
58 | * become ready and start receiving video data | |
59 | * @enable: the time (in milliseconds) that it takes for the panel to | |
60 | * display the first valid frame after starting to receive | |
61 | * video data | |
62 | * @disable: the time (in milliseconds) that it takes for the panel to | |
63 | * turn the display off (no content is visible) | |
64 | * @unprepare: the time (in milliseconds) that it takes for the panel | |
65 | * to power itself down completely | |
66 | */ | |
67 | struct { | |
68 | unsigned int prepare; | |
69 | unsigned int enable; | |
70 | unsigned int disable; | |
71 | unsigned int unprepare; | |
72 | } delay; | |
795f7ab3 BB |
73 | |
74 | u32 bus_format; | |
f0aa0838 | 75 | u32 bus_flags; |
280921de TR |
76 | }; |
77 | ||
280921de TR |
78 | struct panel_simple { |
79 | struct drm_panel base; | |
613a633e | 80 | bool prepared; |
280921de TR |
81 | bool enabled; |
82 | ||
83 | const struct panel_desc *desc; | |
84 | ||
85 | struct backlight_device *backlight; | |
86 | struct regulator *supply; | |
87 | struct i2c_adapter *ddc; | |
88 | ||
cfdf0549 | 89 | struct gpio_desc *enable_gpio; |
280921de TR |
90 | }; |
91 | ||
92 | static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) | |
93 | { | |
94 | return container_of(panel, struct panel_simple, base); | |
95 | } | |
96 | ||
97 | static int panel_simple_get_fixed_modes(struct panel_simple *panel) | |
98 | { | |
99 | struct drm_connector *connector = panel->base.connector; | |
100 | struct drm_device *drm = panel->base.drm; | |
101 | struct drm_display_mode *mode; | |
102 | unsigned int i, num = 0; | |
103 | ||
104 | if (!panel->desc) | |
105 | return 0; | |
106 | ||
a5d3e625 PZ |
107 | for (i = 0; i < panel->desc->num_timings; i++) { |
108 | const struct display_timing *dt = &panel->desc->timings[i]; | |
109 | struct videomode vm; | |
110 | ||
111 | videomode_from_timing(dt, &vm); | |
112 | mode = drm_mode_create(drm); | |
113 | if (!mode) { | |
114 | dev_err(drm->dev, "failed to add mode %ux%u\n", | |
115 | dt->hactive.typ, dt->vactive.typ); | |
116 | continue; | |
117 | } | |
118 | ||
119 | drm_display_mode_from_videomode(&vm, mode); | |
120 | drm_mode_set_name(mode); | |
121 | ||
122 | drm_mode_probed_add(connector, mode); | |
123 | num++; | |
124 | } | |
125 | ||
280921de TR |
126 | for (i = 0; i < panel->desc->num_modes; i++) { |
127 | const struct drm_display_mode *m = &panel->desc->modes[i]; | |
128 | ||
129 | mode = drm_mode_duplicate(drm, m); | |
130 | if (!mode) { | |
131 | dev_err(drm->dev, "failed to add mode %ux%u@%u\n", | |
132 | m->hdisplay, m->vdisplay, m->vrefresh); | |
133 | continue; | |
134 | } | |
135 | ||
136 | drm_mode_set_name(mode); | |
137 | ||
138 | drm_mode_probed_add(connector, mode); | |
139 | num++; | |
140 | } | |
141 | ||
0208d511 | 142 | connector->display_info.bpc = panel->desc->bpc; |
280921de TR |
143 | connector->display_info.width_mm = panel->desc->size.width; |
144 | connector->display_info.height_mm = panel->desc->size.height; | |
795f7ab3 BB |
145 | if (panel->desc->bus_format) |
146 | drm_display_info_set_bus_formats(&connector->display_info, | |
147 | &panel->desc->bus_format, 1); | |
f0aa0838 | 148 | connector->display_info.bus_flags = panel->desc->bus_flags; |
280921de TR |
149 | |
150 | return num; | |
151 | } | |
152 | ||
153 | static int panel_simple_disable(struct drm_panel *panel) | |
154 | { | |
155 | struct panel_simple *p = to_panel_simple(panel); | |
156 | ||
157 | if (!p->enabled) | |
158 | return 0; | |
159 | ||
160 | if (p->backlight) { | |
161 | p->backlight->props.power = FB_BLANK_POWERDOWN; | |
162 | backlight_update_status(p->backlight); | |
163 | } | |
164 | ||
f673c37e AK |
165 | if (p->desc->delay.disable) |
166 | msleep(p->desc->delay.disable); | |
167 | ||
280921de TR |
168 | p->enabled = false; |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
c0e1d170 AK |
173 | static int panel_simple_unprepare(struct drm_panel *panel) |
174 | { | |
613a633e AK |
175 | struct panel_simple *p = to_panel_simple(panel); |
176 | ||
177 | if (!p->prepared) | |
178 | return 0; | |
179 | ||
180 | if (p->enable_gpio) | |
181 | gpiod_set_value_cansleep(p->enable_gpio, 0); | |
182 | ||
183 | regulator_disable(p->supply); | |
184 | ||
f673c37e AK |
185 | if (p->desc->delay.unprepare) |
186 | msleep(p->desc->delay.unprepare); | |
187 | ||
613a633e | 188 | p->prepared = false; |
c0e1d170 | 189 | |
c0e1d170 AK |
190 | return 0; |
191 | } | |
192 | ||
613a633e | 193 | static int panel_simple_prepare(struct drm_panel *panel) |
280921de TR |
194 | { |
195 | struct panel_simple *p = to_panel_simple(panel); | |
196 | int err; | |
197 | ||
613a633e | 198 | if (p->prepared) |
280921de TR |
199 | return 0; |
200 | ||
201 | err = regulator_enable(p->supply); | |
202 | if (err < 0) { | |
203 | dev_err(panel->dev, "failed to enable supply: %d\n", err); | |
204 | return err; | |
205 | } | |
206 | ||
cfdf0549 | 207 | if (p->enable_gpio) |
15c1a919 | 208 | gpiod_set_value_cansleep(p->enable_gpio, 1); |
280921de | 209 | |
f673c37e AK |
210 | if (p->desc->delay.prepare) |
211 | msleep(p->desc->delay.prepare); | |
212 | ||
613a633e AK |
213 | p->prepared = true; |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | static int panel_simple_enable(struct drm_panel *panel) | |
219 | { | |
220 | struct panel_simple *p = to_panel_simple(panel); | |
221 | ||
222 | if (p->enabled) | |
223 | return 0; | |
224 | ||
f673c37e AK |
225 | if (p->desc->delay.enable) |
226 | msleep(p->desc->delay.enable); | |
227 | ||
280921de TR |
228 | if (p->backlight) { |
229 | p->backlight->props.power = FB_BLANK_UNBLANK; | |
230 | backlight_update_status(p->backlight); | |
231 | } | |
232 | ||
233 | p->enabled = true; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static int panel_simple_get_modes(struct drm_panel *panel) | |
239 | { | |
240 | struct panel_simple *p = to_panel_simple(panel); | |
241 | int num = 0; | |
242 | ||
243 | /* probe EDID if a DDC bus is available */ | |
244 | if (p->ddc) { | |
245 | struct edid *edid = drm_get_edid(panel->connector, p->ddc); | |
70bf6878 | 246 | drm_mode_connector_update_edid_property(panel->connector, edid); |
280921de TR |
247 | if (edid) { |
248 | num += drm_add_edid_modes(panel->connector, edid); | |
249 | kfree(edid); | |
250 | } | |
251 | } | |
252 | ||
253 | /* add hard-coded panel modes */ | |
254 | num += panel_simple_get_fixed_modes(p); | |
255 | ||
256 | return num; | |
257 | } | |
258 | ||
a5d3e625 PZ |
259 | static int panel_simple_get_timings(struct drm_panel *panel, |
260 | unsigned int num_timings, | |
261 | struct display_timing *timings) | |
262 | { | |
263 | struct panel_simple *p = to_panel_simple(panel); | |
264 | unsigned int i; | |
265 | ||
266 | if (p->desc->num_timings < num_timings) | |
267 | num_timings = p->desc->num_timings; | |
268 | ||
269 | if (timings) | |
270 | for (i = 0; i < num_timings; i++) | |
271 | timings[i] = p->desc->timings[i]; | |
272 | ||
273 | return p->desc->num_timings; | |
274 | } | |
275 | ||
280921de TR |
276 | static const struct drm_panel_funcs panel_simple_funcs = { |
277 | .disable = panel_simple_disable, | |
c0e1d170 AK |
278 | .unprepare = panel_simple_unprepare, |
279 | .prepare = panel_simple_prepare, | |
280921de TR |
280 | .enable = panel_simple_enable, |
281 | .get_modes = panel_simple_get_modes, | |
a5d3e625 | 282 | .get_timings = panel_simple_get_timings, |
280921de TR |
283 | }; |
284 | ||
285 | static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) | |
286 | { | |
287 | struct device_node *backlight, *ddc; | |
288 | struct panel_simple *panel; | |
280921de TR |
289 | int err; |
290 | ||
291 | panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); | |
292 | if (!panel) | |
293 | return -ENOMEM; | |
294 | ||
295 | panel->enabled = false; | |
613a633e | 296 | panel->prepared = false; |
280921de TR |
297 | panel->desc = desc; |
298 | ||
299 | panel->supply = devm_regulator_get(dev, "power"); | |
300 | if (IS_ERR(panel->supply)) | |
301 | return PTR_ERR(panel->supply); | |
302 | ||
a61400d8 AC |
303 | panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", |
304 | GPIOD_OUT_LOW); | |
cfdf0549 AC |
305 | if (IS_ERR(panel->enable_gpio)) { |
306 | err = PTR_ERR(panel->enable_gpio); | |
9746c619 AC |
307 | dev_err(dev, "failed to request GPIO: %d\n", err); |
308 | return err; | |
309 | } | |
280921de | 310 | |
280921de TR |
311 | backlight = of_parse_phandle(dev->of_node, "backlight", 0); |
312 | if (backlight) { | |
313 | panel->backlight = of_find_backlight_by_node(backlight); | |
314 | of_node_put(backlight); | |
315 | ||
cfdf0549 AC |
316 | if (!panel->backlight) |
317 | return -EPROBE_DEFER; | |
280921de TR |
318 | } |
319 | ||
320 | ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); | |
321 | if (ddc) { | |
322 | panel->ddc = of_find_i2c_adapter_by_node(ddc); | |
323 | of_node_put(ddc); | |
324 | ||
325 | if (!panel->ddc) { | |
326 | err = -EPROBE_DEFER; | |
327 | goto free_backlight; | |
328 | } | |
329 | } | |
330 | ||
331 | drm_panel_init(&panel->base); | |
332 | panel->base.dev = dev; | |
333 | panel->base.funcs = &panel_simple_funcs; | |
334 | ||
335 | err = drm_panel_add(&panel->base); | |
336 | if (err < 0) | |
337 | goto free_ddc; | |
338 | ||
339 | dev_set_drvdata(dev, panel); | |
340 | ||
341 | return 0; | |
342 | ||
343 | free_ddc: | |
344 | if (panel->ddc) | |
345 | put_device(&panel->ddc->dev); | |
346 | free_backlight: | |
347 | if (panel->backlight) | |
348 | put_device(&panel->backlight->dev); | |
280921de TR |
349 | |
350 | return err; | |
351 | } | |
352 | ||
353 | static int panel_simple_remove(struct device *dev) | |
354 | { | |
355 | struct panel_simple *panel = dev_get_drvdata(dev); | |
356 | ||
357 | drm_panel_detach(&panel->base); | |
358 | drm_panel_remove(&panel->base); | |
359 | ||
360 | panel_simple_disable(&panel->base); | |
361 | ||
362 | if (panel->ddc) | |
363 | put_device(&panel->ddc->dev); | |
364 | ||
365 | if (panel->backlight) | |
366 | put_device(&panel->backlight->dev); | |
367 | ||
280921de TR |
368 | return 0; |
369 | } | |
370 | ||
d02fd93e TR |
371 | static void panel_simple_shutdown(struct device *dev) |
372 | { | |
373 | struct panel_simple *panel = dev_get_drvdata(dev); | |
374 | ||
375 | panel_simple_disable(&panel->base); | |
376 | } | |
377 | ||
1c550fa1 PZ |
378 | static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { |
379 | .clock = 33333, | |
380 | .hdisplay = 800, | |
381 | .hsync_start = 800 + 0, | |
382 | .hsync_end = 800 + 0 + 255, | |
383 | .htotal = 800 + 0 + 255 + 0, | |
384 | .vdisplay = 480, | |
385 | .vsync_start = 480 + 2, | |
386 | .vsync_end = 480 + 2 + 45, | |
387 | .vtotal = 480 + 2 + 45 + 0, | |
388 | .vrefresh = 60, | |
389 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, | |
390 | }; | |
391 | ||
392 | static const struct panel_desc ampire_am800480r3tmqwa1h = { | |
393 | .modes = &ire_am800480r3tmqwa1h_mode, | |
394 | .num_modes = 1, | |
395 | .bpc = 6, | |
396 | .size = { | |
397 | .width = 152, | |
398 | .height = 91, | |
399 | }, | |
400 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
401 | }; | |
402 | ||
280921de TR |
403 | static const struct drm_display_mode auo_b101aw03_mode = { |
404 | .clock = 51450, | |
405 | .hdisplay = 1024, | |
406 | .hsync_start = 1024 + 156, | |
407 | .hsync_end = 1024 + 156 + 8, | |
408 | .htotal = 1024 + 156 + 8 + 156, | |
409 | .vdisplay = 600, | |
410 | .vsync_start = 600 + 16, | |
411 | .vsync_end = 600 + 16 + 6, | |
412 | .vtotal = 600 + 16 + 6 + 16, | |
413 | .vrefresh = 60, | |
414 | }; | |
415 | ||
416 | static const struct panel_desc auo_b101aw03 = { | |
417 | .modes = &auo_b101aw03_mode, | |
418 | .num_modes = 1, | |
0208d511 | 419 | .bpc = 6, |
280921de TR |
420 | .size = { |
421 | .width = 223, | |
422 | .height = 125, | |
423 | }, | |
424 | }; | |
425 | ||
a531bc3d HL |
426 | static const struct drm_display_mode auo_b101ean01_mode = { |
427 | .clock = 72500, | |
428 | .hdisplay = 1280, | |
429 | .hsync_start = 1280 + 119, | |
430 | .hsync_end = 1280 + 119 + 32, | |
431 | .htotal = 1280 + 119 + 32 + 21, | |
432 | .vdisplay = 800, | |
433 | .vsync_start = 800 + 4, | |
434 | .vsync_end = 800 + 4 + 20, | |
435 | .vtotal = 800 + 4 + 20 + 8, | |
436 | .vrefresh = 60, | |
437 | }; | |
438 | ||
439 | static const struct panel_desc auo_b101ean01 = { | |
440 | .modes = &auo_b101ean01_mode, | |
441 | .num_modes = 1, | |
442 | .bpc = 6, | |
443 | .size = { | |
444 | .width = 217, | |
445 | .height = 136, | |
446 | }, | |
447 | }; | |
448 | ||
dac746e0 RC |
449 | static const struct drm_display_mode auo_b101xtn01_mode = { |
450 | .clock = 72000, | |
451 | .hdisplay = 1366, | |
452 | .hsync_start = 1366 + 20, | |
453 | .hsync_end = 1366 + 20 + 70, | |
454 | .htotal = 1366 + 20 + 70, | |
455 | .vdisplay = 768, | |
456 | .vsync_start = 768 + 14, | |
457 | .vsync_end = 768 + 14 + 42, | |
458 | .vtotal = 768 + 14 + 42, | |
459 | .vrefresh = 60, | |
460 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
461 | }; | |
462 | ||
463 | static const struct panel_desc auo_b101xtn01 = { | |
464 | .modes = &auo_b101xtn01_mode, | |
465 | .num_modes = 1, | |
466 | .bpc = 6, | |
467 | .size = { | |
468 | .width = 223, | |
469 | .height = 125, | |
470 | }, | |
471 | }; | |
472 | ||
e35e305e AK |
473 | static const struct drm_display_mode auo_b116xw03_mode = { |
474 | .clock = 70589, | |
475 | .hdisplay = 1366, | |
476 | .hsync_start = 1366 + 40, | |
477 | .hsync_end = 1366 + 40 + 40, | |
478 | .htotal = 1366 + 40 + 40 + 32, | |
479 | .vdisplay = 768, | |
480 | .vsync_start = 768 + 10, | |
481 | .vsync_end = 768 + 10 + 12, | |
482 | .vtotal = 768 + 10 + 12 + 6, | |
483 | .vrefresh = 60, | |
484 | }; | |
485 | ||
486 | static const struct panel_desc auo_b116xw03 = { | |
487 | .modes = &auo_b116xw03_mode, | |
488 | .num_modes = 1, | |
489 | .bpc = 6, | |
490 | .size = { | |
491 | .width = 256, | |
492 | .height = 144, | |
493 | }, | |
494 | }; | |
495 | ||
a333f7ad SM |
496 | static const struct drm_display_mode auo_b133xtn01_mode = { |
497 | .clock = 69500, | |
498 | .hdisplay = 1366, | |
499 | .hsync_start = 1366 + 48, | |
500 | .hsync_end = 1366 + 48 + 32, | |
501 | .htotal = 1366 + 48 + 32 + 20, | |
502 | .vdisplay = 768, | |
503 | .vsync_start = 768 + 3, | |
504 | .vsync_end = 768 + 3 + 6, | |
505 | .vtotal = 768 + 3 + 6 + 13, | |
506 | .vrefresh = 60, | |
507 | }; | |
508 | ||
509 | static const struct panel_desc auo_b133xtn01 = { | |
510 | .modes = &auo_b133xtn01_mode, | |
511 | .num_modes = 1, | |
0208d511 | 512 | .bpc = 6, |
a333f7ad SM |
513 | .size = { |
514 | .width = 293, | |
515 | .height = 165, | |
516 | }, | |
517 | }; | |
518 | ||
3e51d609 AK |
519 | static const struct drm_display_mode auo_b133htn01_mode = { |
520 | .clock = 150660, | |
521 | .hdisplay = 1920, | |
522 | .hsync_start = 1920 + 172, | |
523 | .hsync_end = 1920 + 172 + 80, | |
524 | .htotal = 1920 + 172 + 80 + 60, | |
525 | .vdisplay = 1080, | |
526 | .vsync_start = 1080 + 25, | |
527 | .vsync_end = 1080 + 25 + 10, | |
528 | .vtotal = 1080 + 25 + 10 + 10, | |
529 | .vrefresh = 60, | |
530 | }; | |
531 | ||
532 | static const struct panel_desc auo_b133htn01 = { | |
533 | .modes = &auo_b133htn01_mode, | |
534 | .num_modes = 1, | |
d7a839cd | 535 | .bpc = 6, |
3e51d609 AK |
536 | .size = { |
537 | .width = 293, | |
538 | .height = 165, | |
539 | }, | |
540 | .delay = { | |
541 | .prepare = 105, | |
542 | .enable = 20, | |
543 | .unprepare = 50, | |
544 | }, | |
545 | }; | |
546 | ||
d47df633 PZ |
547 | static const struct drm_display_mode avic_tm070ddh03_mode = { |
548 | .clock = 51200, | |
549 | .hdisplay = 1024, | |
550 | .hsync_start = 1024 + 160, | |
551 | .hsync_end = 1024 + 160 + 4, | |
552 | .htotal = 1024 + 160 + 4 + 156, | |
553 | .vdisplay = 600, | |
554 | .vsync_start = 600 + 17, | |
555 | .vsync_end = 600 + 17 + 1, | |
556 | .vtotal = 600 + 17 + 1 + 17, | |
557 | .vrefresh = 60, | |
558 | }; | |
559 | ||
560 | static const struct panel_desc avic_tm070ddh03 = { | |
561 | .modes = &avic_tm070ddh03_mode, | |
562 | .num_modes = 1, | |
563 | .bpc = 8, | |
564 | .size = { | |
565 | .width = 154, | |
566 | .height = 90, | |
567 | }, | |
568 | .delay = { | |
569 | .prepare = 20, | |
570 | .enable = 200, | |
571 | .disable = 200, | |
572 | }, | |
573 | }; | |
574 | ||
4c930757 SW |
575 | static const struct drm_display_mode chunghwa_claa101wa01a_mode = { |
576 | .clock = 72070, | |
577 | .hdisplay = 1366, | |
578 | .hsync_start = 1366 + 58, | |
579 | .hsync_end = 1366 + 58 + 58, | |
580 | .htotal = 1366 + 58 + 58 + 58, | |
581 | .vdisplay = 768, | |
582 | .vsync_start = 768 + 4, | |
583 | .vsync_end = 768 + 4 + 4, | |
584 | .vtotal = 768 + 4 + 4 + 4, | |
585 | .vrefresh = 60, | |
586 | }; | |
587 | ||
588 | static const struct panel_desc chunghwa_claa101wa01a = { | |
589 | .modes = &chunghwa_claa101wa01a_mode, | |
590 | .num_modes = 1, | |
0208d511 | 591 | .bpc = 6, |
4c930757 SW |
592 | .size = { |
593 | .width = 220, | |
594 | .height = 120, | |
595 | }, | |
596 | }; | |
597 | ||
280921de TR |
598 | static const struct drm_display_mode chunghwa_claa101wb01_mode = { |
599 | .clock = 69300, | |
600 | .hdisplay = 1366, | |
601 | .hsync_start = 1366 + 48, | |
602 | .hsync_end = 1366 + 48 + 32, | |
603 | .htotal = 1366 + 48 + 32 + 20, | |
604 | .vdisplay = 768, | |
605 | .vsync_start = 768 + 16, | |
606 | .vsync_end = 768 + 16 + 8, | |
607 | .vtotal = 768 + 16 + 8 + 16, | |
608 | .vrefresh = 60, | |
609 | }; | |
610 | ||
611 | static const struct panel_desc chunghwa_claa101wb01 = { | |
612 | .modes = &chunghwa_claa101wb01_mode, | |
613 | .num_modes = 1, | |
0208d511 | 614 | .bpc = 6, |
280921de TR |
615 | .size = { |
616 | .width = 223, | |
617 | .height = 125, | |
618 | }, | |
619 | }; | |
620 | ||
26ab0065 SA |
621 | static const struct drm_display_mode edt_et057090dhu_mode = { |
622 | .clock = 25175, | |
623 | .hdisplay = 640, | |
624 | .hsync_start = 640 + 16, | |
625 | .hsync_end = 640 + 16 + 30, | |
626 | .htotal = 640 + 16 + 30 + 114, | |
627 | .vdisplay = 480, | |
628 | .vsync_start = 480 + 10, | |
629 | .vsync_end = 480 + 10 + 3, | |
630 | .vtotal = 480 + 10 + 3 + 32, | |
631 | .vrefresh = 60, | |
632 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
633 | }; | |
634 | ||
635 | static const struct panel_desc edt_et057090dhu = { | |
636 | .modes = &edt_et057090dhu_mode, | |
637 | .num_modes = 1, | |
0208d511 | 638 | .bpc = 6, |
26ab0065 SA |
639 | .size = { |
640 | .width = 115, | |
641 | .height = 86, | |
642 | }, | |
643 | }; | |
644 | ||
fff5de45 PZ |
645 | static const struct drm_display_mode edt_etm0700g0dh6_mode = { |
646 | .clock = 33260, | |
647 | .hdisplay = 800, | |
648 | .hsync_start = 800 + 40, | |
649 | .hsync_end = 800 + 40 + 128, | |
650 | .htotal = 800 + 40 + 128 + 88, | |
651 | .vdisplay = 480, | |
652 | .vsync_start = 480 + 10, | |
653 | .vsync_end = 480 + 10 + 2, | |
654 | .vtotal = 480 + 10 + 2 + 33, | |
655 | .vrefresh = 60, | |
656 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
657 | }; | |
658 | ||
659 | static const struct panel_desc edt_etm0700g0dh6 = { | |
660 | .modes = &edt_etm0700g0dh6_mode, | |
661 | .num_modes = 1, | |
0208d511 | 662 | .bpc = 6, |
fff5de45 PZ |
663 | .size = { |
664 | .width = 152, | |
665 | .height = 91, | |
666 | }, | |
667 | }; | |
668 | ||
102932b0 BB |
669 | static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { |
670 | .clock = 32260, | |
671 | .hdisplay = 800, | |
672 | .hsync_start = 800 + 168, | |
673 | .hsync_end = 800 + 168 + 64, | |
674 | .htotal = 800 + 168 + 64 + 88, | |
675 | .vdisplay = 480, | |
676 | .vsync_start = 480 + 37, | |
677 | .vsync_end = 480 + 37 + 2, | |
678 | .vtotal = 480 + 37 + 2 + 8, | |
679 | .vrefresh = 60, | |
680 | }; | |
681 | ||
682 | static const struct panel_desc foxlink_fl500wvr00_a0t = { | |
683 | .modes = &foxlink_fl500wvr00_a0t_mode, | |
684 | .num_modes = 1, | |
d7a839cd | 685 | .bpc = 8, |
102932b0 BB |
686 | .size = { |
687 | .width = 108, | |
688 | .height = 65, | |
689 | }, | |
bb276cb3 | 690 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
102932b0 BB |
691 | }; |
692 | ||
d435a2af PZ |
693 | static const struct drm_display_mode giantplus_gpg482739qs5_mode = { |
694 | .clock = 9000, | |
695 | .hdisplay = 480, | |
696 | .hsync_start = 480 + 5, | |
697 | .hsync_end = 480 + 5 + 1, | |
698 | .htotal = 480 + 5 + 1 + 40, | |
699 | .vdisplay = 272, | |
700 | .vsync_start = 272 + 8, | |
701 | .vsync_end = 272 + 8 + 1, | |
702 | .vtotal = 272 + 8 + 1 + 8, | |
703 | .vrefresh = 60, | |
704 | }; | |
705 | ||
706 | static const struct panel_desc giantplus_gpg482739qs5 = { | |
707 | .modes = &giantplus_gpg482739qs5_mode, | |
708 | .num_modes = 1, | |
709 | .bpc = 8, | |
710 | .size = { | |
711 | .width = 95, | |
712 | .height = 54, | |
713 | }, | |
33536a09 | 714 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
d435a2af PZ |
715 | }; |
716 | ||
ab07725a PZ |
717 | static const struct display_timing hannstar_hsd070pww1_timing = { |
718 | .pixelclock = { 64300000, 71100000, 82000000 }, | |
719 | .hactive = { 1280, 1280, 1280 }, | |
720 | .hfront_porch = { 1, 1, 10 }, | |
721 | .hback_porch = { 1, 1, 10 }, | |
d901d2ba PZ |
722 | /* |
723 | * According to the data sheet, the minimum horizontal blanking interval | |
724 | * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the | |
725 | * minimum working horizontal blanking interval to be 60 clocks. | |
726 | */ | |
727 | .hsync_len = { 58, 158, 661 }, | |
ab07725a PZ |
728 | .vactive = { 800, 800, 800 }, |
729 | .vfront_porch = { 1, 1, 10 }, | |
730 | .vback_porch = { 1, 1, 10 }, | |
731 | .vsync_len = { 1, 21, 203 }, | |
732 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
a853205e PZ |
733 | }; |
734 | ||
735 | static const struct panel_desc hannstar_hsd070pww1 = { | |
ab07725a PZ |
736 | .timings = &hannstar_hsd070pww1_timing, |
737 | .num_timings = 1, | |
a853205e PZ |
738 | .bpc = 6, |
739 | .size = { | |
740 | .width = 151, | |
741 | .height = 94, | |
742 | }, | |
58d6a7bc | 743 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
a853205e PZ |
744 | }; |
745 | ||
c0d607e5 EN |
746 | static const struct display_timing hannstar_hsd100pxn1_timing = { |
747 | .pixelclock = { 55000000, 65000000, 75000000 }, | |
748 | .hactive = { 1024, 1024, 1024 }, | |
749 | .hfront_porch = { 40, 40, 40 }, | |
750 | .hback_porch = { 220, 220, 220 }, | |
751 | .hsync_len = { 20, 60, 100 }, | |
752 | .vactive = { 768, 768, 768 }, | |
753 | .vfront_porch = { 7, 7, 7 }, | |
754 | .vback_porch = { 21, 21, 21 }, | |
755 | .vsync_len = { 10, 10, 10 }, | |
756 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
757 | }; | |
758 | ||
759 | static const struct panel_desc hannstar_hsd100pxn1 = { | |
760 | .timings = &hannstar_hsd100pxn1_timing, | |
761 | .num_timings = 1, | |
762 | .bpc = 6, | |
763 | .size = { | |
764 | .width = 203, | |
765 | .height = 152, | |
766 | }, | |
4946b043 | 767 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c0d607e5 EN |
768 | }; |
769 | ||
61ac0bf8 LS |
770 | static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { |
771 | .clock = 33333, | |
772 | .hdisplay = 800, | |
773 | .hsync_start = 800 + 85, | |
774 | .hsync_end = 800 + 85 + 86, | |
775 | .htotal = 800 + 85 + 86 + 85, | |
776 | .vdisplay = 480, | |
777 | .vsync_start = 480 + 16, | |
778 | .vsync_end = 480 + 16 + 13, | |
779 | .vtotal = 480 + 16 + 13 + 16, | |
780 | .vrefresh = 60, | |
781 | }; | |
782 | ||
783 | static const struct panel_desc hitachi_tx23d38vm0caa = { | |
784 | .modes = &hitachi_tx23d38vm0caa_mode, | |
785 | .num_modes = 1, | |
786 | .bpc = 6, | |
787 | .size = { | |
788 | .width = 195, | |
789 | .height = 117, | |
790 | }, | |
791 | }; | |
792 | ||
41bcceb4 NF |
793 | static const struct drm_display_mode innolux_at043tn24_mode = { |
794 | .clock = 9000, | |
795 | .hdisplay = 480, | |
796 | .hsync_start = 480 + 2, | |
797 | .hsync_end = 480 + 2 + 41, | |
798 | .htotal = 480 + 2 + 41 + 2, | |
799 | .vdisplay = 272, | |
800 | .vsync_start = 272 + 2, | |
801 | .vsync_end = 272 + 2 + 11, | |
802 | .vtotal = 272 + 2 + 11 + 2, | |
803 | .vrefresh = 60, | |
804 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
805 | }; | |
806 | ||
807 | static const struct panel_desc innolux_at043tn24 = { | |
808 | .modes = &innolux_at043tn24_mode, | |
809 | .num_modes = 1, | |
810 | .bpc = 8, | |
811 | .size = { | |
812 | .width = 95, | |
813 | .height = 54, | |
814 | }, | |
815 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
816 | }; | |
817 | ||
d731f661 | 818 | static const struct drm_display_mode innolux_g121i1_l01_mode = { |
0a2288c0 | 819 | .clock = 71000, |
d731f661 LS |
820 | .hdisplay = 1280, |
821 | .hsync_start = 1280 + 64, | |
822 | .hsync_end = 1280 + 64 + 32, | |
823 | .htotal = 1280 + 64 + 32 + 64, | |
824 | .vdisplay = 800, | |
825 | .vsync_start = 800 + 9, | |
826 | .vsync_end = 800 + 9 + 6, | |
827 | .vtotal = 800 + 9 + 6 + 9, | |
828 | .vrefresh = 60, | |
829 | }; | |
830 | ||
831 | static const struct panel_desc innolux_g121i1_l01 = { | |
832 | .modes = &innolux_g121i1_l01_mode, | |
833 | .num_modes = 1, | |
834 | .bpc = 6, | |
835 | .size = { | |
836 | .width = 261, | |
837 | .height = 163, | |
838 | }, | |
839 | }; | |
840 | ||
f8fa17ba AB |
841 | static const struct drm_display_mode innolux_g121x1_l03_mode = { |
842 | .clock = 65000, | |
843 | .hdisplay = 1024, | |
844 | .hsync_start = 1024 + 0, | |
845 | .hsync_end = 1024 + 1, | |
846 | .htotal = 1024 + 0 + 1 + 320, | |
847 | .vdisplay = 768, | |
848 | .vsync_start = 768 + 38, | |
849 | .vsync_end = 768 + 38 + 1, | |
850 | .vtotal = 768 + 38 + 1 + 0, | |
851 | .vrefresh = 60, | |
2e8c5eb9 | 852 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
f8fa17ba AB |
853 | }; |
854 | ||
855 | static const struct panel_desc innolux_g121x1_l03 = { | |
856 | .modes = &innolux_g121x1_l03_mode, | |
857 | .num_modes = 1, | |
858 | .bpc = 6, | |
859 | .size = { | |
860 | .width = 246, | |
861 | .height = 185, | |
862 | }, | |
863 | .delay = { | |
864 | .enable = 200, | |
865 | .unprepare = 200, | |
866 | .disable = 400, | |
867 | }, | |
868 | }; | |
869 | ||
0a2288c0 | 870 | static const struct drm_display_mode innolux_n116bge_mode = { |
7fe8c777 | 871 | .clock = 76420, |
0a2288c0 | 872 | .hdisplay = 1366, |
7fe8c777 DK |
873 | .hsync_start = 1366 + 136, |
874 | .hsync_end = 1366 + 136 + 30, | |
875 | .htotal = 1366 + 136 + 30 + 60, | |
0a2288c0 TR |
876 | .vdisplay = 768, |
877 | .vsync_start = 768 + 8, | |
7fe8c777 DK |
878 | .vsync_end = 768 + 8 + 12, |
879 | .vtotal = 768 + 8 + 12 + 12, | |
0a2288c0 TR |
880 | .vrefresh = 60, |
881 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
882 | }; | |
883 | ||
884 | static const struct panel_desc innolux_n116bge = { | |
885 | .modes = &innolux_n116bge_mode, | |
886 | .num_modes = 1, | |
887 | .bpc = 6, | |
888 | .size = { | |
889 | .width = 256, | |
890 | .height = 144, | |
891 | }, | |
892 | }; | |
893 | ||
ea44739d AB |
894 | static const struct drm_display_mode innolux_n156bge_l21_mode = { |
895 | .clock = 69300, | |
896 | .hdisplay = 1366, | |
897 | .hsync_start = 1366 + 16, | |
898 | .hsync_end = 1366 + 16 + 34, | |
899 | .htotal = 1366 + 16 + 34 + 50, | |
900 | .vdisplay = 768, | |
901 | .vsync_start = 768 + 2, | |
902 | .vsync_end = 768 + 2 + 6, | |
903 | .vtotal = 768 + 2 + 6 + 12, | |
904 | .vrefresh = 60, | |
905 | }; | |
906 | ||
907 | static const struct panel_desc innolux_n156bge_l21 = { | |
908 | .modes = &innolux_n156bge_l21_mode, | |
909 | .num_modes = 1, | |
0208d511 | 910 | .bpc = 6, |
ea44739d AB |
911 | .size = { |
912 | .width = 344, | |
913 | .height = 193, | |
914 | }, | |
915 | }; | |
916 | ||
bccac3f1 MG |
917 | static const struct drm_display_mode innolux_zj070na_01p_mode = { |
918 | .clock = 51501, | |
919 | .hdisplay = 1024, | |
920 | .hsync_start = 1024 + 128, | |
921 | .hsync_end = 1024 + 128 + 64, | |
922 | .htotal = 1024 + 128 + 64 + 128, | |
923 | .vdisplay = 600, | |
924 | .vsync_start = 600 + 16, | |
925 | .vsync_end = 600 + 16 + 4, | |
926 | .vtotal = 600 + 16 + 4 + 16, | |
927 | .vrefresh = 60, | |
928 | }; | |
929 | ||
930 | static const struct panel_desc innolux_zj070na_01p = { | |
931 | .modes = &innolux_zj070na_01p_mode, | |
932 | .num_modes = 1, | |
933 | .bpc = 6, | |
934 | .size = { | |
935 | .width = 1024, | |
936 | .height = 600, | |
937 | }, | |
938 | }; | |
939 | ||
8def22e5 LS |
940 | static const struct display_timing kyo_tcg121xglp_timing = { |
941 | .pixelclock = { 52000000, 65000000, 71000000 }, | |
942 | .hactive = { 1024, 1024, 1024 }, | |
943 | .hfront_porch = { 2, 2, 2 }, | |
944 | .hback_porch = { 2, 2, 2 }, | |
945 | .hsync_len = { 86, 124, 244 }, | |
946 | .vactive = { 768, 768, 768 }, | |
947 | .vfront_porch = { 2, 2, 2 }, | |
948 | .vback_porch = { 2, 2, 2 }, | |
949 | .vsync_len = { 6, 34, 73 }, | |
950 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
951 | }; | |
952 | ||
953 | static const struct panel_desc kyo_tcg121xglp = { | |
954 | .timings = &kyo_tcg121xglp_timing, | |
955 | .num_timings = 1, | |
956 | .bpc = 8, | |
957 | .size = { | |
958 | .width = 246, | |
959 | .height = 184, | |
960 | }, | |
961 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
962 | }; | |
963 | ||
dd015002 HS |
964 | static const struct drm_display_mode lg_lb070wv8_mode = { |
965 | .clock = 33246, | |
966 | .hdisplay = 800, | |
967 | .hsync_start = 800 + 88, | |
968 | .hsync_end = 800 + 88 + 80, | |
969 | .htotal = 800 + 88 + 80 + 88, | |
970 | .vdisplay = 480, | |
971 | .vsync_start = 480 + 10, | |
972 | .vsync_end = 480 + 10 + 25, | |
973 | .vtotal = 480 + 10 + 25 + 10, | |
974 | .vrefresh = 60, | |
975 | }; | |
976 | ||
977 | static const struct panel_desc lg_lb070wv8 = { | |
978 | .modes = &lg_lb070wv8_mode, | |
979 | .num_modes = 1, | |
980 | .bpc = 16, | |
981 | .size = { | |
982 | .width = 151, | |
983 | .height = 91, | |
984 | }, | |
985 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
986 | }; | |
987 | ||
690d8fa7 JS |
988 | static const struct drm_display_mode lg_lp120up1_mode = { |
989 | .clock = 162300, | |
990 | .hdisplay = 1920, | |
991 | .hsync_start = 1920 + 40, | |
992 | .hsync_end = 1920 + 40 + 40, | |
993 | .htotal = 1920 + 40 + 40+ 80, | |
994 | .vdisplay = 1280, | |
995 | .vsync_start = 1280 + 4, | |
996 | .vsync_end = 1280 + 4 + 4, | |
997 | .vtotal = 1280 + 4 + 4 + 12, | |
998 | .vrefresh = 60, | |
999 | }; | |
1000 | ||
1001 | static const struct panel_desc lg_lp120up1 = { | |
1002 | .modes = &lg_lp120up1_mode, | |
1003 | .num_modes = 1, | |
1004 | .bpc = 8, | |
1005 | .size = { | |
1006 | .width = 267, | |
1007 | .height = 183, | |
1008 | }, | |
1009 | }; | |
1010 | ||
ec7c5653 TR |
1011 | static const struct drm_display_mode lg_lp129qe_mode = { |
1012 | .clock = 285250, | |
1013 | .hdisplay = 2560, | |
1014 | .hsync_start = 2560 + 48, | |
1015 | .hsync_end = 2560 + 48 + 32, | |
1016 | .htotal = 2560 + 48 + 32 + 80, | |
1017 | .vdisplay = 1700, | |
1018 | .vsync_start = 1700 + 3, | |
1019 | .vsync_end = 1700 + 3 + 10, | |
1020 | .vtotal = 1700 + 3 + 10 + 36, | |
1021 | .vrefresh = 60, | |
1022 | }; | |
1023 | ||
1024 | static const struct panel_desc lg_lp129qe = { | |
1025 | .modes = &lg_lp129qe_mode, | |
1026 | .num_modes = 1, | |
0208d511 | 1027 | .bpc = 8, |
ec7c5653 TR |
1028 | .size = { |
1029 | .width = 272, | |
1030 | .height = 181, | |
1031 | }, | |
1032 | }; | |
1033 | ||
c6e87f91 | 1034 | static const struct drm_display_mode nec_nl4827hc19_05b_mode = { |
1035 | .clock = 10870, | |
1036 | .hdisplay = 480, | |
1037 | .hsync_start = 480 + 2, | |
1038 | .hsync_end = 480 + 2 + 41, | |
1039 | .htotal = 480 + 2 + 41 + 2, | |
1040 | .vdisplay = 272, | |
1041 | .vsync_start = 272 + 2, | |
1042 | .vsync_end = 272 + 2 + 4, | |
1043 | .vtotal = 272 + 2 + 4 + 2, | |
1044 | .vrefresh = 74, | |
4bc390c6 | 1045 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
c6e87f91 | 1046 | }; |
1047 | ||
1048 | static const struct panel_desc nec_nl4827hc19_05b = { | |
1049 | .modes = &nec_nl4827hc19_05b_mode, | |
1050 | .num_modes = 1, | |
1051 | .bpc = 8, | |
1052 | .size = { | |
1053 | .width = 95, | |
1054 | .height = 54, | |
1055 | }, | |
2c80661d SA |
1056 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
1057 | .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, | |
c6e87f91 | 1058 | }; |
1059 | ||
a99fb626 GB |
1060 | static const struct display_timing okaya_rs800480t_7x0gp_timing = { |
1061 | .pixelclock = { 30000000, 30000000, 40000000 }, | |
1062 | .hactive = { 800, 800, 800 }, | |
1063 | .hfront_porch = { 40, 40, 40 }, | |
1064 | .hback_porch = { 40, 40, 40 }, | |
1065 | .hsync_len = { 1, 48, 48 }, | |
1066 | .vactive = { 480, 480, 480 }, | |
1067 | .vfront_porch = { 13, 13, 13 }, | |
1068 | .vback_porch = { 29, 29, 29 }, | |
1069 | .vsync_len = { 3, 3, 3 }, | |
1070 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
1071 | }; | |
1072 | ||
1073 | static const struct panel_desc okaya_rs800480t_7x0gp = { | |
1074 | .timings = &okaya_rs800480t_7x0gp_timing, | |
1075 | .num_timings = 1, | |
1076 | .bpc = 6, | |
1077 | .size = { | |
1078 | .width = 154, | |
1079 | .height = 87, | |
1080 | }, | |
1081 | .delay = { | |
1082 | .prepare = 41, | |
1083 | .enable = 50, | |
1084 | .unprepare = 41, | |
1085 | .disable = 50, | |
1086 | }, | |
1087 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
1088 | }; | |
1089 | ||
cf5c9e6d MR |
1090 | static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { |
1091 | .clock = 9000, | |
1092 | .hdisplay = 480, | |
1093 | .hsync_start = 480 + 5, | |
1094 | .hsync_end = 480 + 5 + 30, | |
1095 | .htotal = 480 + 5 + 30 + 10, | |
1096 | .vdisplay = 272, | |
1097 | .vsync_start = 272 + 8, | |
1098 | .vsync_end = 272 + 8 + 5, | |
1099 | .vtotal = 272 + 8 + 5 + 3, | |
1100 | .vrefresh = 60, | |
1101 | }; | |
1102 | ||
1103 | static const struct panel_desc olimex_lcd_olinuxino_43ts = { | |
1104 | .modes = &olimex_lcd_olinuxino_43ts_mode, | |
1105 | .num_modes = 1, | |
1106 | .size = { | |
1107 | .width = 105, | |
1108 | .height = 67, | |
1109 | }, | |
1110 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
1111 | }; | |
1112 | ||
e8b6f561 EA |
1113 | /* |
1114 | * 800x480 CVT. The panel appears to be quite accepting, at least as far as | |
1115 | * pixel clocks, but this is the timing that was being used in the Adafruit | |
1116 | * installation instructions. | |
1117 | */ | |
1118 | static const struct drm_display_mode ontat_yx700wv03_mode = { | |
1119 | .clock = 29500, | |
1120 | .hdisplay = 800, | |
1121 | .hsync_start = 824, | |
1122 | .hsync_end = 896, | |
1123 | .htotal = 992, | |
1124 | .vdisplay = 480, | |
1125 | .vsync_start = 483, | |
1126 | .vsync_end = 493, | |
1127 | .vtotal = 500, | |
1128 | .vrefresh = 60, | |
1129 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
1130 | }; | |
1131 | ||
1132 | /* | |
1133 | * Specification at: | |
1134 | * https://www.adafruit.com/images/product-files/2406/c3163.pdf | |
1135 | */ | |
1136 | static const struct panel_desc ontat_yx700wv03 = { | |
1137 | .modes = &ontat_yx700wv03_mode, | |
1138 | .num_modes = 1, | |
1139 | .bpc = 8, | |
1140 | .size = { | |
1141 | .width = 154, | |
1142 | .height = 83, | |
1143 | }, | |
1144 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1145 | }; | |
1146 | ||
725c9d40 PZ |
1147 | static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { |
1148 | .clock = 25000, | |
1149 | .hdisplay = 480, | |
1150 | .hsync_start = 480 + 10, | |
1151 | .hsync_end = 480 + 10 + 10, | |
1152 | .htotal = 480 + 10 + 10 + 15, | |
1153 | .vdisplay = 800, | |
1154 | .vsync_start = 800 + 3, | |
1155 | .vsync_end = 800 + 3 + 3, | |
1156 | .vtotal = 800 + 3 + 3 + 3, | |
1157 | .vrefresh = 60, | |
1158 | }; | |
1159 | ||
1160 | static const struct panel_desc ortustech_com43h4m85ulc = { | |
1161 | .modes = &ortustech_com43h4m85ulc_mode, | |
1162 | .num_modes = 1, | |
1163 | .bpc = 8, | |
1164 | .size = { | |
1165 | .width = 56, | |
1166 | .height = 93, | |
1167 | }, | |
1168 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1169 | }; | |
1170 | ||
d2a6f0f5 JW |
1171 | static const struct drm_display_mode qd43003c0_40_mode = { |
1172 | .clock = 9000, | |
1173 | .hdisplay = 480, | |
1174 | .hsync_start = 480 + 8, | |
1175 | .hsync_end = 480 + 8 + 4, | |
1176 | .htotal = 480 + 8 + 4 + 39, | |
1177 | .vdisplay = 272, | |
1178 | .vsync_start = 272 + 4, | |
1179 | .vsync_end = 272 + 4 + 10, | |
1180 | .vtotal = 272 + 4 + 10 + 2, | |
1181 | .vrefresh = 60, | |
1182 | }; | |
1183 | ||
1184 | static const struct panel_desc qd43003c0_40 = { | |
1185 | .modes = &qd43003c0_40_mode, | |
1186 | .num_modes = 1, | |
1187 | .bpc = 8, | |
1188 | .size = { | |
1189 | .width = 95, | |
1190 | .height = 53, | |
1191 | }, | |
1192 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1193 | }; | |
1194 | ||
6d54e3d2 MD |
1195 | static const struct drm_display_mode samsung_ltn101nt05_mode = { |
1196 | .clock = 54030, | |
1197 | .hdisplay = 1024, | |
1198 | .hsync_start = 1024 + 24, | |
1199 | .hsync_end = 1024 + 24 + 136, | |
1200 | .htotal = 1024 + 24 + 136 + 160, | |
1201 | .vdisplay = 600, | |
1202 | .vsync_start = 600 + 3, | |
1203 | .vsync_end = 600 + 3 + 6, | |
1204 | .vtotal = 600 + 3 + 6 + 61, | |
1205 | .vrefresh = 60, | |
1206 | }; | |
1207 | ||
1208 | static const struct panel_desc samsung_ltn101nt05 = { | |
1209 | .modes = &samsung_ltn101nt05_mode, | |
1210 | .num_modes = 1, | |
0208d511 | 1211 | .bpc = 6, |
6d54e3d2 MD |
1212 | .size = { |
1213 | .width = 1024, | |
1214 | .height = 600, | |
1215 | }, | |
1216 | }; | |
1217 | ||
0c934306 SM |
1218 | static const struct drm_display_mode samsung_ltn140at29_301_mode = { |
1219 | .clock = 76300, | |
1220 | .hdisplay = 1366, | |
1221 | .hsync_start = 1366 + 64, | |
1222 | .hsync_end = 1366 + 64 + 48, | |
1223 | .htotal = 1366 + 64 + 48 + 128, | |
1224 | .vdisplay = 768, | |
1225 | .vsync_start = 768 + 2, | |
1226 | .vsync_end = 768 + 2 + 5, | |
1227 | .vtotal = 768 + 2 + 5 + 17, | |
1228 | .vrefresh = 60, | |
1229 | }; | |
1230 | ||
1231 | static const struct panel_desc samsung_ltn140at29_301 = { | |
1232 | .modes = &samsung_ltn140at29_301_mode, | |
1233 | .num_modes = 1, | |
1234 | .bpc = 6, | |
1235 | .size = { | |
1236 | .width = 320, | |
1237 | .height = 187, | |
1238 | }, | |
1239 | }; | |
1240 | ||
9c6615bc BB |
1241 | static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { |
1242 | .clock = 33300, | |
1243 | .hdisplay = 800, | |
1244 | .hsync_start = 800 + 1, | |
1245 | .hsync_end = 800 + 1 + 64, | |
1246 | .htotal = 800 + 1 + 64 + 64, | |
1247 | .vdisplay = 480, | |
1248 | .vsync_start = 480 + 1, | |
1249 | .vsync_end = 480 + 1 + 23, | |
1250 | .vtotal = 480 + 1 + 23 + 22, | |
1251 | .vrefresh = 60, | |
1252 | }; | |
1253 | ||
1254 | static const struct panel_desc shelly_sca07010_bfn_lnn = { | |
1255 | .modes = &shelly_sca07010_bfn_lnn_mode, | |
1256 | .num_modes = 1, | |
1257 | .size = { | |
1258 | .width = 152, | |
1259 | .height = 91, | |
1260 | }, | |
1261 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
1262 | }; | |
1263 | ||
06a9dc65 MS |
1264 | static const struct display_timing urt_umsh_8596md_timing = { |
1265 | .pixelclock = { 33260000, 33260000, 33260000 }, | |
1266 | .hactive = { 800, 800, 800 }, | |
1267 | .hfront_porch = { 41, 41, 41 }, | |
1268 | .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, | |
1269 | .hsync_len = { 71, 128, 128 }, | |
1270 | .vactive = { 480, 480, 480 }, | |
1271 | .vfront_porch = { 10, 10, 10 }, | |
1272 | .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, | |
1273 | .vsync_len = { 2, 2, 2 }, | |
1274 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | | |
1275 | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
1276 | }; | |
1277 | ||
1278 | static const struct panel_desc urt_umsh_8596md_lvds = { | |
1279 | .timings = &urt_umsh_8596md_timing, | |
1280 | .num_timings = 1, | |
1281 | .bpc = 6, | |
1282 | .size = { | |
1283 | .width = 152, | |
1284 | .height = 91, | |
1285 | }, | |
1286 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
1287 | }; | |
1288 | ||
1289 | static const struct panel_desc urt_umsh_8596md_parallel = { | |
1290 | .timings = &urt_umsh_8596md_timing, | |
1291 | .num_timings = 1, | |
1292 | .bpc = 6, | |
1293 | .size = { | |
1294 | .width = 152, | |
1295 | .height = 91, | |
1296 | }, | |
1297 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
1298 | }; | |
1299 | ||
280921de TR |
1300 | static const struct of_device_id platform_of_match[] = { |
1301 | { | |
1c550fa1 PZ |
1302 | .compatible = "ampire,am800480r3tmqwa1h", |
1303 | .data = &ire_am800480r3tmqwa1h, | |
1304 | }, { | |
280921de TR |
1305 | .compatible = "auo,b101aw03", |
1306 | .data = &auo_b101aw03, | |
a531bc3d HL |
1307 | }, { |
1308 | .compatible = "auo,b101ean01", | |
1309 | .data = &auo_b101ean01, | |
dac746e0 RC |
1310 | }, { |
1311 | .compatible = "auo,b101xtn01", | |
1312 | .data = &auo_b101xtn01, | |
e35e305e AK |
1313 | }, { |
1314 | .compatible = "auo,b116xw03", | |
1315 | .data = &auo_b116xw03, | |
3e51d609 AK |
1316 | }, { |
1317 | .compatible = "auo,b133htn01", | |
1318 | .data = &auo_b133htn01, | |
a333f7ad SM |
1319 | }, { |
1320 | .compatible = "auo,b133xtn01", | |
1321 | .data = &auo_b133xtn01, | |
d47df633 PZ |
1322 | }, { |
1323 | .compatible = "avic,tm070ddh03", | |
1324 | .data = &avic_tm070ddh03, | |
4c930757 SW |
1325 | }, { |
1326 | .compatible = "chunghwa,claa101wa01a", | |
1327 | .data = &chunghwa_claa101wa01a | |
280921de TR |
1328 | }, { |
1329 | .compatible = "chunghwa,claa101wb01", | |
1330 | .data = &chunghwa_claa101wb01 | |
26ab0065 SA |
1331 | }, { |
1332 | .compatible = "edt,et057090dhu", | |
1333 | .data = &edt_et057090dhu, | |
fff5de45 PZ |
1334 | }, { |
1335 | .compatible = "edt,et070080dh6", | |
1336 | .data = &edt_etm0700g0dh6, | |
1337 | }, { | |
1338 | .compatible = "edt,etm0700g0dh6", | |
1339 | .data = &edt_etm0700g0dh6, | |
102932b0 BB |
1340 | }, { |
1341 | .compatible = "foxlink,fl500wvr00-a0t", | |
1342 | .data = &foxlink_fl500wvr00_a0t, | |
d435a2af PZ |
1343 | }, { |
1344 | .compatible = "giantplus,gpg482739qs5", | |
1345 | .data = &giantplus_gpg482739qs5 | |
a853205e PZ |
1346 | }, { |
1347 | .compatible = "hannstar,hsd070pww1", | |
1348 | .data = &hannstar_hsd070pww1, | |
c0d607e5 EN |
1349 | }, { |
1350 | .compatible = "hannstar,hsd100pxn1", | |
1351 | .data = &hannstar_hsd100pxn1, | |
61ac0bf8 LS |
1352 | }, { |
1353 | .compatible = "hit,tx23d38vm0caa", | |
1354 | .data = &hitachi_tx23d38vm0caa | |
41bcceb4 NF |
1355 | }, { |
1356 | .compatible = "innolux,at043tn24", | |
1357 | .data = &innolux_at043tn24, | |
d731f661 LS |
1358 | }, { |
1359 | .compatible ="innolux,g121i1-l01", | |
1360 | .data = &innolux_g121i1_l01 | |
f8fa17ba AB |
1361 | }, { |
1362 | .compatible = "innolux,g121x1-l03", | |
1363 | .data = &innolux_g121x1_l03, | |
0a2288c0 TR |
1364 | }, { |
1365 | .compatible = "innolux,n116bge", | |
1366 | .data = &innolux_n116bge, | |
ea44739d AB |
1367 | }, { |
1368 | .compatible = "innolux,n156bge-l21", | |
1369 | .data = &innolux_n156bge_l21, | |
bccac3f1 MG |
1370 | }, { |
1371 | .compatible = "innolux,zj070na-01p", | |
1372 | .data = &innolux_zj070na_01p, | |
8def22e5 LS |
1373 | }, { |
1374 | .compatible = "kyo,tcg121xglp", | |
1375 | .data = &kyo_tcg121xglp, | |
dd015002 HS |
1376 | }, { |
1377 | .compatible = "lg,lb070wv8", | |
1378 | .data = &lg_lb070wv8, | |
690d8fa7 JS |
1379 | }, { |
1380 | .compatible = "lg,lp120up1", | |
1381 | .data = &lg_lp120up1, | |
ec7c5653 TR |
1382 | }, { |
1383 | .compatible = "lg,lp129qe", | |
1384 | .data = &lg_lp129qe, | |
c6e87f91 | 1385 | }, { |
1386 | .compatible = "nec,nl4827hc19-05b", | |
1387 | .data = &nec_nl4827hc19_05b, | |
a99fb626 GB |
1388 | }, { |
1389 | .compatible = "okaya,rs800480t-7x0gp", | |
1390 | .data = &okaya_rs800480t_7x0gp, | |
cf5c9e6d MR |
1391 | }, { |
1392 | .compatible = "olimex,lcd-olinuxino-43-ts", | |
1393 | .data = &olimex_lcd_olinuxino_43ts, | |
e8b6f561 EA |
1394 | }, { |
1395 | .compatible = "ontat,yx700wv03", | |
1396 | .data = &ontat_yx700wv03, | |
725c9d40 PZ |
1397 | }, { |
1398 | .compatible = "ortustech,com43h4m85ulc", | |
1399 | .data = &ortustech_com43h4m85ulc, | |
d2a6f0f5 JW |
1400 | }, { |
1401 | .compatible = "qiaodian,qd43003c0-40", | |
1402 | .data = &qd43003c0_40, | |
6d54e3d2 MD |
1403 | }, { |
1404 | .compatible = "samsung,ltn101nt05", | |
1405 | .data = &samsung_ltn101nt05, | |
0c934306 SM |
1406 | }, { |
1407 | .compatible = "samsung,ltn140at29-301", | |
1408 | .data = &samsung_ltn140at29_301, | |
9c6615bc BB |
1409 | }, { |
1410 | .compatible = "shelly,sca07010-bfn-lnn", | |
1411 | .data = &shelly_sca07010_bfn_lnn, | |
06a9dc65 MS |
1412 | }, { |
1413 | .compatible = "urt,umsh-8596md-t", | |
1414 | .data = &urt_umsh_8596md_parallel, | |
1415 | }, { | |
1416 | .compatible = "urt,umsh-8596md-1t", | |
1417 | .data = &urt_umsh_8596md_parallel, | |
1418 | }, { | |
1419 | .compatible = "urt,umsh-8596md-7t", | |
1420 | .data = &urt_umsh_8596md_parallel, | |
1421 | }, { | |
1422 | .compatible = "urt,umsh-8596md-11t", | |
1423 | .data = &urt_umsh_8596md_lvds, | |
1424 | }, { | |
1425 | .compatible = "urt,umsh-8596md-19t", | |
1426 | .data = &urt_umsh_8596md_lvds, | |
1427 | }, { | |
1428 | .compatible = "urt,umsh-8596md-20t", | |
1429 | .data = &urt_umsh_8596md_parallel, | |
280921de TR |
1430 | }, { |
1431 | /* sentinel */ | |
1432 | } | |
1433 | }; | |
1434 | MODULE_DEVICE_TABLE(of, platform_of_match); | |
1435 | ||
1436 | static int panel_simple_platform_probe(struct platform_device *pdev) | |
1437 | { | |
1438 | const struct of_device_id *id; | |
1439 | ||
1440 | id = of_match_node(platform_of_match, pdev->dev.of_node); | |
1441 | if (!id) | |
1442 | return -ENODEV; | |
1443 | ||
1444 | return panel_simple_probe(&pdev->dev, id->data); | |
1445 | } | |
1446 | ||
1447 | static int panel_simple_platform_remove(struct platform_device *pdev) | |
1448 | { | |
1449 | return panel_simple_remove(&pdev->dev); | |
1450 | } | |
1451 | ||
d02fd93e TR |
1452 | static void panel_simple_platform_shutdown(struct platform_device *pdev) |
1453 | { | |
1454 | panel_simple_shutdown(&pdev->dev); | |
1455 | } | |
1456 | ||
280921de TR |
1457 | static struct platform_driver panel_simple_platform_driver = { |
1458 | .driver = { | |
1459 | .name = "panel-simple", | |
280921de TR |
1460 | .of_match_table = platform_of_match, |
1461 | }, | |
1462 | .probe = panel_simple_platform_probe, | |
1463 | .remove = panel_simple_platform_remove, | |
d02fd93e | 1464 | .shutdown = panel_simple_platform_shutdown, |
280921de TR |
1465 | }; |
1466 | ||
210fcd9d TR |
1467 | struct panel_desc_dsi { |
1468 | struct panel_desc desc; | |
1469 | ||
462658b8 | 1470 | unsigned long flags; |
210fcd9d TR |
1471 | enum mipi_dsi_pixel_format format; |
1472 | unsigned int lanes; | |
1473 | }; | |
1474 | ||
d718d79e TR |
1475 | static const struct drm_display_mode auo_b080uan01_mode = { |
1476 | .clock = 154500, | |
1477 | .hdisplay = 1200, | |
1478 | .hsync_start = 1200 + 62, | |
1479 | .hsync_end = 1200 + 62 + 4, | |
1480 | .htotal = 1200 + 62 + 4 + 62, | |
1481 | .vdisplay = 1920, | |
1482 | .vsync_start = 1920 + 9, | |
1483 | .vsync_end = 1920 + 9 + 2, | |
1484 | .vtotal = 1920 + 9 + 2 + 8, | |
1485 | .vrefresh = 60, | |
1486 | }; | |
1487 | ||
1488 | static const struct panel_desc_dsi auo_b080uan01 = { | |
1489 | .desc = { | |
1490 | .modes = &auo_b080uan01_mode, | |
1491 | .num_modes = 1, | |
1492 | .bpc = 8, | |
1493 | .size = { | |
1494 | .width = 108, | |
1495 | .height = 272, | |
1496 | }, | |
1497 | }, | |
1498 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, | |
1499 | .format = MIPI_DSI_FMT_RGB888, | |
1500 | .lanes = 4, | |
1501 | }; | |
1502 | ||
c8521969 CZ |
1503 | static const struct drm_display_mode boe_tv080wum_nl0_mode = { |
1504 | .clock = 160000, | |
1505 | .hdisplay = 1200, | |
1506 | .hsync_start = 1200 + 120, | |
1507 | .hsync_end = 1200 + 120 + 20, | |
1508 | .htotal = 1200 + 120 + 20 + 21, | |
1509 | .vdisplay = 1920, | |
1510 | .vsync_start = 1920 + 21, | |
1511 | .vsync_end = 1920 + 21 + 3, | |
1512 | .vtotal = 1920 + 21 + 3 + 18, | |
1513 | .vrefresh = 60, | |
1514 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
1515 | }; | |
1516 | ||
1517 | static const struct panel_desc_dsi boe_tv080wum_nl0 = { | |
1518 | .desc = { | |
1519 | .modes = &boe_tv080wum_nl0_mode, | |
1520 | .num_modes = 1, | |
1521 | .size = { | |
1522 | .width = 107, | |
1523 | .height = 172, | |
1524 | }, | |
1525 | }, | |
1526 | .flags = MIPI_DSI_MODE_VIDEO | | |
1527 | MIPI_DSI_MODE_VIDEO_BURST | | |
1528 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, | |
1529 | .format = MIPI_DSI_FMT_RGB888, | |
1530 | .lanes = 4, | |
1531 | }; | |
1532 | ||
712ac1ba AC |
1533 | static const struct drm_display_mode lg_ld070wx3_sl01_mode = { |
1534 | .clock = 71000, | |
1535 | .hdisplay = 800, | |
1536 | .hsync_start = 800 + 32, | |
1537 | .hsync_end = 800 + 32 + 1, | |
1538 | .htotal = 800 + 32 + 1 + 57, | |
1539 | .vdisplay = 1280, | |
1540 | .vsync_start = 1280 + 28, | |
1541 | .vsync_end = 1280 + 28 + 1, | |
1542 | .vtotal = 1280 + 28 + 1 + 14, | |
1543 | .vrefresh = 60, | |
1544 | }; | |
1545 | ||
1546 | static const struct panel_desc_dsi lg_ld070wx3_sl01 = { | |
1547 | .desc = { | |
1548 | .modes = &lg_ld070wx3_sl01_mode, | |
1549 | .num_modes = 1, | |
d7a839cd | 1550 | .bpc = 8, |
712ac1ba AC |
1551 | .size = { |
1552 | .width = 94, | |
1553 | .height = 151, | |
1554 | }, | |
1555 | }, | |
5e4cc278 | 1556 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, |
712ac1ba AC |
1557 | .format = MIPI_DSI_FMT_RGB888, |
1558 | .lanes = 4, | |
1559 | }; | |
1560 | ||
499ce85a AC |
1561 | static const struct drm_display_mode lg_lh500wx1_sd03_mode = { |
1562 | .clock = 67000, | |
1563 | .hdisplay = 720, | |
1564 | .hsync_start = 720 + 12, | |
1565 | .hsync_end = 720 + 12 + 4, | |
1566 | .htotal = 720 + 12 + 4 + 112, | |
1567 | .vdisplay = 1280, | |
1568 | .vsync_start = 1280 + 8, | |
1569 | .vsync_end = 1280 + 8 + 4, | |
1570 | .vtotal = 1280 + 8 + 4 + 12, | |
1571 | .vrefresh = 60, | |
1572 | }; | |
1573 | ||
1574 | static const struct panel_desc_dsi lg_lh500wx1_sd03 = { | |
1575 | .desc = { | |
1576 | .modes = &lg_lh500wx1_sd03_mode, | |
1577 | .num_modes = 1, | |
d7a839cd | 1578 | .bpc = 8, |
499ce85a AC |
1579 | .size = { |
1580 | .width = 62, | |
1581 | .height = 110, | |
1582 | }, | |
1583 | }, | |
1584 | .flags = MIPI_DSI_MODE_VIDEO, | |
1585 | .format = MIPI_DSI_FMT_RGB888, | |
1586 | .lanes = 4, | |
1587 | }; | |
1588 | ||
280921de TR |
1589 | static const struct drm_display_mode panasonic_vvx10f004b00_mode = { |
1590 | .clock = 157200, | |
1591 | .hdisplay = 1920, | |
1592 | .hsync_start = 1920 + 154, | |
1593 | .hsync_end = 1920 + 154 + 16, | |
1594 | .htotal = 1920 + 154 + 16 + 32, | |
1595 | .vdisplay = 1200, | |
1596 | .vsync_start = 1200 + 17, | |
1597 | .vsync_end = 1200 + 17 + 2, | |
1598 | .vtotal = 1200 + 17 + 2 + 16, | |
1599 | .vrefresh = 60, | |
1600 | }; | |
1601 | ||
210fcd9d TR |
1602 | static const struct panel_desc_dsi panasonic_vvx10f004b00 = { |
1603 | .desc = { | |
1604 | .modes = &panasonic_vvx10f004b00_mode, | |
1605 | .num_modes = 1, | |
d7a839cd | 1606 | .bpc = 8, |
210fcd9d TR |
1607 | .size = { |
1608 | .width = 217, | |
1609 | .height = 136, | |
1610 | }, | |
280921de | 1611 | }, |
5e4cc278 AC |
1612 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1613 | MIPI_DSI_CLOCK_NON_CONTINUOUS, | |
210fcd9d TR |
1614 | .format = MIPI_DSI_FMT_RGB888, |
1615 | .lanes = 4, | |
1616 | }; | |
1617 | ||
c8521969 | 1618 | |
210fcd9d TR |
1619 | static const struct of_device_id dsi_of_match[] = { |
1620 | { | |
d718d79e TR |
1621 | .compatible = "auo,b080uan01", |
1622 | .data = &auo_b080uan01 | |
c8521969 CZ |
1623 | }, { |
1624 | .compatible = "boe,tv080wum-nl0", | |
1625 | .data = &boe_tv080wum_nl0 | |
d718d79e | 1626 | }, { |
712ac1ba AC |
1627 | .compatible = "lg,ld070wx3-sl01", |
1628 | .data = &lg_ld070wx3_sl01 | |
1629 | }, { | |
499ce85a AC |
1630 | .compatible = "lg,lh500wx1-sd03", |
1631 | .data = &lg_lh500wx1_sd03 | |
1632 | }, { | |
210fcd9d TR |
1633 | .compatible = "panasonic,vvx10f004b00", |
1634 | .data = &panasonic_vvx10f004b00 | |
1635 | }, { | |
1636 | /* sentinel */ | |
1637 | } | |
1638 | }; | |
1639 | MODULE_DEVICE_TABLE(of, dsi_of_match); | |
1640 | ||
1641 | static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) | |
1642 | { | |
1643 | const struct panel_desc_dsi *desc; | |
1644 | const struct of_device_id *id; | |
1645 | int err; | |
1646 | ||
1647 | id = of_match_node(dsi_of_match, dsi->dev.of_node); | |
1648 | if (!id) | |
1649 | return -ENODEV; | |
1650 | ||
1651 | desc = id->data; | |
1652 | ||
1653 | err = panel_simple_probe(&dsi->dev, &desc->desc); | |
1654 | if (err < 0) | |
1655 | return err; | |
1656 | ||
462658b8 | 1657 | dsi->mode_flags = desc->flags; |
210fcd9d TR |
1658 | dsi->format = desc->format; |
1659 | dsi->lanes = desc->lanes; | |
1660 | ||
1661 | return mipi_dsi_attach(dsi); | |
1662 | } | |
1663 | ||
1664 | static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) | |
1665 | { | |
1666 | int err; | |
1667 | ||
1668 | err = mipi_dsi_detach(dsi); | |
1669 | if (err < 0) | |
1670 | dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); | |
1671 | ||
1672 | return panel_simple_remove(&dsi->dev); | |
1673 | } | |
1674 | ||
d02fd93e TR |
1675 | static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) |
1676 | { | |
1677 | panel_simple_shutdown(&dsi->dev); | |
1678 | } | |
1679 | ||
210fcd9d TR |
1680 | static struct mipi_dsi_driver panel_simple_dsi_driver = { |
1681 | .driver = { | |
1682 | .name = "panel-simple-dsi", | |
210fcd9d TR |
1683 | .of_match_table = dsi_of_match, |
1684 | }, | |
1685 | .probe = panel_simple_dsi_probe, | |
1686 | .remove = panel_simple_dsi_remove, | |
d02fd93e | 1687 | .shutdown = panel_simple_dsi_shutdown, |
280921de TR |
1688 | }; |
1689 | ||
1690 | static int __init panel_simple_init(void) | |
1691 | { | |
210fcd9d TR |
1692 | int err; |
1693 | ||
1694 | err = platform_driver_register(&panel_simple_platform_driver); | |
1695 | if (err < 0) | |
1696 | return err; | |
1697 | ||
1698 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { | |
1699 | err = mipi_dsi_driver_register(&panel_simple_dsi_driver); | |
1700 | if (err < 0) | |
1701 | return err; | |
1702 | } | |
1703 | ||
1704 | return 0; | |
280921de TR |
1705 | } |
1706 | module_init(panel_simple_init); | |
1707 | ||
1708 | static void __exit panel_simple_exit(void) | |
1709 | { | |
210fcd9d TR |
1710 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) |
1711 | mipi_dsi_driver_unregister(&panel_simple_dsi_driver); | |
1712 | ||
280921de TR |
1713 | platform_driver_unregister(&panel_simple_platform_driver); |
1714 | } | |
1715 | module_exit(panel_simple_exit); | |
1716 | ||
1717 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
1718 | MODULE_DESCRIPTION("DRM Driver for Simple Panels"); | |
1719 | MODULE_LICENSE("GPL and additional rights"); |