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of: Add vendor prefix for Ortus Technology Co., Ltd.
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
36struct panel_desc {
37 const struct drm_display_mode *modes;
38 unsigned int num_modes;
39
0208d511
SM		 40 unsigned int bpc;
41
280921de
TR		 42 struct {
43 unsigned int width;
44 unsigned int height;
45 } size;
f673c37e
AK		 46
47 /**
48 * @prepare: the time (in milliseconds) that it takes for the panel to
49 * become ready and start receiving video data
50 * @enable: the time (in milliseconds) that it takes for the panel to
51 * display the first valid frame after starting to receive
52 * video data
53 * @disable: the time (in milliseconds) that it takes for the panel to
54 * turn the display off (no content is visible)
55 * @unprepare: the time (in milliseconds) that it takes for the panel
56 * to power itself down completely
57 */
58 struct {
59 unsigned int prepare;
60 unsigned int enable;
61 unsigned int disable;
62 unsigned int unprepare;
63 } delay;
795f7ab3
BB		 64
65 u32 bus_format;
280921de
TR		 66};
67
280921de
TR		 68struct panel_simple {
69 struct drm_panel base;
613a633e 70 bool prepared;
280921de
TR		 71 bool enabled;
72
73 const struct panel_desc *desc;
74
75 struct backlight_device *backlight;
76 struct regulator *supply;
77 struct i2c_adapter *ddc;
78
cfdf0549 79 struct gpio_desc *enable_gpio;
280921de
TR		 80};
81
82static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
83{
84 return container_of(panel, struct panel_simple, base);
85}
86
87static int panel_simple_get_fixed_modes(struct panel_simple *panel)
88{
89 struct drm_connector *connector = panel->base.connector;
90 struct drm_device *drm = panel->base.drm;
91 struct drm_display_mode *mode;
92 unsigned int i, num = 0;
93
94 if (!panel->desc)
95 return 0;
96
97 for (i = 0; i < panel->desc->num_modes; i++) {
98 const struct drm_display_mode *m = &panel->desc->modes[i];
99
100 mode = drm_mode_duplicate(drm, m);
101 if (!mode) {
102 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
103 m->hdisplay, m->vdisplay, m->vrefresh);
104 continue;
105 }
106
107 drm_mode_set_name(mode);
108
109 drm_mode_probed_add(connector, mode);
110 num++;
111 }
112
0208d511 113 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 114 connector->display_info.width_mm = panel->desc->size.width;
115 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 116 if (panel->desc->bus_format)
117 drm_display_info_set_bus_formats(&connector->display_info,
118 &panel->desc->bus_format, 1);
280921de
TR		 119
120 return num;
121}
122
123static int panel_simple_disable(struct drm_panel *panel)
124{
125 struct panel_simple *p = to_panel_simple(panel);
126
127 if (!p->enabled)
128 return 0;
129
130 if (p->backlight) {
131 p->backlight->props.power = FB_BLANK_POWERDOWN;
132 backlight_update_status(p->backlight);
133 }
134
f673c37e
AK		 135 if (p->desc->delay.disable)
136 msleep(p->desc->delay.disable);
137
280921de
TR		 138 p->enabled = false;
139
140 return 0;
141}
142
c0e1d170
AK		 143static int panel_simple_unprepare(struct drm_panel *panel)
144{
613a633e
AK		 145 struct panel_simple *p = to_panel_simple(panel);
146
147 if (!p->prepared)
148 return 0;
149
150 if (p->enable_gpio)
151 gpiod_set_value_cansleep(p->enable_gpio, 0);
152
153 regulator_disable(p->supply);
154
f673c37e
AK		 155 if (p->desc->delay.unprepare)
156 msleep(p->desc->delay.unprepare);
157
613a633e 158 p->prepared = false;
c0e1d170 159
c0e1d170
AK		 160 return 0;
161}
162
613a633e 163static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 164{
165 struct panel_simple *p = to_panel_simple(panel);
166 int err;
167
613a633e 168 if (p->prepared)
280921de
TR		 169 return 0;
170
171 err = regulator_enable(p->supply);
172 if (err < 0) {
173 dev_err(panel->dev, "failed to enable supply: %d\n", err);
174 return err;
175 }
176
cfdf0549 177 if (p->enable_gpio)
15c1a919 178 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 179
f673c37e
AK		 180 if (p->desc->delay.prepare)
181 msleep(p->desc->delay.prepare);
182
613a633e
AK		 183 p->prepared = true;
184
185 return 0;
186}
187
188static int panel_simple_enable(struct drm_panel *panel)
189{
190 struct panel_simple *p = to_panel_simple(panel);
191
192 if (p->enabled)
193 return 0;
194
f673c37e
AK		 195 if (p->desc->delay.enable)
196 msleep(p->desc->delay.enable);
197
280921de
TR		 198 if (p->backlight) {
199 p->backlight->props.power = FB_BLANK_UNBLANK;
200 backlight_update_status(p->backlight);
201 }
202
203 p->enabled = true;
204
205 return 0;
206}
207
208static int panel_simple_get_modes(struct drm_panel *panel)
209{
210 struct panel_simple *p = to_panel_simple(panel);
211 int num = 0;
212
213 /* probe EDID if a DDC bus is available */
214 if (p->ddc) {
215 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 216 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 217 if (edid) {
218 num += drm_add_edid_modes(panel->connector, edid);
219 kfree(edid);
220 }
221 }
222
223 /* add hard-coded panel modes */
224 num += panel_simple_get_fixed_modes(p);
225
226 return num;
227}
228
229static const struct drm_panel_funcs panel_simple_funcs = {
230 .disable = panel_simple_disable,
c0e1d170
AK		 231 .unprepare = panel_simple_unprepare,
232 .prepare = panel_simple_prepare,
280921de
TR		 233 .enable = panel_simple_enable,
234 .get_modes = panel_simple_get_modes,
235};
236
237static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
238{
239 struct device_node *backlight, *ddc;
240 struct panel_simple *panel;
280921de
TR		 241 int err;
242
243 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
244 if (!panel)
245 return -ENOMEM;
246
247 panel->enabled = false;
613a633e 248 panel->prepared = false;
280921de
TR		 249 panel->desc = desc;
250
251 panel->supply = devm_regulator_get(dev, "power");
252 if (IS_ERR(panel->supply))
253 return PTR_ERR(panel->supply);
254
a61400d8
AC		 255 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
256 GPIOD_OUT_LOW);
cfdf0549
AC		 257 if (IS_ERR(panel->enable_gpio)) {
258 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 259 dev_err(dev, "failed to request GPIO: %d\n", err);
260 return err;
261 }
280921de 262
280921de
TR		 263 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
264 if (backlight) {
265 panel->backlight = of_find_backlight_by_node(backlight);
266 of_node_put(backlight);
267
cfdf0549
AC		 268 if (!panel->backlight)
269 return -EPROBE_DEFER;
280921de
TR		 270 }
271
272 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
273 if (ddc) {
274 panel->ddc = of_find_i2c_adapter_by_node(ddc);
275 of_node_put(ddc);
276
277 if (!panel->ddc) {
278 err = -EPROBE_DEFER;
279 goto free_backlight;
280 }
281 }
282
283 drm_panel_init(&panel->base);
284 panel->base.dev = dev;
285 panel->base.funcs = &panel_simple_funcs;
286
287 err = drm_panel_add(&panel->base);
288 if (err < 0)
289 goto free_ddc;
290
291 dev_set_drvdata(dev, panel);
292
293 return 0;
294
295free_ddc:
296 if (panel->ddc)
297 put_device(&panel->ddc->dev);
298free_backlight:
299 if (panel->backlight)
300 put_device(&panel->backlight->dev);
280921de
TR		 301
302 return err;
303}
304
305static int panel_simple_remove(struct device *dev)
306{
307 struct panel_simple *panel = dev_get_drvdata(dev);
308
309 drm_panel_detach(&panel->base);
310 drm_panel_remove(&panel->base);
311
312 panel_simple_disable(&panel->base);
313
314 if (panel->ddc)
315 put_device(&panel->ddc->dev);
316
317 if (panel->backlight)
318 put_device(&panel->backlight->dev);
319
280921de
TR		 320 return 0;
321}
322
d02fd93e
TR		 323static void panel_simple_shutdown(struct device *dev)
324{
325 struct panel_simple *panel = dev_get_drvdata(dev);
326
327 panel_simple_disable(&panel->base);
328}
329
280921de
TR		 330static const struct drm_display_mode auo_b101aw03_mode = {
331 .clock = 51450,
332 .hdisplay = 1024,
333 .hsync_start = 1024 + 156,
334 .hsync_end = 1024 + 156 + 8,
335 .htotal = 1024 + 156 + 8 + 156,
336 .vdisplay = 600,
337 .vsync_start = 600 + 16,
338 .vsync_end = 600 + 16 + 6,
339 .vtotal = 600 + 16 + 6 + 16,
340 .vrefresh = 60,
341};
342
343static const struct panel_desc auo_b101aw03 = {
344 .modes = &auo_b101aw03_mode,
345 .num_modes = 1,
0208d511 346 .bpc = 6,
280921de
TR		 347 .size = {
348 .width = 223,
349 .height = 125,
350 },
351};
352
a531bc3d
HL		 353static const struct drm_display_mode auo_b101ean01_mode = {
354 .clock = 72500,
355 .hdisplay = 1280,
356 .hsync_start = 1280 + 119,
357 .hsync_end = 1280 + 119 + 32,
358 .htotal = 1280 + 119 + 32 + 21,
359 .vdisplay = 800,
360 .vsync_start = 800 + 4,
361 .vsync_end = 800 + 4 + 20,
362 .vtotal = 800 + 4 + 20 + 8,
363 .vrefresh = 60,
364};
365
366static const struct panel_desc auo_b101ean01 = {
367 .modes = &auo_b101ean01_mode,
368 .num_modes = 1,
369 .bpc = 6,
370 .size = {
371 .width = 217,
372 .height = 136,
373 },
374};
375
dac746e0
RC		 376static const struct drm_display_mode auo_b101xtn01_mode = {
377 .clock = 72000,
378 .hdisplay = 1366,
379 .hsync_start = 1366 + 20,
380 .hsync_end = 1366 + 20 + 70,
381 .htotal = 1366 + 20 + 70,
382 .vdisplay = 768,
383 .vsync_start = 768 + 14,
384 .vsync_end = 768 + 14 + 42,
385 .vtotal = 768 + 14 + 42,
386 .vrefresh = 60,
387 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
388};
389
390static const struct panel_desc auo_b101xtn01 = {
391 .modes = &auo_b101xtn01_mode,
392 .num_modes = 1,
393 .bpc = 6,
394 .size = {
395 .width = 223,
396 .height = 125,
397 },
398};
399
e35e305e
AK		 400static const struct drm_display_mode auo_b116xw03_mode = {
401 .clock = 70589,
402 .hdisplay = 1366,
403 .hsync_start = 1366 + 40,
404 .hsync_end = 1366 + 40 + 40,
405 .htotal = 1366 + 40 + 40 + 32,
406 .vdisplay = 768,
407 .vsync_start = 768 + 10,
408 .vsync_end = 768 + 10 + 12,
409 .vtotal = 768 + 10 + 12 + 6,
410 .vrefresh = 60,
411};
412
413static const struct panel_desc auo_b116xw03 = {
414 .modes = &auo_b116xw03_mode,
415 .num_modes = 1,
416 .bpc = 6,
417 .size = {
418 .width = 256,
419 .height = 144,
420 },
421};
422
a333f7ad
SM		 423static const struct drm_display_mode auo_b133xtn01_mode = {
424 .clock = 69500,
425 .hdisplay = 1366,
426 .hsync_start = 1366 + 48,
427 .hsync_end = 1366 + 48 + 32,
428 .htotal = 1366 + 48 + 32 + 20,
429 .vdisplay = 768,
430 .vsync_start = 768 + 3,
431 .vsync_end = 768 + 3 + 6,
432 .vtotal = 768 + 3 + 6 + 13,
433 .vrefresh = 60,
434};
435
436static const struct panel_desc auo_b133xtn01 = {
437 .modes = &auo_b133xtn01_mode,
438 .num_modes = 1,
0208d511 439 .bpc = 6,
a333f7ad
SM		 440 .size = {
441 .width = 293,
442 .height = 165,
443 },
444};
445
3e51d609
AK		 446static const struct drm_display_mode auo_b133htn01_mode = {
447 .clock = 150660,
448 .hdisplay = 1920,
449 .hsync_start = 1920 + 172,
450 .hsync_end = 1920 + 172 + 80,
451 .htotal = 1920 + 172 + 80 + 60,
452 .vdisplay = 1080,
453 .vsync_start = 1080 + 25,
454 .vsync_end = 1080 + 25 + 10,
455 .vtotal = 1080 + 25 + 10 + 10,
456 .vrefresh = 60,
457};
458
459static const struct panel_desc auo_b133htn01 = {
460 .modes = &auo_b133htn01_mode,
461 .num_modes = 1,
d7a839cd 462 .bpc = 6,
3e51d609
AK		 463 .size = {
464 .width = 293,
465 .height = 165,
466 },
467 .delay = {
468 .prepare = 105,
469 .enable = 20,
470 .unprepare = 50,
471 },
472};
473
d47df633
PZ		 474static const struct drm_display_mode avic_tm070ddh03_mode = {
475 .clock = 51200,
476 .hdisplay = 1024,
477 .hsync_start = 1024 + 160,
478 .hsync_end = 1024 + 160 + 4,
479 .htotal = 1024 + 160 + 4 + 156,
480 .vdisplay = 600,
481 .vsync_start = 600 + 17,
482 .vsync_end = 600 + 17 + 1,
483 .vtotal = 600 + 17 + 1 + 17,
484 .vrefresh = 60,
485};
486
487static const struct panel_desc avic_tm070ddh03 = {
488 .modes = &avic_tm070ddh03_mode,
489 .num_modes = 1,
490 .bpc = 8,
491 .size = {
492 .width = 154,
493 .height = 90,
494 },
495 .delay = {
496 .prepare = 20,
497 .enable = 200,
498 .disable = 200,
499 },
500};
501
4c930757
SW		 502static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
503 .clock = 72070,
504 .hdisplay = 1366,
505 .hsync_start = 1366 + 58,
506 .hsync_end = 1366 + 58 + 58,
507 .htotal = 1366 + 58 + 58 + 58,
508 .vdisplay = 768,
509 .vsync_start = 768 + 4,
510 .vsync_end = 768 + 4 + 4,
511 .vtotal = 768 + 4 + 4 + 4,
512 .vrefresh = 60,
513};
514
515static const struct panel_desc chunghwa_claa101wa01a = {
516 .modes = &chunghwa_claa101wa01a_mode,
517 .num_modes = 1,
0208d511 518 .bpc = 6,
4c930757
SW		 519 .size = {
520 .width = 220,
521 .height = 120,
522 },
523};
524
280921de
TR		 525static const struct drm_display_mode chunghwa_claa101wb01_mode = {
526 .clock = 69300,
527 .hdisplay = 1366,
528 .hsync_start = 1366 + 48,
529 .hsync_end = 1366 + 48 + 32,
530 .htotal = 1366 + 48 + 32 + 20,
531 .vdisplay = 768,
532 .vsync_start = 768 + 16,
533 .vsync_end = 768 + 16 + 8,
534 .vtotal = 768 + 16 + 8 + 16,
535 .vrefresh = 60,
536};
537
538static const struct panel_desc chunghwa_claa101wb01 = {
539 .modes = &chunghwa_claa101wb01_mode,
540 .num_modes = 1,
0208d511 541 .bpc = 6,
280921de
TR		 542 .size = {
543 .width = 223,
544 .height = 125,
545 },
546};
547
26ab0065
SA		 548static const struct drm_display_mode edt_et057090dhu_mode = {
549 .clock = 25175,
550 .hdisplay = 640,
551 .hsync_start = 640 + 16,
552 .hsync_end = 640 + 16 + 30,
553 .htotal = 640 + 16 + 30 + 114,
554 .vdisplay = 480,
555 .vsync_start = 480 + 10,
556 .vsync_end = 480 + 10 + 3,
557 .vtotal = 480 + 10 + 3 + 32,
558 .vrefresh = 60,
559 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
560};
561
562static const struct panel_desc edt_et057090dhu = {
563 .modes = &edt_et057090dhu_mode,
564 .num_modes = 1,
0208d511 565 .bpc = 6,
26ab0065
SA		 566 .size = {
567 .width = 115,
568 .height = 86,
569 },
570};
571
fff5de45
PZ		 572static const struct drm_display_mode edt_etm0700g0dh6_mode = {
573 .clock = 33260,
574 .hdisplay = 800,
575 .hsync_start = 800 + 40,
576 .hsync_end = 800 + 40 + 128,
577 .htotal = 800 + 40 + 128 + 88,
578 .vdisplay = 480,
579 .vsync_start = 480 + 10,
580 .vsync_end = 480 + 10 + 2,
581 .vtotal = 480 + 10 + 2 + 33,
582 .vrefresh = 60,
583 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
584};
585
586static const struct panel_desc edt_etm0700g0dh6 = {
587 .modes = &edt_etm0700g0dh6_mode,
588 .num_modes = 1,
0208d511 589 .bpc = 6,
fff5de45
PZ		 590 .size = {
591 .width = 152,
592 .height = 91,
593 },
594};
595
102932b0
BB		 596static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
597 .clock = 32260,
598 .hdisplay = 800,
599 .hsync_start = 800 + 168,
600 .hsync_end = 800 + 168 + 64,
601 .htotal = 800 + 168 + 64 + 88,
602 .vdisplay = 480,
603 .vsync_start = 480 + 37,
604 .vsync_end = 480 + 37 + 2,
605 .vtotal = 480 + 37 + 2 + 8,
606 .vrefresh = 60,
607};
608
609static const struct panel_desc foxlink_fl500wvr00_a0t = {
610 .modes = &foxlink_fl500wvr00_a0t_mode,
611 .num_modes = 1,
d7a839cd 612 .bpc = 8,
102932b0
BB		 613 .size = {
614 .width = 108,
615 .height = 65,
616 },
bb276cb3 617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 618};
619
d435a2af
PZ		 620static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
621 .clock = 9000,
622 .hdisplay = 480,
623 .hsync_start = 480 + 5,
624 .hsync_end = 480 + 5 + 1,
625 .htotal = 480 + 5 + 1 + 40,
626 .vdisplay = 272,
627 .vsync_start = 272 + 8,
628 .vsync_end = 272 + 8 + 1,
629 .vtotal = 272 + 8 + 1 + 8,
630 .vrefresh = 60,
631};
632
633static const struct panel_desc giantplus_gpg482739qs5 = {
634 .modes = &giantplus_gpg482739qs5_mode,
635 .num_modes = 1,
636 .bpc = 8,
637 .size = {
638 .width = 95,
639 .height = 54,
640 },
33536a09 641 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 642};
643
a853205e
PZ		 644static const struct drm_display_mode hannstar_hsd070pww1_mode = {
645 .clock = 71100,
646 .hdisplay = 1280,
647 .hsync_start = 1280 + 1,
648 .hsync_end = 1280 + 1 + 158,
649 .htotal = 1280 + 1 + 158 + 1,
650 .vdisplay = 800,
651 .vsync_start = 800 + 1,
652 .vsync_end = 800 + 1 + 21,
653 .vtotal = 800 + 1 + 21 + 1,
654 .vrefresh = 60,
655};
656
657static const struct panel_desc hannstar_hsd070pww1 = {
658 .modes = &hannstar_hsd070pww1_mode,
659 .num_modes = 1,
660 .bpc = 6,
661 .size = {
662 .width = 151,
663 .height = 94,
664 },
665};
666
61ac0bf8
LS		 667static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
668 .clock = 33333,
669 .hdisplay = 800,
670 .hsync_start = 800 + 85,
671 .hsync_end = 800 + 85 + 86,
672 .htotal = 800 + 85 + 86 + 85,
673 .vdisplay = 480,
674 .vsync_start = 480 + 16,
675 .vsync_end = 480 + 16 + 13,
676 .vtotal = 480 + 16 + 13 + 16,
677 .vrefresh = 60,
678};
679
680static const struct panel_desc hitachi_tx23d38vm0caa = {
681 .modes = &hitachi_tx23d38vm0caa_mode,
682 .num_modes = 1,
683 .bpc = 6,
684 .size = {
685 .width = 195,
686 .height = 117,
687 },
688};
689
41bcceb4
NF		 690static const struct drm_display_mode innolux_at043tn24_mode = {
691 .clock = 9000,
692 .hdisplay = 480,
693 .hsync_start = 480 + 2,
694 .hsync_end = 480 + 2 + 41,
695 .htotal = 480 + 2 + 41 + 2,
696 .vdisplay = 272,
697 .vsync_start = 272 + 2,
698 .vsync_end = 272 + 2 + 11,
699 .vtotal = 272 + 2 + 11 + 2,
700 .vrefresh = 60,
701 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
702};
703
704static const struct panel_desc innolux_at043tn24 = {
705 .modes = &innolux_at043tn24_mode,
706 .num_modes = 1,
707 .bpc = 8,
708 .size = {
709 .width = 95,
710 .height = 54,
711 },
712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
713};
714
d731f661 715static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 716 .clock = 71000,
d731f661
LS		 717 .hdisplay = 1280,
718 .hsync_start = 1280 + 64,
719 .hsync_end = 1280 + 64 + 32,
720 .htotal = 1280 + 64 + 32 + 64,
721 .vdisplay = 800,
722 .vsync_start = 800 + 9,
723 .vsync_end = 800 + 9 + 6,
724 .vtotal = 800 + 9 + 6 + 9,
725 .vrefresh = 60,
726};
727
728static const struct panel_desc innolux_g121i1_l01 = {
729 .modes = &innolux_g121i1_l01_mode,
730 .num_modes = 1,
731 .bpc = 6,
732 .size = {
733 .width = 261,
734 .height = 163,
735 },
736};
737
0a2288c0 738static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 739 .clock = 76420,
0a2288c0 740 .hdisplay = 1366,
7fe8c777
DK		 741 .hsync_start = 1366 + 136,
742 .hsync_end = 1366 + 136 + 30,
743 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 744 .vdisplay = 768,
745 .vsync_start = 768 + 8,
7fe8c777
DK		 746 .vsync_end = 768 + 8 + 12,
747 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 748 .vrefresh = 60,
749 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
750};
751
752static const struct panel_desc innolux_n116bge = {
753 .modes = &innolux_n116bge_mode,
754 .num_modes = 1,
755 .bpc = 6,
756 .size = {
757 .width = 256,
758 .height = 144,
759 },
760};
761
ea44739d
AB		 762static const struct drm_display_mode innolux_n156bge_l21_mode = {
763 .clock = 69300,
764 .hdisplay = 1366,
765 .hsync_start = 1366 + 16,
766 .hsync_end = 1366 + 16 + 34,
767 .htotal = 1366 + 16 + 34 + 50,
768 .vdisplay = 768,
769 .vsync_start = 768 + 2,
770 .vsync_end = 768 + 2 + 6,
771 .vtotal = 768 + 2 + 6 + 12,
772 .vrefresh = 60,
773};
774
775static const struct panel_desc innolux_n156bge_l21 = {
776 .modes = &innolux_n156bge_l21_mode,
777 .num_modes = 1,
0208d511 778 .bpc = 6,
ea44739d
AB		 779 .size = {
780 .width = 344,
781 .height = 193,
782 },
783};
784
bccac3f1
MG		 785static const struct drm_display_mode innolux_zj070na_01p_mode = {
786 .clock = 51501,
787 .hdisplay = 1024,
788 .hsync_start = 1024 + 128,
789 .hsync_end = 1024 + 128 + 64,
790 .htotal = 1024 + 128 + 64 + 128,
791 .vdisplay = 600,
792 .vsync_start = 600 + 16,
793 .vsync_end = 600 + 16 + 4,
794 .vtotal = 600 + 16 + 4 + 16,
795 .vrefresh = 60,
796};
797
798static const struct panel_desc innolux_zj070na_01p = {
799 .modes = &innolux_zj070na_01p_mode,
800 .num_modes = 1,
801 .bpc = 6,
802 .size = {
803 .width = 1024,
804 .height = 600,
805 },
806};
807
ec7c5653
TR		 808static const struct drm_display_mode lg_lp129qe_mode = {
809 .clock = 285250,
810 .hdisplay = 2560,
811 .hsync_start = 2560 + 48,
812 .hsync_end = 2560 + 48 + 32,
813 .htotal = 2560 + 48 + 32 + 80,
814 .vdisplay = 1700,
815 .vsync_start = 1700 + 3,
816 .vsync_end = 1700 + 3 + 10,
817 .vtotal = 1700 + 3 + 10 + 36,
818 .vrefresh = 60,
819};
820
821static const struct panel_desc lg_lp129qe = {
822 .modes = &lg_lp129qe_mode,
823 .num_modes = 1,
0208d511 824 .bpc = 8,
ec7c5653
TR		 825 .size = {
826 .width = 272,
827 .height = 181,
828 },
829};
830
6d54e3d2
MD		 831static const struct drm_display_mode samsung_ltn101nt05_mode = {
832 .clock = 54030,
833 .hdisplay = 1024,
834 .hsync_start = 1024 + 24,
835 .hsync_end = 1024 + 24 + 136,
836 .htotal = 1024 + 24 + 136 + 160,
837 .vdisplay = 600,
838 .vsync_start = 600 + 3,
839 .vsync_end = 600 + 3 + 6,
840 .vtotal = 600 + 3 + 6 + 61,
841 .vrefresh = 60,
842};
843
844static const struct panel_desc samsung_ltn101nt05 = {
845 .modes = &samsung_ltn101nt05_mode,
846 .num_modes = 1,
0208d511 847 .bpc = 6,
6d54e3d2
MD		 848 .size = {
849 .width = 1024,
850 .height = 600,
851 },
852};
853
0c934306
SM		 854static const struct drm_display_mode samsung_ltn140at29_301_mode = {
855 .clock = 76300,
856 .hdisplay = 1366,
857 .hsync_start = 1366 + 64,
858 .hsync_end = 1366 + 64 + 48,
859 .htotal = 1366 + 64 + 48 + 128,
860 .vdisplay = 768,
861 .vsync_start = 768 + 2,
862 .vsync_end = 768 + 2 + 5,
863 .vtotal = 768 + 2 + 5 + 17,
864 .vrefresh = 60,
865};
866
867static const struct panel_desc samsung_ltn140at29_301 = {
868 .modes = &samsung_ltn140at29_301_mode,
869 .num_modes = 1,
870 .bpc = 6,
871 .size = {
872 .width = 320,
873 .height = 187,
874 },
875};
876
9c6615bc
BB		 877static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
878 .clock = 33300,
879 .hdisplay = 800,
880 .hsync_start = 800 + 1,
881 .hsync_end = 800 + 1 + 64,
882 .htotal = 800 + 1 + 64 + 64,
883 .vdisplay = 480,
884 .vsync_start = 480 + 1,
885 .vsync_end = 480 + 1 + 23,
886 .vtotal = 480 + 1 + 23 + 22,
887 .vrefresh = 60,
888};
889
890static const struct panel_desc shelly_sca07010_bfn_lnn = {
891 .modes = &shelly_sca07010_bfn_lnn_mode,
892 .num_modes = 1,
893 .size = {
894 .width = 152,
895 .height = 91,
896 },
897 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
898};
899
280921de
TR		 900static const struct of_device_id platform_of_match[] = {
901 {
902 .compatible = "auo,b101aw03",
903 .data = &auo_b101aw03,
a531bc3d
HL		 904 }, {
905 .compatible = "auo,b101ean01",
906 .data = &auo_b101ean01,
dac746e0
RC		 907 }, {
908 .compatible = "auo,b101xtn01",
909 .data = &auo_b101xtn01,
e35e305e
AK		 910 }, {
911 .compatible = "auo,b116xw03",
912 .data = &auo_b116xw03,
3e51d609
AK		 913 }, {
914 .compatible = "auo,b133htn01",
915 .data = &auo_b133htn01,
a333f7ad
SM		 916 }, {
917 .compatible = "auo,b133xtn01",
918 .data = &auo_b133xtn01,
d47df633
PZ		 919 }, {
920 .compatible = "avic,tm070ddh03",
921 .data = &avic_tm070ddh03,
4c930757
SW		 922 }, {
923 .compatible = "chunghwa,claa101wa01a",
924 .data = &chunghwa_claa101wa01a
280921de
TR		 925 }, {
926 .compatible = "chunghwa,claa101wb01",
927 .data = &chunghwa_claa101wb01
26ab0065
SA		 928 }, {
929 .compatible = "edt,et057090dhu",
930 .data = &edt_et057090dhu,
fff5de45
PZ		 931 }, {
932 .compatible = "edt,et070080dh6",
933 .data = &edt_etm0700g0dh6,
934 }, {
935 .compatible = "edt,etm0700g0dh6",
936 .data = &edt_etm0700g0dh6,
102932b0
BB		 937 }, {
938 .compatible = "foxlink,fl500wvr00-a0t",
939 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 940 }, {
941 .compatible = "giantplus,gpg482739qs5",
942 .data = &giantplus_gpg482739qs5
a853205e
PZ		 943 }, {
944 .compatible = "hannstar,hsd070pww1",
945 .data = &hannstar_hsd070pww1,
61ac0bf8
LS		 946 }, {
947 .compatible = "hit,tx23d38vm0caa",
948 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 949 }, {
950 .compatible = "innolux,at043tn24",
951 .data = &innolux_at043tn24,
d731f661
LS		 952 }, {
953 .compatible ="innolux,g121i1-l01",
954 .data = &innolux_g121i1_l01
0a2288c0
TR		 955 }, {
956 .compatible = "innolux,n116bge",
957 .data = &innolux_n116bge,
ea44739d
AB		 958 }, {
959 .compatible = "innolux,n156bge-l21",
960 .data = &innolux_n156bge_l21,
bccac3f1
MG		 961 }, {
962 .compatible = "innolux,zj070na-01p",
963 .data = &innolux_zj070na_01p,
ec7c5653
TR		 964 }, {
965 .compatible = "lg,lp129qe",
966 .data = &lg_lp129qe,
6d54e3d2
MD		 967 }, {
968 .compatible = "samsung,ltn101nt05",
969 .data = &samsung_ltn101nt05,
0c934306
SM		 970 }, {
971 .compatible = "samsung,ltn140at29-301",
972 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 973 }, {
974 .compatible = "shelly,sca07010-bfn-lnn",
975 .data = &shelly_sca07010_bfn_lnn,
280921de
TR		 976 }, {
977 /* sentinel */
978 }
979};
980MODULE_DEVICE_TABLE(of, platform_of_match);
981
982static int panel_simple_platform_probe(struct platform_device *pdev)
983{
984 const struct of_device_id *id;
985
986 id = of_match_node(platform_of_match, pdev->dev.of_node);
987 if (!id)
988 return -ENODEV;
989
990 return panel_simple_probe(&pdev->dev, id->data);
991}
992
993static int panel_simple_platform_remove(struct platform_device *pdev)
994{
995 return panel_simple_remove(&pdev->dev);
996}
997
d02fd93e
TR		 998static void panel_simple_platform_shutdown(struct platform_device *pdev)
999{
1000 panel_simple_shutdown(&pdev->dev);
1001}
1002
280921de
TR		 1003static struct platform_driver panel_simple_platform_driver = {
1004 .driver = {
1005 .name = "panel-simple",
280921de
TR		 1006 .of_match_table = platform_of_match,
1007 },
1008 .probe = panel_simple_platform_probe,
1009 .remove = panel_simple_platform_remove,
d02fd93e 1010 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1011};
1012
210fcd9d
TR		 1013struct panel_desc_dsi {
1014 struct panel_desc desc;
1015
462658b8 1016 unsigned long flags;
210fcd9d
TR		 1017 enum mipi_dsi_pixel_format format;
1018 unsigned int lanes;
1019};
1020
712ac1ba
AC		 1021static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1022 .clock = 71000,
1023 .hdisplay = 800,
1024 .hsync_start = 800 + 32,
1025 .hsync_end = 800 + 32 + 1,
1026 .htotal = 800 + 32 + 1 + 57,
1027 .vdisplay = 1280,
1028 .vsync_start = 1280 + 28,
1029 .vsync_end = 1280 + 28 + 1,
1030 .vtotal = 1280 + 28 + 1 + 14,
1031 .vrefresh = 60,
1032};
1033
1034static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1035 .desc = {
1036 .modes = &lg_ld070wx3_sl01_mode,
1037 .num_modes = 1,
d7a839cd 1038 .bpc = 8,
712ac1ba
AC		 1039 .size = {
1040 .width = 94,
1041 .height = 151,
1042 },
1043 },
5e4cc278 1044 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1045 .format = MIPI_DSI_FMT_RGB888,
1046 .lanes = 4,
1047};
1048
499ce85a
AC		 1049static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1050 .clock = 67000,
1051 .hdisplay = 720,
1052 .hsync_start = 720 + 12,
1053 .hsync_end = 720 + 12 + 4,
1054 .htotal = 720 + 12 + 4 + 112,
1055 .vdisplay = 1280,
1056 .vsync_start = 1280 + 8,
1057 .vsync_end = 1280 + 8 + 4,
1058 .vtotal = 1280 + 8 + 4 + 12,
1059 .vrefresh = 60,
1060};
1061
1062static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1063 .desc = {
1064 .modes = &lg_lh500wx1_sd03_mode,
1065 .num_modes = 1,
d7a839cd 1066 .bpc = 8,
499ce85a
AC		 1067 .size = {
1068 .width = 62,
1069 .height = 110,
1070 },
1071 },
1072 .flags = MIPI_DSI_MODE_VIDEO,
1073 .format = MIPI_DSI_FMT_RGB888,
1074 .lanes = 4,
1075};
1076
280921de
TR		 1077static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1078 .clock = 157200,
1079 .hdisplay = 1920,
1080 .hsync_start = 1920 + 154,
1081 .hsync_end = 1920 + 154 + 16,
1082 .htotal = 1920 + 154 + 16 + 32,
1083 .vdisplay = 1200,
1084 .vsync_start = 1200 + 17,
1085 .vsync_end = 1200 + 17 + 2,
1086 .vtotal = 1200 + 17 + 2 + 16,
1087 .vrefresh = 60,
1088};
1089
210fcd9d
TR		 1090static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1091 .desc = {
1092 .modes = &panasonic_vvx10f004b00_mode,
1093 .num_modes = 1,
d7a839cd 1094 .bpc = 8,
210fcd9d
TR		 1095 .size = {
1096 .width = 217,
1097 .height = 136,
1098 },
280921de 1099 },
5e4cc278
AC		 1100 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1101 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1102 .format = MIPI_DSI_FMT_RGB888,
1103 .lanes = 4,
1104};
1105
1106static const struct of_device_id dsi_of_match[] = {
1107 {
712ac1ba
AC		 1108 .compatible = "lg,ld070wx3-sl01",
1109 .data = &lg_ld070wx3_sl01
1110 }, {
499ce85a
AC		 1111 .compatible = "lg,lh500wx1-sd03",
1112 .data = &lg_lh500wx1_sd03
1113 }, {
210fcd9d
TR		 1114 .compatible = "panasonic,vvx10f004b00",
1115 .data = &panasonic_vvx10f004b00
1116 }, {
1117 /* sentinel */
1118 }
1119};
1120MODULE_DEVICE_TABLE(of, dsi_of_match);
1121
1122static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1123{
1124 const struct panel_desc_dsi *desc;
1125 const struct of_device_id *id;
1126 int err;
1127
1128 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1129 if (!id)
1130 return -ENODEV;
1131
1132 desc = id->data;
1133
1134 err = panel_simple_probe(&dsi->dev, &desc->desc);
1135 if (err < 0)
1136 return err;
1137
462658b8 1138 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1139 dsi->format = desc->format;
1140 dsi->lanes = desc->lanes;
1141
1142 return mipi_dsi_attach(dsi);
1143}
1144
1145static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1146{
1147 int err;
1148
1149 err = mipi_dsi_detach(dsi);
1150 if (err < 0)
1151 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1152
1153 return panel_simple_remove(&dsi->dev);
1154}
1155
d02fd93e
TR		 1156static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1157{
1158 panel_simple_shutdown(&dsi->dev);
1159}
1160
210fcd9d
TR		 1161static struct mipi_dsi_driver panel_simple_dsi_driver = {
1162 .driver = {
1163 .name = "panel-simple-dsi",
210fcd9d
TR		 1164 .of_match_table = dsi_of_match,
1165 },
1166 .probe = panel_simple_dsi_probe,
1167 .remove = panel_simple_dsi_remove,
d02fd93e 1168 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1169};
1170
1171static int __init panel_simple_init(void)
1172{
210fcd9d
TR		 1173 int err;
1174
1175 err = platform_driver_register(&panel_simple_platform_driver);
1176 if (err < 0)
1177 return err;
1178
1179 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1180 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1181 if (err < 0)
1182 return err;
1183 }
1184
1185 return 0;
280921de
TR		 1186}
1187module_init(panel_simple_init);
1188
1189static void __exit panel_simple_exit(void)
1190{
210fcd9d
TR		 1191 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1192 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1193
280921de
TR		 1194 platform_driver_unregister(&panel_simple_platform_driver);
1195}
1196module_exit(panel_simple_exit);
1197
1198MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1199MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1200MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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