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Merge branch 'for-linus' of git://neil.brown.name/md
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
63 } else if (a2 > a1) {
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
5b1714d3
AD		 70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 256 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 257 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 260 radeon_crtc->enabled = false;
d7311171
AD		 261 /* adjust pm to dpms changes AFTER disabling crtcs */
262 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 263 break;
264 }
771fe6b9
JG		 265}
266
267static void
268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 269 struct drm_display_mode *mode)
771fe6b9 270{
5a9bcacc 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 276 u16 misc = 0;
771fe6b9 277
5a9bcacc 278 memset(&args, 0, sizeof(args));
5b1714d3 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 280 args.usH_Blanking_Time =
5b1714d3
AD		 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 283 args.usV_Blanking_Time =
5b1714d3 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 285 args.usH_SyncOffset =
5b1714d3 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 287 args.usH_SyncWidth =
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
5b1714d3 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 293 args.ucH_Border = radeon_crtc->h_border;
294 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 309
5a9bcacc 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 311}
312
5a9bcacc
AD		 313static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
771fe6b9 315{
5a9bcacc 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 321 u16 misc = 0;
771fe6b9 322
5a9bcacc
AD		 323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
327 args.usH_SyncWidth =
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
345
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 348
5a9bcacc 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 350}
351
b792210e
AD		 352static void atombios_disable_ss(struct drm_crtc *crtc)
353{
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct drm_device *dev = crtc->dev;
356 struct radeon_device *rdev = dev->dev_private;
357 u32 ss_cntl;
358
359 if (ASIC_IS_DCE4(rdev)) {
360 switch (radeon_crtc->pll_id) {
361 case ATOM_PPLL1:
362 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
363 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
364 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
365 break;
366 case ATOM_PPLL2:
367 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
369 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
370 break;
371 case ATOM_DCPLL:
372 case ATOM_PPLL_INVALID:
373 return;
374 }
375 } else if (ASIC_IS_AVIVO(rdev)) {
376 switch (radeon_crtc->pll_id) {
377 case ATOM_PPLL1:
378 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
379 ss_cntl &= ~1;
380 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
381 break;
382 case ATOM_PPLL2:
383 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
384 ss_cntl &= ~1;
385 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
386 break;
387 case ATOM_DCPLL:
388 case ATOM_PPLL_INVALID:
389 return;
390 }
391 }
392}
393
394
26b9fc3a
AD		 395union atom_enable_ss {
396 ENABLE_LVDS_SS_PARAMETERS legacy;
397 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
398};
399
b792210e 400static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 401{
402 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
403 struct drm_device *dev = crtc->dev;
404 struct radeon_device *rdev = dev->dev_private;
405 struct drm_encoder *encoder = NULL;
406 struct radeon_encoder *radeon_encoder = NULL;
407 struct radeon_encoder_atom_dig *dig = NULL;
408 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 409 union atom_enable_ss args;
ebbe1cb9
AD		 410 uint16_t percentage = 0;
411 uint8_t type = 0, step = 0, delay = 0, range = 0;
412
bcc1c2a1
AD		 413 /* XXX add ss support for DCE4 */
414 if (ASIC_IS_DCE4(rdev))
415 return;
416
ebbe1cb9
AD		 417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
418 if (encoder->crtc == crtc) {
419 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 420 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 421 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
422 dig = radeon_encoder->enc_priv;
423 if (dig && dig->ss) {
424 percentage = dig->ss->percentage;
425 type = dig->ss->type;
426 step = dig->ss->step;
427 delay = dig->ss->delay;
428 range = dig->ss->range;
b792210e 429 } else
d11aa88b 430 return;
b792210e 431 } else
ebbe1cb9
AD		 432 return;
433 break;
434 }
435 }
436
437 if (!radeon_encoder)
438 return;
439
26b9fc3a 440 memset(&args, 0, sizeof(args));
ebbe1cb9 441 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 442 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
443 args.v1.ucSpreadSpectrumType = type;
444 args.v1.ucSpreadSpectrumStep = step;
445 args.v1.ucSpreadSpectrumDelay = delay;
446 args.v1.ucSpreadSpectrumRange = range;
447 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 448 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 449 } else {
26b9fc3a
AD		 450 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
451 args.legacy.ucSpreadSpectrumType = type;
452 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
453 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 454 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 455 }
26b9fc3a 456 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 457}
458
4eaeca33
AD		 459union adjust_pixel_clock {
460 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 461 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 462};
463
464static u32 atombios_adjust_pll(struct drm_crtc *crtc,
465 struct drm_display_mode *mode,
466 struct radeon_pll *pll)
771fe6b9 467{
771fe6b9
JG		 468 struct drm_device *dev = crtc->dev;
469 struct radeon_device *rdev = dev->dev_private;
470 struct drm_encoder *encoder = NULL;
471 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 472 u32 adjusted_clock = mode->clock;
bcc1c2a1 473 int encoder_mode = 0;
fc10332b 474
4eaeca33
AD		 475 /* reset the pll flags */
476 pll->flags = 0;
771fe6b9 477
7c27f87d
AD		 478 /* select the PLL algo */
479 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 480 if (radeon_new_pll == 0)
481 pll->algo = PLL_ALGO_LEGACY;
482 else
483 pll->algo = PLL_ALGO_NEW;
484 } else {
485 if (radeon_new_pll == 1)
486 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 487 else
488 pll->algo = PLL_ALGO_LEGACY;
383be5d1 489 }
7c27f87d 490
771fe6b9 491 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 492 if ((rdev->family == CHIP_RS600) ||
493 (rdev->family == CHIP_RS690) ||
494 (rdev->family == CHIP_RS740))
2ff776cf 495 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 496 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 497
771fe6b9 498 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 499 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 500 else
fc10332b 501 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 502 } else {
fc10332b 503 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 504
505 if (mode->clock > 200000) /* range limits??? */
fc10332b 506 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 507 else
fc10332b 508 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 509
510 }
511
512 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
513 if (encoder->crtc == crtc) {
4eaeca33 514 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 515 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 516 if (ASIC_IS_AVIVO(rdev)) {
517 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
518 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
519 adjusted_clock = mode->clock * 2;
a1a4b23b
AD		 520 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
521 pll->algo = PLL_ALGO_LEGACY;
522 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
523 }
4eaeca33
AD		 524 } else {
525 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 526 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 527 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 528 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 529 }
3ce0a23d 530 break;
771fe6b9
JG		 531 }
532 }
533
2606c886
AD		 534 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
535 * accordingly based on the encoder/transmitter to work around
536 * special hw requirements.
537 */
538 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 539 union adjust_pixel_clock args;
4eaeca33
AD		 540 u8 frev, crev;
541 int index;
2606c886 542
2606c886 543 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 544 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
545 &crev))
546 return adjusted_clock;
4eaeca33
AD		 547
548 memset(&args, 0, sizeof(args));
549
550 switch (frev) {
551 case 1:
552 switch (crev) {
553 case 1:
554 case 2:
555 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
556 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 557 args.v1.ucEncodeMode = encoder_mode;
4eaeca33
AD		 558
559 atom_execute_table(rdev->mode_info.atom_context,
560 index, (uint32_t *)&args);
561 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
562 break;
bcc1c2a1
AD		 563 case 3:
564 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
565 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
566 args.v3.sInput.ucEncodeMode = encoder_mode;
567 args.v3.sInput.ucDispPllConfig = 0;
568 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
569 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
570
571 if (encoder_mode == ATOM_ENCODER_MODE_DP)
572 args.v3.sInput.ucDispPllConfig |=
573 DISPPLL_CONFIG_COHERENT_MODE;
574 else {
575 if (dig->coherent_mode)
576 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE;
578 if (mode->clock > 165000)
579 args.v3.sInput.ucDispPllConfig |=
580 DISPPLL_CONFIG_DUAL_LINK;
581 }
582 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
583 /* may want to enable SS on DP/eDP eventually */
9f998ad7
AD		 584 /*args.v3.sInput.ucDispPllConfig |=
585 DISPPLL_CONFIG_SS_ENABLE;*/
586 if (encoder_mode == ATOM_ENCODER_MODE_DP)
bcc1c2a1 587 args.v3.sInput.ucDispPllConfig |=
9f998ad7
AD		 588 DISPPLL_CONFIG_COHERENT_MODE;
589 else {
590 if (mode->clock > 165000)
591 args.v3.sInput.ucDispPllConfig |=
592 DISPPLL_CONFIG_DUAL_LINK;
593 }
bcc1c2a1
AD		 594 }
595 atom_execute_table(rdev->mode_info.atom_context,
596 index, (uint32_t *)&args);
597 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
598 if (args.v3.sOutput.ucRefDiv) {
599 pll->flags |= RADEON_PLL_USE_REF_DIV;
600 pll->reference_div = args.v3.sOutput.ucRefDiv;
601 }
602 if (args.v3.sOutput.ucPostDiv) {
603 pll->flags |= RADEON_PLL_USE_POST_DIV;
604 pll->post_div = args.v3.sOutput.ucPostDiv;
605 }
606 break;
4eaeca33
AD		 607 default:
608 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
609 return adjusted_clock;
610 }
611 break;
612 default:
613 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
614 return adjusted_clock;
615 }
d56ef9c8 616 }
4eaeca33
AD		 617 return adjusted_clock;
618}
619
620union set_pixel_clock {
621 SET_PIXEL_CLOCK_PS_ALLOCATION base;
622 PIXEL_CLOCK_PARAMETERS v1;
623 PIXEL_CLOCK_PARAMETERS_V2 v2;
624 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 625 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 626};
627
bcc1c2a1
AD		 628static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
629{
630 struct drm_device *dev = crtc->dev;
631 struct radeon_device *rdev = dev->dev_private;
632 u8 frev, crev;
633 int index;
634 union set_pixel_clock args;
635
636 memset(&args, 0, sizeof(args));
637
638 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 639 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
640 &crev))
641 return;
bcc1c2a1
AD		 642
643 switch (frev) {
644 case 1:
645 switch (crev) {
646 case 5:
647 /* if the default dcpll clock is specified,
648 * SetPixelClock provides the dividers
649 */
650 args.v5.ucCRTC = ATOM_CRTC_INVALID;
651 args.v5.usPixelClock = rdev->clock.default_dispclk;
652 args.v5.ucPpll = ATOM_DCPLL;
653 break;
654 default:
655 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
656 return;
657 }
658 break;
659 default:
660 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
661 return;
662 }
663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
664}
665
37f9003b
AD		 666static void atombios_crtc_program_pll(struct drm_crtc *crtc,
667 int crtc_id,
668 int pll_id,
669 u32 encoder_mode,
670 u32 encoder_id,
671 u32 clock,
672 u32 ref_div,
673 u32 fb_div,
674 u32 frac_fb_div,
675 u32 post_div)
4eaeca33 676{
4eaeca33
AD		 677 struct drm_device *dev = crtc->dev;
678 struct radeon_device *rdev = dev->dev_private;
4eaeca33 679 u8 frev, crev;
37f9003b 680 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 681 union set_pixel_clock args;
4eaeca33
AD		 682
683 memset(&args, 0, sizeof(args));
684
a084e6ee
AD		 685 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
686 &crev))
687 return;
771fe6b9
JG		 688
689 switch (frev) {
690 case 1:
691 switch (crev) {
692 case 1:
37f9003b
AD		 693 if (clock == ATOM_DISABLE)
694 return;
695 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 696 args.v1.usRefDiv = cpu_to_le16(ref_div);
697 args.v1.usFbDiv = cpu_to_le16(fb_div);
698 args.v1.ucFracFbDiv = frac_fb_div;
699 args.v1.ucPostDiv = post_div;
37f9003b
AD		 700 args.v1.ucPpll = pll_id;
701 args.v1.ucCRTC = crtc_id;
4eaeca33 702 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 703 break;
704 case 2:
37f9003b 705 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 706 args.v2.usRefDiv = cpu_to_le16(ref_div);
707 args.v2.usFbDiv = cpu_to_le16(fb_div);
708 args.v2.ucFracFbDiv = frac_fb_div;
709 args.v2.ucPostDiv = post_div;
37f9003b
AD		 710 args.v2.ucPpll = pll_id;
711 args.v2.ucCRTC = crtc_id;
4eaeca33 712 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 713 break;
714 case 3:
37f9003b 715 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 716 args.v3.usRefDiv = cpu_to_le16(ref_div);
717 args.v3.usFbDiv = cpu_to_le16(fb_div);
718 args.v3.ucFracFbDiv = frac_fb_div;
719 args.v3.ucPostDiv = post_div;
37f9003b
AD		 720 args.v3.ucPpll = pll_id;
721 args.v3.ucMiscInfo = (pll_id << 2);
722 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 723 args.v3.ucEncoderMode = encoder_mode;
724 break;
725 case 5:
37f9003b
AD		 726 args.v5.ucCRTC = crtc_id;
727 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 728 args.v5.ucRefDiv = ref_div;
729 args.v5.usFbDiv = cpu_to_le16(fb_div);
730 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
731 args.v5.ucPostDiv = post_div;
732 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 733 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 734 args.v5.ucEncoderMode = encoder_mode;
37f9003b 735 args.v5.ucPpll = pll_id;
771fe6b9
JG		 736 break;
737 default:
738 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
739 return;
740 }
741 break;
742 default:
743 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
744 return;
745 }
746
771fe6b9
JG		 747 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
748}
749
37f9003b
AD		 750static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
751{
752 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
753 struct drm_device *dev = crtc->dev;
754 struct radeon_device *rdev = dev->dev_private;
755 struct drm_encoder *encoder = NULL;
756 struct radeon_encoder *radeon_encoder = NULL;
757 u32 pll_clock = mode->clock;
758 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
759 struct radeon_pll *pll;
760 u32 adjusted_clock;
761 int encoder_mode = 0;
762
763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
764 if (encoder->crtc == crtc) {
765 radeon_encoder = to_radeon_encoder(encoder);
766 encoder_mode = atombios_get_encoder_mode(encoder);
767 break;
768 }
769 }
770
771 if (!radeon_encoder)
772 return;
773
774 switch (radeon_crtc->pll_id) {
775 case ATOM_PPLL1:
776 pll = &rdev->clock.p1pll;
777 break;
778 case ATOM_PPLL2:
779 pll = &rdev->clock.p2pll;
780 break;
781 case ATOM_DCPLL:
782 case ATOM_PPLL_INVALID:
783 default:
784 pll = &rdev->clock.dcpll;
785 break;
786 }
787
788 /* adjust pixel clock as needed */
789 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
790
791 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
792 &ref_div, &post_div);
793
794 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
795 encoder_mode, radeon_encoder->encoder_id, mode->clock,
796 ref_div, fb_div, frac_fb_div, post_div);
797
798}
799
bcc1c2a1
AD		 800static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
801 struct drm_framebuffer *old_fb)
802{
803 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
804 struct drm_device *dev = crtc->dev;
805 struct radeon_device *rdev = dev->dev_private;
806 struct radeon_framebuffer *radeon_fb;
807 struct drm_gem_object *obj;
808 struct radeon_bo *rbo;
809 uint64_t fb_location;
810 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
811 int r;
812
813 /* no fb bound */
814 if (!crtc->fb) {
d9fdaafb 815 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 816 return 0;
817 }
818
819 radeon_fb = to_radeon_framebuffer(crtc->fb);
820
821 /* Pin framebuffer & get tilling informations */
822 obj = radeon_fb->obj;
823 rbo = obj->driver_private;
824 r = radeon_bo_reserve(rbo, false);
825 if (unlikely(r != 0))
826 return r;
827 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
828 if (unlikely(r != 0)) {
829 radeon_bo_unreserve(rbo);
830 return -EINVAL;
831 }
832 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
833 radeon_bo_unreserve(rbo);
834
835 switch (crtc->fb->bits_per_pixel) {
836 case 8:
837 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
838 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
839 break;
840 case 15:
841 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
842 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
843 break;
844 case 16:
845 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
846 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
847 break;
848 case 24:
849 case 32:
850 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
851 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
852 break;
853 default:
854 DRM_ERROR("Unsupported screen depth %d\n",
855 crtc->fb->bits_per_pixel);
856 return -EINVAL;
857 }
858
97d66328
AD		 859 if (tiling_flags & RADEON_TILING_MACRO)
860 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
861 else if (tiling_flags & RADEON_TILING_MICRO)
862 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
863
bcc1c2a1
AD		 864 switch (radeon_crtc->crtc_id) {
865 case 0:
866 WREG32(AVIVO_D1VGA_CONTROL, 0);
867 break;
868 case 1:
869 WREG32(AVIVO_D2VGA_CONTROL, 0);
870 break;
871 case 2:
872 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
873 break;
874 case 3:
875 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
876 break;
877 case 4:
878 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
879 break;
880 case 5:
881 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
882 break;
883 default:
884 break;
885 }
886
887 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
888 upper_32_bits(fb_location));
889 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
890 upper_32_bits(fb_location));
891 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
892 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
893 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
894 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
895 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
896
897 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
898 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
899 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
900 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
901 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
902 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
903
904 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
905 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
906 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
907
908 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
909 crtc->mode.vdisplay);
910 x &= ~3;
911 y &= ~1;
912 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
913 (x << 16) | y);
914 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
915 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
916
917 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
918 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
919 EVERGREEN_INTERLEAVE_EN);
920 else
921 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
922
923 if (old_fb && old_fb != crtc->fb) {
924 radeon_fb = to_radeon_framebuffer(old_fb);
925 rbo = radeon_fb->obj->driver_private;
926 r = radeon_bo_reserve(rbo, false);
927 if (unlikely(r != 0))
928 return r;
929 radeon_bo_unpin(rbo);
930 radeon_bo_unreserve(rbo);
931 }
932
933 /* Bytes per pixel may have changed */
934 radeon_bandwidth_update(rdev);
935
936 return 0;
937}
938
54f088a9
AD		 939static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
940 struct drm_framebuffer *old_fb)
771fe6b9
JG		 941{
942 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
943 struct drm_device *dev = crtc->dev;
944 struct radeon_device *rdev = dev->dev_private;
945 struct radeon_framebuffer *radeon_fb;
946 struct drm_gem_object *obj;
4c788679 947 struct radeon_bo *rbo;
771fe6b9 948 uint64_t fb_location;
e024e110 949 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 950 int r;
771fe6b9 951
2de3b484
JG		 952 /* no fb bound */
953 if (!crtc->fb) {
d9fdaafb 954 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 955 return 0;
956 }
771fe6b9
JG		 957
958 radeon_fb = to_radeon_framebuffer(crtc->fb);
959
4c788679 960 /* Pin framebuffer & get tilling informations */
771fe6b9 961 obj = radeon_fb->obj;
4c788679
JG		 962 rbo = obj->driver_private;
963 r = radeon_bo_reserve(rbo, false);
964 if (unlikely(r != 0))
965 return r;
966 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
967 if (unlikely(r != 0)) {
968 radeon_bo_unreserve(rbo);
771fe6b9
JG		 969 return -EINVAL;
970 }
4c788679
JG		 971 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
972 radeon_bo_unreserve(rbo);
771fe6b9
JG		 973
974 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 975 case 8:
976 fb_format =
977 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
978 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
979 break;
771fe6b9
JG		 980 case 15:
981 fb_format =
982 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
983 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
984 break;
985 case 16:
986 fb_format =
987 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
988 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
989 break;
990 case 24:
991 case 32:
992 fb_format =
993 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
994 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
995 break;
996 default:
997 DRM_ERROR("Unsupported screen depth %d\n",
998 crtc->fb->bits_per_pixel);
999 return -EINVAL;
1000 }
1001
40c4ac1c
AD		 1002 if (rdev->family >= CHIP_R600) {
1003 if (tiling_flags & RADEON_TILING_MACRO)
1004 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1005 else if (tiling_flags & RADEON_TILING_MICRO)
1006 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1007 } else {
1008 if (tiling_flags & RADEON_TILING_MACRO)
1009 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1010
40c4ac1c
AD		 1011 if (tiling_flags & RADEON_TILING_MICRO)
1012 fb_format |= AVIVO_D1GRPH_TILED;
1013 }
e024e110 1014
771fe6b9
JG		 1015 if (radeon_crtc->crtc_id == 0)
1016 WREG32(AVIVO_D1VGA_CONTROL, 0);
1017 else
1018 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1019
1020 if (rdev->family >= CHIP_RV770) {
1021 if (radeon_crtc->crtc_id) {
1022 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1023 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1024 } else {
1025 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1026 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1027 }
1028 }
771fe6b9
JG		 1029 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1030 (u32) fb_location);
1031 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1032 radeon_crtc->crtc_offset, (u32) fb_location);
1033 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1034
1035 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1036 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1037 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1038 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1039 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1040 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1041
1042 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1043 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1044 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1045
1046 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1047 crtc->mode.vdisplay);
1048 x &= ~3;
1049 y &= ~1;
1050 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1051 (x << 16) | y);
1052 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1053 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1054
1055 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1056 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1057 AVIVO_D1MODE_INTERLEAVE_EN);
1058 else
1059 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1060
1061 if (old_fb && old_fb != crtc->fb) {
1062 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1063 rbo = radeon_fb->obj->driver_private;
1064 r = radeon_bo_reserve(rbo, false);
1065 if (unlikely(r != 0))
1066 return r;
1067 radeon_bo_unpin(rbo);
1068 radeon_bo_unreserve(rbo);
771fe6b9 1069 }
f30f37de
MD		 1070
1071 /* Bytes per pixel may have changed */
1072 radeon_bandwidth_update(rdev);
1073
771fe6b9
JG		 1074 return 0;
1075}
1076
54f088a9
AD		 1077int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1078 struct drm_framebuffer *old_fb)
1079{
1080 struct drm_device *dev = crtc->dev;
1081 struct radeon_device *rdev = dev->dev_private;
1082
bcc1c2a1
AD		 1083 if (ASIC_IS_DCE4(rdev))
1084 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1085 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1086 return avivo_crtc_set_base(crtc, x, y, old_fb);
1087 else
1088 return radeon_crtc_set_base(crtc, x, y, old_fb);
1089}
1090
615e0cb6
AD		 1091/* properly set additional regs when using atombios */
1092static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1093{
1094 struct drm_device *dev = crtc->dev;
1095 struct radeon_device *rdev = dev->dev_private;
1096 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1097 u32 disp_merge_cntl;
1098
1099 switch (radeon_crtc->crtc_id) {
1100 case 0:
1101 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1102 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1103 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1104 break;
1105 case 1:
1106 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1107 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1108 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1109 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1110 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1111 break;
1112 }
1113}
1114
bcc1c2a1
AD		 1115static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1116{
1117 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1118 struct drm_device *dev = crtc->dev;
1119 struct radeon_device *rdev = dev->dev_private;
1120 struct drm_encoder *test_encoder;
1121 struct drm_crtc *test_crtc;
1122 uint32_t pll_in_use = 0;
1123
1124 if (ASIC_IS_DCE4(rdev)) {
1125 /* if crtc is driving DP and we have an ext clock, use that */
1126 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1127 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1128 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1129 if (rdev->clock.dp_extclk)
1130 return ATOM_PPLL_INVALID;
1131 }
1132 }
1133 }
1134
1135 /* otherwise, pick one of the plls */
1136 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1137 struct radeon_crtc *radeon_test_crtc;
1138
1139 if (crtc == test_crtc)
1140 continue;
1141
1142 radeon_test_crtc = to_radeon_crtc(test_crtc);
1143 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1144 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1145 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1146 }
1147 if (!(pll_in_use & 1))
1148 return ATOM_PPLL1;
1149 return ATOM_PPLL2;
1150 } else
1151 return radeon_crtc->crtc_id;
1152
1153}
1154
771fe6b9
JG		 1155int atombios_crtc_mode_set(struct drm_crtc *crtc,
1156 struct drm_display_mode *mode,
1157 struct drm_display_mode *adjusted_mode,
1158 int x, int y, struct drm_framebuffer *old_fb)
1159{
1160 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1161 struct drm_device *dev = crtc->dev;
1162 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1163
1164 /* TODO color tiling */
771fe6b9 1165
b792210e 1166 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1167 /* always set DCPLL */
1168 if (ASIC_IS_DCE4(rdev))
1169 atombios_crtc_set_dcpll(crtc);
771fe6b9 1170 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1171 atombios_enable_ss(crtc);
771fe6b9 1172
5b1714d3 1173 if (ASIC_IS_AVIVO(rdev))
bcc1c2a1 1174 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
771fe6b9 1175 else {
bcc1c2a1 1176 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1177 if (radeon_crtc->crtc_id == 0)
1178 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1179 radeon_legacy_atom_fixup(crtc);
771fe6b9 1180 }
bcc1c2a1 1181 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1182 atombios_overscan_setup(crtc, mode, adjusted_mode);
1183 atombios_scaler_setup(crtc);
771fe6b9
JG		 1184 return 0;
1185}
1186
1187static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1188 struct drm_display_mode *mode,
1189 struct drm_display_mode *adjusted_mode)
1190{
03214bd5
AD		 1191 struct drm_device *dev = crtc->dev;
1192 struct radeon_device *rdev = dev->dev_private;
1193
1194 /* adjust pm to upcoming mode change */
1195 radeon_pm_compute_clocks(rdev);
1196
c93bb85b
JG		 1197 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1198 return false;
771fe6b9
JG		 1199 return true;
1200}
1201
1202static void atombios_crtc_prepare(struct drm_crtc *crtc)
1203{
267364ac
AD		 1204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1205
1206 /* pick pll */
1207 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1208
37b4390e 1209 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1210 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1211}
1212
1213static void atombios_crtc_commit(struct drm_crtc *crtc)
1214{
1215 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1216 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1217}
1218
37f9003b
AD		 1219static void atombios_crtc_disable(struct drm_crtc *crtc)
1220{
1221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1222 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1223
1224 switch (radeon_crtc->pll_id) {
1225 case ATOM_PPLL1:
1226 case ATOM_PPLL2:
1227 /* disable the ppll */
1228 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1229 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1230 break;
1231 default:
1232 break;
1233 }
1234 radeon_crtc->pll_id = -1;
1235}
1236
771fe6b9
JG		 1237static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1238 .dpms = atombios_crtc_dpms,
1239 .mode_fixup = atombios_crtc_mode_fixup,
1240 .mode_set = atombios_crtc_mode_set,
1241 .mode_set_base = atombios_crtc_set_base,
1242 .prepare = atombios_crtc_prepare,
1243 .commit = atombios_crtc_commit,
068143d3 1244 .load_lut = radeon_crtc_load_lut,
37f9003b 1245 .disable = atombios_crtc_disable,
771fe6b9
JG		 1246};
1247
1248void radeon_atombios_init_crtc(struct drm_device *dev,
1249 struct radeon_crtc *radeon_crtc)
1250{
bcc1c2a1
AD		 1251 struct radeon_device *rdev = dev->dev_private;
1252
1253 if (ASIC_IS_DCE4(rdev)) {
1254 switch (radeon_crtc->crtc_id) {
1255 case 0:
1256 default:
12d7798f 1257 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1258 break;
1259 case 1:
12d7798f 1260 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1261 break;
1262 case 2:
12d7798f 1263 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1264 break;
1265 case 3:
12d7798f 1266 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1267 break;
1268 case 4:
12d7798f 1269 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1270 break;
1271 case 5:
12d7798f 1272 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1273 break;
1274 }
1275 } else {
1276 if (radeon_crtc->crtc_id == 1)
1277 radeon_crtc->crtc_offset =
1278 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1279 else
1280 radeon_crtc->crtc_offset = 0;
1281 }
1282 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1283 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1284}
Linux kernel - Deliverables
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