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Merge git://git.samba.org/sfrench/cifs-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
fef9f91f
AD		 234static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
235{
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 struct drm_device *dev = crtc->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
240 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
241
242 memset(&args, 0, sizeof(args));
243
244 args.ucDispPipeId = radeon_crtc->crtc_id;
245 args.ucEnable = state;
246
247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
248}
249
771fe6b9
JG		 250void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
251{
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
500b7587 254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 255
256 switch (mode) {
257 case DRM_MODE_DPMS_ON:
d7311171
AD		 258 radeon_crtc->enabled = true;
259 /* adjust pm to dpms changes BEFORE enabling crtcs */
260 radeon_pm_compute_clocks(rdev);
fef9f91f
AD		 261 /* disable crtc pair power gating before programming */
262 if (ASIC_IS_DCE6(rdev))
263 atombios_powergate_crtc(crtc, ATOM_DISABLE);
37b4390e 264 atombios_enable_crtc(crtc, ATOM_ENABLE);
79f17c64 265 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 266 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
267 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 268 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 269 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 270 break;
271 case DRM_MODE_DPMS_STANDBY:
272 case DRM_MODE_DPMS_SUSPEND:
273 case DRM_MODE_DPMS_OFF:
45f9a39b 274 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 275 if (radeon_crtc->enabled)
276 atombios_blank_crtc(crtc, ATOM_ENABLE);
79f17c64 277 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 278 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
279 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 280 radeon_crtc->enabled = false;
fef9f91f
AD		 281 /* power gating is per-pair */
282 if (ASIC_IS_DCE6(rdev)) {
283 struct drm_crtc *other_crtc;
284 struct radeon_crtc *other_radeon_crtc;
285 list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
286 other_radeon_crtc = to_radeon_crtc(other_crtc);
287 if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
288 ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
289 ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
290 ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
291 ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
292 ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
293 /* if both crtcs in the pair are off, enable power gating */
294 if (other_radeon_crtc->enabled == false)
295 atombios_powergate_crtc(crtc, ATOM_ENABLE);
296 break;
297 }
298 }
299 }
d7311171
AD		 300 /* adjust pm to dpms changes AFTER disabling crtcs */
301 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 302 break;
303 }
771fe6b9
JG		 304}
305
306static void
307atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 308 struct drm_display_mode *mode)
771fe6b9 309{
5a9bcacc 310 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 311 struct drm_device *dev = crtc->dev;
312 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 313 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 314 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 315 u16 misc = 0;
771fe6b9 316
5a9bcacc 317 memset(&args, 0, sizeof(args));
5b1714d3 318 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 319 args.usH_Blanking_Time =
5b1714d3
AD		 320 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
321 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 322 args.usV_Blanking_Time =
5b1714d3 323 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 324 args.usH_SyncOffset =
5b1714d3 325 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 326 args.usH_SyncWidth =
327 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
328 args.usV_SyncOffset =
5b1714d3 329 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 330 args.usV_SyncWidth =
331 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 332 args.ucH_Border = radeon_crtc->h_border;
333 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 334
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
345
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 348
5a9bcacc 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 350}
351
5a9bcacc
AD		 352static void atombios_crtc_set_timing(struct drm_crtc *crtc,
353 struct drm_display_mode *mode)
771fe6b9 354{
5a9bcacc 355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 356 struct drm_device *dev = crtc->dev;
357 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 358 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 359 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 360 u16 misc = 0;
771fe6b9 361
5a9bcacc
AD		 362 memset(&args, 0, sizeof(args));
363 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
364 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
365 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
366 args.usH_SyncWidth =
367 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
368 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
369 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
370 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
371 args.usV_SyncWidth =
372 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
373
54bfe496
AD		 374 args.ucOverscanRight = radeon_crtc->h_border;
375 args.ucOverscanLeft = radeon_crtc->h_border;
376 args.ucOverscanBottom = radeon_crtc->v_border;
377 args.ucOverscanTop = radeon_crtc->v_border;
378
5a9bcacc
AD		 379 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
380 misc |= ATOM_VSYNC_POLARITY;
381 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
382 misc |= ATOM_HSYNC_POLARITY;
383 if (mode->flags & DRM_MODE_FLAG_CSYNC)
384 misc |= ATOM_COMPOSITESYNC;
385 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
386 misc |= ATOM_INTERLACE;
387 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
388 misc |= ATOM_DOUBLE_CLOCK_MODE;
389
390 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
391 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 392
5a9bcacc 393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 394}
395
3fa47d9e 396static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
b792210e 397{
b792210e
AD		 398 u32 ss_cntl;
399
400 if (ASIC_IS_DCE4(rdev)) {
3fa47d9e 401 switch (pll_id) {
b792210e
AD		 402 case ATOM_PPLL1:
403 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
404 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
405 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
406 break;
407 case ATOM_PPLL2:
408 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
409 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
410 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
411 break;
412 case ATOM_DCPLL:
413 case ATOM_PPLL_INVALID:
414 return;
415 }
416 } else if (ASIC_IS_AVIVO(rdev)) {
3fa47d9e 417 switch (pll_id) {
b792210e
AD		 418 case ATOM_PPLL1:
419 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
420 ss_cntl &= ~1;
421 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
422 break;
423 case ATOM_PPLL2:
424 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
425 ss_cntl &= ~1;
426 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
427 break;
428 case ATOM_DCPLL:
429 case ATOM_PPLL_INVALID:
430 return;
431 }
432 }
433}
434
435
26b9fc3a 436union atom_enable_ss {
ba032a58
AD		 437 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
438 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 439 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 441 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 442};
443
3fa47d9e 444static void atombios_crtc_program_ss(struct radeon_device *rdev,
ba032a58
AD		 445 int enable,
446 int pll_id,
447 struct radeon_atom_ss *ss)
ebbe1cb9 448{
ebbe1cb9 449 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 450 union atom_enable_ss args;
ebbe1cb9 451
ba032a58 452 memset(&args, 0, sizeof(args));
bcc1c2a1 453
a572eaa3 454 if (ASIC_IS_DCE5(rdev)) {
4589433c 455 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
8e8e523d 456 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
a572eaa3
AD		 457 switch (pll_id) {
458 case ATOM_PPLL1:
459 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 460 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
461 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 462 break;
463 case ATOM_PPLL2:
464 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 465 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
466 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 467 break;
468 case ATOM_DCPLL:
469 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 470 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
471 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 472 break;
473 case ATOM_PPLL_INVALID:
474 return;
475 }
d0ae3e89 476 args.v3.ucEnable = enable;
0671bdd7 477 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
8e8e523d 478 args.v3.ucEnable = ATOM_DISABLE;
a572eaa3 479 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58 480 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 481 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 482 switch (pll_id) {
483 case ATOM_PPLL1:
484 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 485 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
486 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 487 break;
488 case ATOM_PPLL2:
489 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 490 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
491 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 492 break;
ba032a58
AD		 493 case ATOM_DCPLL:
494 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 495 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
496 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 497 break;
498 case ATOM_PPLL_INVALID:
499 return;
ebbe1cb9 500 }
ba032a58 501 args.v2.ucEnable = enable;
09cc6506 502 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
8e8e523d 503 args.v2.ucEnable = ATOM_DISABLE;
ba032a58
AD		 504 } else if (ASIC_IS_DCE3(rdev)) {
505 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 506 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 507 args.v1.ucSpreadSpectrumStep = ss->step;
508 args.v1.ucSpreadSpectrumDelay = ss->delay;
509 args.v1.ucSpreadSpectrumRange = ss->range;
510 args.v1.ucPpll = pll_id;
511 args.v1.ucEnable = enable;
512 } else if (ASIC_IS_AVIVO(rdev)) {
8e8e523d
AD		 513 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
514 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 515 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 516 return;
517 }
518 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 519 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 520 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
521 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
522 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
523 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 524 } else {
8e8e523d
AD		 525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 527 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 528 return;
529 }
530 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 531 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 532 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
533 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
534 args.lvds_ss.ucEnable = enable;
ebbe1cb9 535 }
26b9fc3a 536 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 537}
538
4eaeca33
AD		 539union adjust_pixel_clock {
540 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 541 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 542};
543
544static u32 atombios_adjust_pll(struct drm_crtc *crtc,
545 struct drm_display_mode *mode,
ba032a58
AD		 546 struct radeon_pll *pll,
547 bool ss_enabled,
548 struct radeon_atom_ss *ss)
771fe6b9 549{
771fe6b9
JG		 550 struct drm_device *dev = crtc->dev;
551 struct radeon_device *rdev = dev->dev_private;
552 struct drm_encoder *encoder = NULL;
553 struct radeon_encoder *radeon_encoder = NULL;
df271bec 554 struct drm_connector *connector = NULL;
4eaeca33 555 u32 adjusted_clock = mode->clock;
bcc1c2a1 556 int encoder_mode = 0;
fbee67a6
AD		 557 u32 dp_clock = mode->clock;
558 int bpc = 8;
9aa59993 559 bool is_duallink = false;
fc10332b 560
4eaeca33
AD		 561 /* reset the pll flags */
562 pll->flags = 0;
771fe6b9
JG		 563
564 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 565 if ((rdev->family == CHIP_RS600) ||
566 (rdev->family == CHIP_RS690) ||
567 (rdev->family == CHIP_RS740))
2ff776cf 568 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 569 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 570
571 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
572 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
573 else
574 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 575
5785e53f 576 if (rdev->family < CHIP_RV770)
9bb09fa1 577 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
37d4174d
AD		 578 /* use frac fb div on APUs */
579 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
580 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
5480f727 581 } else {
fc10332b 582 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 583
5480f727
DA		 584 if (mode->clock > 200000) /* range limits??? */
585 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
586 else
587 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 588 }
589
771fe6b9
JG		 590 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
591 if (encoder->crtc == crtc) {
4eaeca33 592 radeon_encoder = to_radeon_encoder(encoder);
df271bec 593 connector = radeon_get_connector_for_encoder(encoder);
017d213f
AD		 594 /* if (connector && connector->display_info.bpc)
595 bpc = connector->display_info.bpc; */
bcc1c2a1 596 encoder_mode = atombios_get_encoder_mode(encoder);
9aa59993 597 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
eac4dff6 598 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
1d33e1fc 599 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
fbee67a6
AD		 600 if (connector) {
601 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
602 struct radeon_connector_atom_dig *dig_connector =
603 radeon_connector->con_priv;
604
605 dp_clock = dig_connector->dp_clock;
606 }
607 }
5b40ddf8 608
ba032a58
AD		 609 /* use recommended ref_div for ss */
610 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
611 if (ss_enabled) {
612 if (ss->refdiv) {
613 pll->flags |= RADEON_PLL_USE_REF_DIV;
614 pll->reference_div = ss->refdiv;
5b40ddf8
AD		 615 if (ASIC_IS_AVIVO(rdev))
616 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
ba032a58
AD		 617 }
618 }
619 }
5b40ddf8 620
4eaeca33
AD		 621 if (ASIC_IS_AVIVO(rdev)) {
622 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
623 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
624 adjusted_clock = mode->clock * 2;
48dfaaeb 625 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 626 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
5b40ddf8
AD		 627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
628 pll->flags |= RADEON_PLL_IS_LCD;
4eaeca33
AD		 629 } else {
630 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 631 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 632 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 633 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 634 }
3ce0a23d 635 break;
771fe6b9
JG		 636 }
637 }
638
2606c886
AD		 639 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
640 * accordingly based on the encoder/transmitter to work around
641 * special hw requirements.
642 */
643 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 644 union adjust_pixel_clock args;
4eaeca33
AD		 645 u8 frev, crev;
646 int index;
2606c886 647
2606c886 648 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 649 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
650 &crev))
651 return adjusted_clock;
4eaeca33
AD		 652
653 memset(&args, 0, sizeof(args));
654
655 switch (frev) {
656 case 1:
657 switch (crev) {
658 case 1:
659 case 2:
660 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
661 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 662 args.v1.ucEncodeMode = encoder_mode;
8e8e523d 663 if (ss_enabled && ss->percentage)
fbee67a6
AD		 664 args.v1.ucConfig |=
665 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 666
667 atom_execute_table(rdev->mode_info.atom_context,
668 index, (uint32_t *)&args);
669 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
670 break;
bcc1c2a1
AD		 671 case 3:
672 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
673 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
674 args.v3.sInput.ucEncodeMode = encoder_mode;
675 args.v3.sInput.ucDispPllConfig = 0;
8e8e523d 676 if (ss_enabled && ss->percentage)
b526ce22
AD		 677 args.v3.sInput.ucDispPllConfig |=
678 DISPPLL_CONFIG_SS_ENABLE;
996d5c59 679 if (ENCODER_MODE_IS_DP(encoder_mode)) {
b4f15f80
AD		 680 args.v3.sInput.ucDispPllConfig |=
681 DISPPLL_CONFIG_COHERENT_MODE;
682 /* 16200 or 27000 */
683 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
684 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
bcc1c2a1 685 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b4f15f80
AD		 686 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
687 /* deep color support */
688 args.v3.sInput.usPixelClock =
689 cpu_to_le16((mode->clock * bpc / 8) / 10);
690 if (dig->coherent_mode)
bcc1c2a1
AD		 691 args.v3.sInput.ucDispPllConfig |=
692 DISPPLL_CONFIG_COHERENT_MODE;
9aa59993 693 if (is_duallink)
bcc1c2a1 694 args.v3.sInput.ucDispPllConfig |=
b4f15f80 695 DISPPLL_CONFIG_DUAL_LINK;
bcc1c2a1 696 }
1d33e1fc
AD		 697 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
698 ENCODER_OBJECT_ID_NONE)
699 args.v3.sInput.ucExtTransmitterID =
700 radeon_encoder_get_dp_bridge_encoder_id(encoder);
701 else
cc9f67a0
AD		 702 args.v3.sInput.ucExtTransmitterID = 0;
703
bcc1c2a1
AD		 704 atom_execute_table(rdev->mode_info.atom_context,
705 index, (uint32_t *)&args);
706 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
707 if (args.v3.sOutput.ucRefDiv) {
9f4283f4 708 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 709 pll->flags |= RADEON_PLL_USE_REF_DIV;
710 pll->reference_div = args.v3.sOutput.ucRefDiv;
711 }
712 if (args.v3.sOutput.ucPostDiv) {
9f4283f4 713 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 714 pll->flags |= RADEON_PLL_USE_POST_DIV;
715 pll->post_div = args.v3.sOutput.ucPostDiv;
716 }
717 break;
4eaeca33
AD		 718 default:
719 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
720 return adjusted_clock;
721 }
722 break;
723 default:
724 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
725 return adjusted_clock;
726 }
d56ef9c8 727 }
4eaeca33
AD		 728 return adjusted_clock;
729}
730
731union set_pixel_clock {
732 SET_PIXEL_CLOCK_PS_ALLOCATION base;
733 PIXEL_CLOCK_PARAMETERS v1;
734 PIXEL_CLOCK_PARAMETERS_V2 v2;
735 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 736 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 737 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 738};
739
f82b3ddc
AD		 740/* on DCE5, make sure the voltage is high enough to support the
741 * required disp clk.
742 */
f3f1f03e 743static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
f82b3ddc 744 u32 dispclk)
bcc1c2a1 745{
bcc1c2a1
AD		 746 u8 frev, crev;
747 int index;
748 union set_pixel_clock args;
749
750 memset(&args, 0, sizeof(args));
751
752 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 753 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
754 &crev))
755 return;
bcc1c2a1
AD		 756
757 switch (frev) {
758 case 1:
759 switch (crev) {
760 case 5:
761 /* if the default dcpll clock is specified,
762 * SetPixelClock provides the dividers
763 */
764 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 765 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 766 args.v5.ucPpll = ATOM_DCPLL;
767 break;
f82b3ddc
AD		 768 case 6:
769 /* if the default dcpll clock is specified,
770 * SetPixelClock provides the dividers
771 */
265aa6c8 772 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
729b95ef
AD		 773 if (ASIC_IS_DCE61(rdev))
774 args.v6.ucPpll = ATOM_EXT_PLL1;
775 else if (ASIC_IS_DCE6(rdev))
f3f1f03e
AD		 776 args.v6.ucPpll = ATOM_PPLL0;
777 else
778 args.v6.ucPpll = ATOM_DCPLL;
f82b3ddc 779 break;
bcc1c2a1
AD		 780 default:
781 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
782 return;
783 }
784 break;
785 default:
786 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
787 return;
788 }
789 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
790}
791
37f9003b 792static void atombios_crtc_program_pll(struct drm_crtc *crtc,
f1bece7f 793 u32 crtc_id,
37f9003b
AD		 794 int pll_id,
795 u32 encoder_mode,
796 u32 encoder_id,
797 u32 clock,
798 u32 ref_div,
799 u32 fb_div,
800 u32 frac_fb_div,
df271bec 801 u32 post_div,
8e8e523d
AD		 802 int bpc,
803 bool ss_enabled,
804 struct radeon_atom_ss *ss)
4eaeca33 805{
4eaeca33
AD		 806 struct drm_device *dev = crtc->dev;
807 struct radeon_device *rdev = dev->dev_private;
4eaeca33 808 u8 frev, crev;
37f9003b 809 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 810 union set_pixel_clock args;
4eaeca33
AD		 811
812 memset(&args, 0, sizeof(args));
813
a084e6ee
AD		 814 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
815 &crev))
816 return;
771fe6b9
JG		 817
818 switch (frev) {
819 case 1:
820 switch (crev) {
821 case 1:
37f9003b
AD		 822 if (clock == ATOM_DISABLE)
823 return;
824 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 825 args.v1.usRefDiv = cpu_to_le16(ref_div);
826 args.v1.usFbDiv = cpu_to_le16(fb_div);
827 args.v1.ucFracFbDiv = frac_fb_div;
828 args.v1.ucPostDiv = post_div;
37f9003b
AD		 829 args.v1.ucPpll = pll_id;
830 args.v1.ucCRTC = crtc_id;
4eaeca33 831 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 832 break;
833 case 2:
37f9003b 834 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 835 args.v2.usRefDiv = cpu_to_le16(ref_div);
836 args.v2.usFbDiv = cpu_to_le16(fb_div);
837 args.v2.ucFracFbDiv = frac_fb_div;
838 args.v2.ucPostDiv = post_div;
37f9003b
AD		 839 args.v2.ucPpll = pll_id;
840 args.v2.ucCRTC = crtc_id;
4eaeca33 841 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 842 break;
843 case 3:
37f9003b 844 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 845 args.v3.usRefDiv = cpu_to_le16(ref_div);
846 args.v3.usFbDiv = cpu_to_le16(fb_div);
847 args.v3.ucFracFbDiv = frac_fb_div;
848 args.v3.ucPostDiv = post_div;
37f9003b
AD		 849 args.v3.ucPpll = pll_id;
850 args.v3.ucMiscInfo = (pll_id << 2);
6f15c506
AD		 851 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
852 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
37f9003b 853 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 854 args.v3.ucEncoderMode = encoder_mode;
855 break;
856 case 5:
37f9003b
AD		 857 args.v5.ucCRTC = crtc_id;
858 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 859 args.v5.ucRefDiv = ref_div;
860 args.v5.usFbDiv = cpu_to_le16(fb_div);
861 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
862 args.v5.ucPostDiv = post_div;
863 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 864 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
865 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
df271bec
AD		 866 switch (bpc) {
867 case 8:
868 default:
869 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
870 break;
871 case 10:
872 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
873 break;
874 }
37f9003b 875 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 876 args.v5.ucEncoderMode = encoder_mode;
37f9003b 877 args.v5.ucPpll = pll_id;
771fe6b9 878 break;
f82b3ddc 879 case 6:
f1bece7f 880 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
f82b3ddc
AD		 881 args.v6.ucRefDiv = ref_div;
882 args.v6.usFbDiv = cpu_to_le16(fb_div);
883 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
884 args.v6.ucPostDiv = post_div;
885 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 886 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
887 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
df271bec
AD		 888 switch (bpc) {
889 case 8:
890 default:
891 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
892 break;
893 case 10:
894 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
895 break;
896 case 12:
897 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
898 break;
899 case 16:
900 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
901 break;
902 }
f82b3ddc
AD		 903 args.v6.ucTransmitterID = encoder_id;
904 args.v6.ucEncoderMode = encoder_mode;
905 args.v6.ucPpll = pll_id;
906 break;
771fe6b9
JG		 907 default:
908 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
909 return;
910 }
911 break;
912 default:
913 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
914 return;
915 }
916
771fe6b9
JG		 917 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
918}
919
37f9003b
AD		 920static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
921{
922 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
923 struct drm_device *dev = crtc->dev;
924 struct radeon_device *rdev = dev->dev_private;
925 struct drm_encoder *encoder = NULL;
926 struct radeon_encoder *radeon_encoder = NULL;
927 u32 pll_clock = mode->clock;
928 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
929 struct radeon_pll *pll;
930 u32 adjusted_clock;
931 int encoder_mode = 0;
ba032a58
AD		 932 struct radeon_atom_ss ss;
933 bool ss_enabled = false;
df271bec 934 int bpc = 8;
37f9003b
AD		 935
936 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
937 if (encoder->crtc == crtc) {
938 radeon_encoder = to_radeon_encoder(encoder);
939 encoder_mode = atombios_get_encoder_mode(encoder);
940 break;
941 }
942 }
943
944 if (!radeon_encoder)
945 return;
946
947 switch (radeon_crtc->pll_id) {
948 case ATOM_PPLL1:
949 pll = &rdev->clock.p1pll;
950 break;
951 case ATOM_PPLL2:
952 pll = &rdev->clock.p2pll;
953 break;
954 case ATOM_DCPLL:
955 case ATOM_PPLL_INVALID:
956 default:
957 pll = &rdev->clock.dcpll;
958 break;
959 }
960
ba032a58
AD		 961 if (radeon_encoder->active_device &
962 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
963 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
964 struct drm_connector *connector =
965 radeon_get_connector_for_encoder(encoder);
966 struct radeon_connector *radeon_connector =
967 to_radeon_connector(connector);
968 struct radeon_connector_atom_dig *dig_connector =
969 radeon_connector->con_priv;
970 int dp_clock;
017d213f
AD		 971
972 /* if (connector->display_info.bpc)
973 bpc = connector->display_info.bpc; */
ba032a58
AD		 974
975 switch (encoder_mode) {
996d5c59 976 case ATOM_ENCODER_MODE_DP_MST:
ba032a58
AD		 977 case ATOM_ENCODER_MODE_DP:
978 /* DP/eDP */
979 dp_clock = dig_connector->dp_clock / 10;
2307790f
AD		 980 if (ASIC_IS_DCE4(rdev))
981 ss_enabled =
982 radeon_atombios_get_asic_ss_info(rdev, &ss,
983 ASIC_INTERNAL_SS_ON_DP,
984 dp_clock);
985 else {
986 if (dp_clock == 16200) {
ba032a58 987 ss_enabled =
2307790f
AD		 988 radeon_atombios_get_ppll_ss_info(rdev, &ss,
989 ATOM_DP_SS_ID2);
8e8e523d
AD		 990 if (!ss_enabled)
991 ss_enabled =
2307790f
AD		 992 radeon_atombios_get_ppll_ss_info(rdev, &ss,
993 ATOM_DP_SS_ID1);
8e8e523d 994 } else
ba032a58
AD		 995 ss_enabled =
996 radeon_atombios_get_ppll_ss_info(rdev, &ss,
2307790f 997 ATOM_DP_SS_ID1);
ba032a58
AD		 998 }
999 break;
1000 case ATOM_ENCODER_MODE_LVDS:
1001 if (ASIC_IS_DCE4(rdev))
1002 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1003 dig->lcd_ss_id,
1004 mode->clock / 10);
1005 else
1006 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
1007 dig->lcd_ss_id);
1008 break;
1009 case ATOM_ENCODER_MODE_DVI:
1010 if (ASIC_IS_DCE4(rdev))
1011 ss_enabled =
1012 radeon_atombios_get_asic_ss_info(rdev, &ss,
1013 ASIC_INTERNAL_SS_ON_TMDS,
1014 mode->clock / 10);
1015 break;
1016 case ATOM_ENCODER_MODE_HDMI:
1017 if (ASIC_IS_DCE4(rdev))
1018 ss_enabled =
1019 radeon_atombios_get_asic_ss_info(rdev, &ss,
1020 ASIC_INTERNAL_SS_ON_HDMI,
1021 mode->clock / 10);
1022 break;
1023 default:
1024 break;
1025 }
1026 }
1027
37f9003b 1028 /* adjust pixel clock as needed */
ba032a58 1029 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 1030
64146f8b
AD		 1031 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1032 /* TV seems to prefer the legacy algo on some boards */
1033 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1034 &ref_div, &post_div);
1035 else if (ASIC_IS_AVIVO(rdev))
619efb10
AD		 1036 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1037 &ref_div, &post_div);
1038 else
1039 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1040 &ref_div, &post_div);
37f9003b 1041
3fa47d9e 1042 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
ba032a58 1043
37f9003b
AD		 1044 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1045 encoder_mode, radeon_encoder->encoder_id, mode->clock,
8e8e523d 1046 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
37f9003b 1047
ba032a58
AD		 1048 if (ss_enabled) {
1049 /* calculate ss amount and step size */
1050 if (ASIC_IS_DCE4(rdev)) {
1051 u32 step_size;
1052 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1053 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
8e8e523d 1054 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ba032a58
AD		 1055 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1056 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1057 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1058 (125 * 25 * pll->reference_freq / 100);
1059 else
1060 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1061 (125 * 25 * pll->reference_freq / 100);
1062 ss.step = step_size;
1063 }
1064
3fa47d9e 1065 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
ba032a58 1066 }
37f9003b
AD		 1067}
1068
c9417bdd
AD		 1069static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1070 struct drm_framebuffer *fb,
1071 int x, int y, int atomic)
bcc1c2a1
AD		 1072{
1073 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1074 struct drm_device *dev = crtc->dev;
1075 struct radeon_device *rdev = dev->dev_private;
1076 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1077 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1078 struct drm_gem_object *obj;
1079 struct radeon_bo *rbo;
1080 uint64_t fb_location;
1081 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
285484e2 1082 unsigned bankw, bankh, mtaspect, tile_split;
fa6bee46 1083 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
adcfde51 1084 u32 tmp, viewport_w, viewport_h;
bcc1c2a1
AD		 1085 int r;
1086
1087 /* no fb bound */
4dd19b0d 1088 if (!atomic && !crtc->fb) {
d9fdaafb 1089 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1090 return 0;
1091 }
1092
4dd19b0d
CB		 1093 if (atomic) {
1094 radeon_fb = to_radeon_framebuffer(fb);
1095 target_fb = fb;
1096 }
1097 else {
1098 radeon_fb = to_radeon_framebuffer(crtc->fb);
1099 target_fb = crtc->fb;
1100 }
bcc1c2a1 1101
4dd19b0d
CB		 1102 /* If atomic, assume fb object is pinned & idle & fenced and
1103 * just update base pointers
1104 */
bcc1c2a1 1105 obj = radeon_fb->obj;
7e4d15d9 1106 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1107 r = radeon_bo_reserve(rbo, false);
1108 if (unlikely(r != 0))
1109 return r;
4dd19b0d
CB		 1110
1111 if (atomic)
1112 fb_location = radeon_bo_gpu_offset(rbo);
1113 else {
1114 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1115 if (unlikely(r != 0)) {
1116 radeon_bo_unreserve(rbo);
1117 return -EINVAL;
1118 }
bcc1c2a1 1119 }
4dd19b0d 1120
bcc1c2a1
AD		 1121 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1122 radeon_bo_unreserve(rbo);
1123
4dd19b0d 1124 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1125 case 8:
1126 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1127 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1128 break;
1129 case 15:
1130 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1131 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1132 break;
1133 case 16:
1134 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1135 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1136#ifdef __BIG_ENDIAN
1137 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1138#endif
bcc1c2a1
AD		 1139 break;
1140 case 24:
1141 case 32:
1142 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1143 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1144#ifdef __BIG_ENDIAN
1145 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1146#endif
bcc1c2a1
AD		 1147 break;
1148 default:
1149 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1150 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1151 return -EINVAL;
1152 }
1153
392e3722
AD		 1154 if (tiling_flags & RADEON_TILING_MACRO) {
1155 if (rdev->family >= CHIP_CAYMAN)
1156 tmp = rdev->config.cayman.tile_config;
1157 else
1158 tmp = rdev->config.evergreen.tile_config;
1159
1160 switch ((tmp & 0xf0) >> 4) {
1161 case 0: /* 4 banks */
1162 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1163 break;
1164 case 1: /* 8 banks */
1165 default:
1166 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1167 break;
1168 case 2: /* 16 banks */
1169 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1170 break;
1171 }
1172
97d66328 1173 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
285484e2
JG		 1174
1175 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1176 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1177 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1178 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1179 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
392e3722 1180 } else if (tiling_flags & RADEON_TILING_MICRO)
97d66328
AD		 1181 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1182
bcc1c2a1
AD		 1183 switch (radeon_crtc->crtc_id) {
1184 case 0:
1185 WREG32(AVIVO_D1VGA_CONTROL, 0);
1186 break;
1187 case 1:
1188 WREG32(AVIVO_D2VGA_CONTROL, 0);
1189 break;
1190 case 2:
1191 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1192 break;
1193 case 3:
1194 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1195 break;
1196 case 4:
1197 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1198 break;
1199 case 5:
1200 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1201 break;
1202 default:
1203 break;
1204 }
1205
1206 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1207 upper_32_bits(fb_location));
1208 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1209 upper_32_bits(fb_location));
1210 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1211 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1212 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1213 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1214 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1215 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1216
1217 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1218 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1219 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1220 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1221 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1222 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1223
01f2c773 1224 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1225 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1226 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1227
1228 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1229 target_fb->height);
bcc1c2a1
AD		 1230 x &= ~3;
1231 y &= ~1;
1232 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1233 (x << 16) | y);
adcfde51
AD		 1234 viewport_w = crtc->mode.hdisplay;
1235 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
bcc1c2a1 1236 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1237 (viewport_w << 16) | viewport_h);
bcc1c2a1 1238
fb9674bd
AD		 1239 /* pageflip setup */
1240 /* make sure flip is at vb rather than hb */
1241 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1242 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1243 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1244
1245 /* set pageflip to happen anywhere in vblank interval */
1246 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1247
4dd19b0d
CB		 1248 if (!atomic && fb && fb != crtc->fb) {
1249 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1250 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1251 r = radeon_bo_reserve(rbo, false);
1252 if (unlikely(r != 0))
1253 return r;
1254 radeon_bo_unpin(rbo);
1255 radeon_bo_unreserve(rbo);
1256 }
1257
1258 /* Bytes per pixel may have changed */
1259 radeon_bandwidth_update(rdev);
1260
1261 return 0;
1262}
1263
4dd19b0d
CB		 1264static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1265 struct drm_framebuffer *fb,
1266 int x, int y, int atomic)
771fe6b9
JG		 1267{
1268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1269 struct drm_device *dev = crtc->dev;
1270 struct radeon_device *rdev = dev->dev_private;
1271 struct radeon_framebuffer *radeon_fb;
1272 struct drm_gem_object *obj;
4c788679 1273 struct radeon_bo *rbo;
4dd19b0d 1274 struct drm_framebuffer *target_fb;
771fe6b9 1275 uint64_t fb_location;
e024e110 1276 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1277 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
adcfde51 1278 u32 tmp, viewport_w, viewport_h;
4c788679 1279 int r;
771fe6b9 1280
2de3b484 1281 /* no fb bound */
4dd19b0d 1282 if (!atomic && !crtc->fb) {
d9fdaafb 1283 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1284 return 0;
1285 }
771fe6b9 1286
4dd19b0d
CB		 1287 if (atomic) {
1288 radeon_fb = to_radeon_framebuffer(fb);
1289 target_fb = fb;
1290 }
1291 else {
1292 radeon_fb = to_radeon_framebuffer(crtc->fb);
1293 target_fb = crtc->fb;
1294 }
771fe6b9
JG		 1295
1296 obj = radeon_fb->obj;
7e4d15d9 1297 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1298 r = radeon_bo_reserve(rbo, false);
1299 if (unlikely(r != 0))
1300 return r;
4dd19b0d
CB		 1301
1302 /* If atomic, assume fb object is pinned & idle & fenced and
1303 * just update base pointers
1304 */
1305 if (atomic)
1306 fb_location = radeon_bo_gpu_offset(rbo);
1307 else {
1308 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1309 if (unlikely(r != 0)) {
1310 radeon_bo_unreserve(rbo);
1311 return -EINVAL;
1312 }
771fe6b9 1313 }
4c788679
JG		 1314 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1315 radeon_bo_unreserve(rbo);
771fe6b9 1316
4dd19b0d 1317 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1318 case 8:
1319 fb_format =
1320 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1321 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1322 break;
771fe6b9
JG		 1323 case 15:
1324 fb_format =
1325 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1326 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1327 break;
1328 case 16:
1329 fb_format =
1330 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1331 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1332#ifdef __BIG_ENDIAN
1333 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1334#endif
771fe6b9
JG		 1335 break;
1336 case 24:
1337 case 32:
1338 fb_format =
1339 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1340 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1341#ifdef __BIG_ENDIAN
1342 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1343#endif
771fe6b9
JG		 1344 break;
1345 default:
1346 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1347 target_fb->bits_per_pixel);
771fe6b9
JG		 1348 return -EINVAL;
1349 }
1350
40c4ac1c
AD		 1351 if (rdev->family >= CHIP_R600) {
1352 if (tiling_flags & RADEON_TILING_MACRO)
1353 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1354 else if (tiling_flags & RADEON_TILING_MICRO)
1355 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1356 } else {
1357 if (tiling_flags & RADEON_TILING_MACRO)
1358 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1359
40c4ac1c
AD		 1360 if (tiling_flags & RADEON_TILING_MICRO)
1361 fb_format |= AVIVO_D1GRPH_TILED;
1362 }
e024e110 1363
771fe6b9
JG		 1364 if (radeon_crtc->crtc_id == 0)
1365 WREG32(AVIVO_D1VGA_CONTROL, 0);
1366 else
1367 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1368
1369 if (rdev->family >= CHIP_RV770) {
1370 if (radeon_crtc->crtc_id) {
95347871
AD		 1371 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1373 } else {
95347871
AD		 1374 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1376 }
1377 }
771fe6b9
JG		 1378 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1379 (u32) fb_location);
1380 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1381 radeon_crtc->crtc_offset, (u32) fb_location);
1382 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1383 if (rdev->family >= CHIP_R600)
1384 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1385
1386 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1387 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1388 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1389 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1390 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1391 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1392
01f2c773 1393 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1394 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1395 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1396
1397 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1398 target_fb->height);
771fe6b9
JG		 1399 x &= ~3;
1400 y &= ~1;
1401 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1402 (x << 16) | y);
adcfde51
AD		 1403 viewport_w = crtc->mode.hdisplay;
1404 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
771fe6b9 1405 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1406 (viewport_w << 16) | viewport_h);
771fe6b9 1407
fb9674bd
AD		 1408 /* pageflip setup */
1409 /* make sure flip is at vb rather than hb */
1410 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1411 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1412 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1413
1414 /* set pageflip to happen anywhere in vblank interval */
1415 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1416
4dd19b0d
CB		 1417 if (!atomic && fb && fb != crtc->fb) {
1418 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1419 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1420 r = radeon_bo_reserve(rbo, false);
1421 if (unlikely(r != 0))
1422 return r;
1423 radeon_bo_unpin(rbo);
1424 radeon_bo_unreserve(rbo);
771fe6b9 1425 }
f30f37de
MD		 1426
1427 /* Bytes per pixel may have changed */
1428 radeon_bandwidth_update(rdev);
1429
771fe6b9
JG		 1430 return 0;
1431}
1432
54f088a9
AD		 1433int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1434 struct drm_framebuffer *old_fb)
1435{
1436 struct drm_device *dev = crtc->dev;
1437 struct radeon_device *rdev = dev->dev_private;
1438
bcc1c2a1 1439 if (ASIC_IS_DCE4(rdev))
c9417bdd 1440 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1441 else if (ASIC_IS_AVIVO(rdev))
1442 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1443 else
1444 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1445}
1446
1447int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1448 struct drm_framebuffer *fb,
21c74a8e 1449 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1450{
1451 struct drm_device *dev = crtc->dev;
1452 struct radeon_device *rdev = dev->dev_private;
1453
1454 if (ASIC_IS_DCE4(rdev))
c9417bdd 1455 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1456 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1457 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1458 else
4dd19b0d 1459 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1460}
1461
615e0cb6
AD		 1462/* properly set additional regs when using atombios */
1463static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1464{
1465 struct drm_device *dev = crtc->dev;
1466 struct radeon_device *rdev = dev->dev_private;
1467 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1468 u32 disp_merge_cntl;
1469
1470 switch (radeon_crtc->crtc_id) {
1471 case 0:
1472 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1473 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1474 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1475 break;
1476 case 1:
1477 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1478 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1479 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1480 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1481 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1482 break;
1483 }
1484}
1485
bcc1c2a1
AD		 1486static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1487{
1488 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1489 struct drm_device *dev = crtc->dev;
1490 struct radeon_device *rdev = dev->dev_private;
1491 struct drm_encoder *test_encoder;
1492 struct drm_crtc *test_crtc;
1493 uint32_t pll_in_use = 0;
1494
24e1f794
AD		 1495 if (ASIC_IS_DCE61(rdev)) {
1496 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1497 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1498 struct radeon_encoder *test_radeon_encoder =
1499 to_radeon_encoder(test_encoder);
1500 struct radeon_encoder_atom_dig *dig =
1501 test_radeon_encoder->enc_priv;
1502
1503 if ((test_radeon_encoder->encoder_id ==
1504 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1505 (dig->linkb == false)) /* UNIPHY A uses PPLL2 */
1506 return ATOM_PPLL2;
1507 }
1508 }
1509 /* UNIPHY B/C/D/E/F */
1510 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1511 struct radeon_crtc *radeon_test_crtc;
1512
1513 if (crtc == test_crtc)
1514 continue;
1515
1516 radeon_test_crtc = to_radeon_crtc(test_crtc);
1517 if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1518 (radeon_test_crtc->pll_id == ATOM_PPLL1))
1519 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1520 }
1521 if (!(pll_in_use & 4))
1522 return ATOM_PPLL0;
1523 return ATOM_PPLL1;
1524 } else if (ASIC_IS_DCE4(rdev)) {
bcc1c2a1
AD		 1525 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1526 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
86a94def
AD		 1527 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1528 * depending on the asic:
1529 * DCE4: PPLL or ext clock
1530 * DCE5: DCPLL or ext clock
1531 *
1532 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1533 * PPLL/DCPLL programming and only program the DP DTO for the
1534 * crtc virtual pixel clock.
1535 */
996d5c59 1536 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
86a94def 1537 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
bcc1c2a1
AD		 1538 return ATOM_PPLL_INVALID;
1539 }
1540 }
1541 }
1542
1543 /* otherwise, pick one of the plls */
1544 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1545 struct radeon_crtc *radeon_test_crtc;
1546
1547 if (crtc == test_crtc)
1548 continue;
1549
1550 radeon_test_crtc = to_radeon_crtc(test_crtc);
1551 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1552 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1553 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1554 }
1555 if (!(pll_in_use & 1))
1556 return ATOM_PPLL1;
1557 return ATOM_PPLL2;
1558 } else
1559 return radeon_crtc->crtc_id;
1560
1561}
1562
f3f1f03e 1563void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
3fa47d9e
AD		 1564{
1565 /* always set DCPLL */
f3f1f03e
AD		 1566 if (ASIC_IS_DCE6(rdev))
1567 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1568 else if (ASIC_IS_DCE4(rdev)) {
3fa47d9e
AD		 1569 struct radeon_atom_ss ss;
1570 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1571 ASIC_INTERNAL_SS_ON_DCPLL,
1572 rdev->clock.default_dispclk);
1573 if (ss_enabled)
1574 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
1575 /* XXX: DCE5, make sure voltage, dispclk is high enough */
f3f1f03e 1576 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
3fa47d9e
AD		 1577 if (ss_enabled)
1578 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
1579 }
1580
1581}
1582
771fe6b9
JG		 1583int atombios_crtc_mode_set(struct drm_crtc *crtc,
1584 struct drm_display_mode *mode,
1585 struct drm_display_mode *adjusted_mode,
1586 int x, int y, struct drm_framebuffer *old_fb)
1587{
1588 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1589 struct drm_device *dev = crtc->dev;
1590 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1591 struct drm_encoder *encoder;
1592 bool is_tvcv = false;
771fe6b9 1593
54bfe496
AD		 1594 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1595 /* find tv std */
1596 if (encoder->crtc == crtc) {
1597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1598 if (radeon_encoder->active_device &
1599 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1600 is_tvcv = true;
1601 }
1602 }
771fe6b9
JG		 1603
1604 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1605
54bfe496 1606 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1607 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1608 else if (ASIC_IS_AVIVO(rdev)) {
1609 if (is_tvcv)
1610 atombios_crtc_set_timing(crtc, adjusted_mode);
1611 else
1612 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1613 } else {
bcc1c2a1 1614 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1615 if (radeon_crtc->crtc_id == 0)
1616 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1617 radeon_legacy_atom_fixup(crtc);
771fe6b9 1618 }
bcc1c2a1 1619 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1620 atombios_overscan_setup(crtc, mode, adjusted_mode);
1621 atombios_scaler_setup(crtc);
771fe6b9
JG		 1622 return 0;
1623}
1624
1625static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1626 struct drm_display_mode *mode,
1627 struct drm_display_mode *adjusted_mode)
1628{
c93bb85b
JG		 1629 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1630 return false;
771fe6b9
JG		 1631 return true;
1632}
1633
1634static void atombios_crtc_prepare(struct drm_crtc *crtc)
1635{
267364ac
AD		 1636 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1637
1638 /* pick pll */
1639 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1640
37b4390e 1641 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1642 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1643}
1644
1645static void atombios_crtc_commit(struct drm_crtc *crtc)
1646{
1647 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1648 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1649}
1650
37f9003b
AD		 1651static void atombios_crtc_disable(struct drm_crtc *crtc)
1652{
1653 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
64199870
AD		 1654 struct drm_device *dev = crtc->dev;
1655 struct radeon_device *rdev = dev->dev_private;
8e8e523d
AD		 1656 struct radeon_atom_ss ss;
1657
37f9003b
AD		 1658 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1659
1660 switch (radeon_crtc->pll_id) {
1661 case ATOM_PPLL1:
1662 case ATOM_PPLL2:
1663 /* disable the ppll */
1664 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
8e8e523d 1665 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
37f9003b 1666 break;
64199870
AD		 1667 case ATOM_PPLL0:
1668 /* disable the ppll */
1669 if (ASIC_IS_DCE61(rdev))
1670 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1671 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1672 break;
37f9003b
AD		 1673 default:
1674 break;
1675 }
1676 radeon_crtc->pll_id = -1;
1677}
1678
771fe6b9
JG		 1679static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1680 .dpms = atombios_crtc_dpms,
1681 .mode_fixup = atombios_crtc_mode_fixup,
1682 .mode_set = atombios_crtc_mode_set,
1683 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1684 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1685 .prepare = atombios_crtc_prepare,
1686 .commit = atombios_crtc_commit,
068143d3 1687 .load_lut = radeon_crtc_load_lut,
37f9003b 1688 .disable = atombios_crtc_disable,
771fe6b9
JG		 1689};
1690
1691void radeon_atombios_init_crtc(struct drm_device *dev,
1692 struct radeon_crtc *radeon_crtc)
1693{
bcc1c2a1
AD		 1694 struct radeon_device *rdev = dev->dev_private;
1695
1696 if (ASIC_IS_DCE4(rdev)) {
1697 switch (radeon_crtc->crtc_id) {
1698 case 0:
1699 default:
12d7798f 1700 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1701 break;
1702 case 1:
12d7798f 1703 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1704 break;
1705 case 2:
12d7798f 1706 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1707 break;
1708 case 3:
12d7798f 1709 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1710 break;
1711 case 4:
12d7798f 1712 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1713 break;
1714 case 5:
12d7798f 1715 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1716 break;
1717 }
1718 } else {
1719 if (radeon_crtc->crtc_id == 1)
1720 radeon_crtc->crtc_offset =
1721 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1722 else
1723 radeon_crtc->crtc_offset = 0;
1724 }
1725 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1726 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1727}
Linux kernel - Deliverables
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