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drm/radeon/kms/pm: add support for no display power states
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
68 } else if (a2 > a1) {
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break;
82 }
83}
84
85static void atombios_scaler_setup(struct drm_crtc *crtc)
86{
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 92
c93bb85b
JG		 93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
c93bb85b
JG		 97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
4ce001ab
DA		 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
102 /* find tv std */
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
108 is_tv = true;
109 }
110 }
111 }
112
c93bb85b
JG		 113 memset(&args, 0, sizeof(args));
114
115 args.ucScaler = radeon_crtc->crtc_id;
116
4ce001ab 117 if (is_tv) {
c93bb85b
JG		 118 switch (tv_std) {
119 case TV_STD_NTSC:
120 default:
121 args.ucTVStandard = ATOM_TV_NTSC;
122 break;
123 case TV_STD_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_PAL_M:
127 args.ucTVStandard = ATOM_TV_PALM;
128 break;
129 case TV_STD_PAL_60:
130 args.ucTVStandard = ATOM_TV_PAL60;
131 break;
132 case TV_STD_NTSC_J:
133 args.ucTVStandard = ATOM_TV_NTSCJ;
134 break;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
137 break;
138 case TV_STD_SECAM:
139 args.ucTVStandard = ATOM_TV_SECAM;
140 break;
141 case TV_STD_PAL_CN:
142 args.ucTVStandard = ATOM_TV_PALCN;
143 break;
144 }
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 146 } else if (is_cv) {
c93bb85b
JG		 147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
149 } else {
150 switch (radeon_crtc->rmx_type) {
151 case RMX_FULL:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 case RMX_CENTER:
155 args.ucEnable = ATOM_SCALER_CENTER;
156 break;
157 case RMX_ASPECT:
158 args.ucEnable = ATOM_SCALER_EXPANSION;
159 break;
160 default:
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
163 else
164 args.ucEnable = ATOM_SCALER_CENTER;
165 break;
166 }
167 }
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 169 if ((is_tv || is_cv)
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 172 }
173}
174
771fe6b9
JG		 175static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
176{
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int index =
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
183
184 memset(&args, 0, sizeof(args));
185
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
188
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
190}
191
192static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
193{
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
199
200 memset(&args, 0, sizeof(args));
201
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
204
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
206}
207
208static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209{
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
215
216 memset(&args, 0, sizeof(args));
217
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
220
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
222}
223
224static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
231
232 memset(&args, 0, sizeof(args));
233
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
236
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
238}
239
240void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
500b7587 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 245
246 switch (mode) {
247 case DRM_MODE_DPMS_ON:
d7311171
AD		 248 radeon_crtc->enabled = true;
249 /* adjust pm to dpms changes BEFORE enabling crtcs */
250 radeon_pm_compute_clocks(rdev);
37b4390e 251 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 252 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 253 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
254 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 255 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 256 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 257 break;
258 case DRM_MODE_DPMS_STANDBY:
259 case DRM_MODE_DPMS_SUSPEND:
260 case DRM_MODE_DPMS_OFF:
45f9a39b 261 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 262 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 263 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 264 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
265 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 266 radeon_crtc->enabled = false;
d7311171
AD		 267 /* adjust pm to dpms changes AFTER disabling crtcs */
268 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 269 break;
270 }
771fe6b9
JG		 271}
272
273static void
274atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 275 struct drm_display_mode *mode)
771fe6b9 276{
5a9bcacc 277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 278 struct drm_device *dev = crtc->dev;
279 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 280 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 281 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 282 u16 misc = 0;
771fe6b9 283
5a9bcacc
AD		 284 memset(&args, 0, sizeof(args));
285 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
286 args.usH_Blanking_Time =
287 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
288 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
289 args.usV_Blanking_Time =
290 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
291 args.usH_SyncOffset =
292 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
293 args.usH_SyncWidth =
294 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
295 args.usV_SyncOffset =
296 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
297 args.usV_SyncWidth =
298 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
299 /*args.ucH_Border = mode->hborder;*/
300 /*args.ucV_Border = mode->vborder;*/
301
302 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
303 misc |= ATOM_VSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
305 misc |= ATOM_HSYNC_POLARITY;
306 if (mode->flags & DRM_MODE_FLAG_CSYNC)
307 misc |= ATOM_COMPOSITESYNC;
308 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
309 misc |= ATOM_INTERLACE;
310 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
311 misc |= ATOM_DOUBLE_CLOCK_MODE;
312
313 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
314 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 315
5a9bcacc 316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 317}
318
5a9bcacc
AD		 319static void atombios_crtc_set_timing(struct drm_crtc *crtc,
320 struct drm_display_mode *mode)
771fe6b9 321{
5a9bcacc 322 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 323 struct drm_device *dev = crtc->dev;
324 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 325 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 326 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 327 u16 misc = 0;
771fe6b9 328
5a9bcacc
AD		 329 memset(&args, 0, sizeof(args));
330 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
331 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
332 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
333 args.usH_SyncWidth =
334 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
335 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
336 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
337 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
338 args.usV_SyncWidth =
339 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
340
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a
AD		 401union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS legacy;
403 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
404};
405
b792210e 406static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 407{
408 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
409 struct drm_device *dev = crtc->dev;
410 struct radeon_device *rdev = dev->dev_private;
411 struct drm_encoder *encoder = NULL;
412 struct radeon_encoder *radeon_encoder = NULL;
413 struct radeon_encoder_atom_dig *dig = NULL;
414 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 415 union atom_enable_ss args;
ebbe1cb9
AD		 416 uint16_t percentage = 0;
417 uint8_t type = 0, step = 0, delay = 0, range = 0;
418
bcc1c2a1
AD		 419 /* XXX add ss support for DCE4 */
420 if (ASIC_IS_DCE4(rdev))
421 return;
422
ebbe1cb9
AD		 423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
424 if (encoder->crtc == crtc) {
425 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 426 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 427 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
428 dig = radeon_encoder->enc_priv;
429 if (dig && dig->ss) {
430 percentage = dig->ss->percentage;
431 type = dig->ss->type;
432 step = dig->ss->step;
433 delay = dig->ss->delay;
434 range = dig->ss->range;
b792210e 435 } else
d11aa88b 436 return;
b792210e 437 } else
ebbe1cb9
AD		 438 return;
439 break;
440 }
441 }
442
443 if (!radeon_encoder)
444 return;
445
26b9fc3a 446 memset(&args, 0, sizeof(args));
ebbe1cb9 447 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 448 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
449 args.v1.ucSpreadSpectrumType = type;
450 args.v1.ucSpreadSpectrumStep = step;
451 args.v1.ucSpreadSpectrumDelay = delay;
452 args.v1.ucSpreadSpectrumRange = range;
453 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 454 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 455 } else {
26b9fc3a
AD		 456 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
457 args.legacy.ucSpreadSpectrumType = type;
458 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
459 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 460 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 461 }
26b9fc3a 462 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 463}
464
4eaeca33
AD		 465union adjust_pixel_clock {
466 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 467 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 468};
469
470static u32 atombios_adjust_pll(struct drm_crtc *crtc,
471 struct drm_display_mode *mode,
472 struct radeon_pll *pll)
771fe6b9 473{
771fe6b9
JG		 474 struct drm_device *dev = crtc->dev;
475 struct radeon_device *rdev = dev->dev_private;
476 struct drm_encoder *encoder = NULL;
477 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 478 u32 adjusted_clock = mode->clock;
bcc1c2a1 479 int encoder_mode = 0;
fc10332b 480
4eaeca33
AD		 481 /* reset the pll flags */
482 pll->flags = 0;
771fe6b9 483
7c27f87d
AD		 484 /* select the PLL algo */
485 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 486 if (radeon_new_pll == 0)
487 pll->algo = PLL_ALGO_LEGACY;
488 else
489 pll->algo = PLL_ALGO_NEW;
490 } else {
491 if (radeon_new_pll == 1)
492 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 493 else
494 pll->algo = PLL_ALGO_LEGACY;
383be5d1 495 }
7c27f87d 496
771fe6b9 497 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 498 if ((rdev->family == CHIP_RS600) ||
499 (rdev->family == CHIP_RS690) ||
500 (rdev->family == CHIP_RS740))
fc10332b
AD		 501 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
502 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 503
771fe6b9 504 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 505 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 506 else
fc10332b 507 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 508 } else {
fc10332b 509 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 510
511 if (mode->clock > 200000) /* range limits??? */
fc10332b 512 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 513 else
fc10332b 514 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 515
516 }
517
518 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
519 if (encoder->crtc == crtc) {
4eaeca33 520 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 521 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 522 if (ASIC_IS_AVIVO(rdev)) {
523 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
524 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
525 adjusted_clock = mode->clock * 2;
a1a4b23b
AD		 526 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
527 pll->algo = PLL_ALGO_LEGACY;
528 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
529 }
4eaeca33
AD		 530 } else {
531 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 532 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 533 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 534 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 535 }
3ce0a23d 536 break;
771fe6b9
JG		 537 }
538 }
539
2606c886
AD		 540 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
541 * accordingly based on the encoder/transmitter to work around
542 * special hw requirements.
543 */
544 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 545 union adjust_pixel_clock args;
4eaeca33
AD		 546 u8 frev, crev;
547 int index;
2606c886 548
2606c886 549 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 550 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
551 &crev))
552 return adjusted_clock;
4eaeca33
AD		 553
554 memset(&args, 0, sizeof(args));
555
556 switch (frev) {
557 case 1:
558 switch (crev) {
559 case 1:
560 case 2:
561 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
562 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 563 args.v1.ucEncodeMode = encoder_mode;
4eaeca33
AD		 564
565 atom_execute_table(rdev->mode_info.atom_context,
566 index, (uint32_t *)&args);
567 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
568 break;
bcc1c2a1
AD		 569 case 3:
570 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
571 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
572 args.v3.sInput.ucEncodeMode = encoder_mode;
573 args.v3.sInput.ucDispPllConfig = 0;
574 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
576
577 if (encoder_mode == ATOM_ENCODER_MODE_DP)
578 args.v3.sInput.ucDispPllConfig |=
579 DISPPLL_CONFIG_COHERENT_MODE;
580 else {
581 if (dig->coherent_mode)
582 args.v3.sInput.ucDispPllConfig |=
583 DISPPLL_CONFIG_COHERENT_MODE;
584 if (mode->clock > 165000)
585 args.v3.sInput.ucDispPllConfig |=
586 DISPPLL_CONFIG_DUAL_LINK;
587 }
588 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
589 /* may want to enable SS on DP/eDP eventually */
9f998ad7
AD		 590 /*args.v3.sInput.ucDispPllConfig |=
591 DISPPLL_CONFIG_SS_ENABLE;*/
592 if (encoder_mode == ATOM_ENCODER_MODE_DP)
bcc1c2a1 593 args.v3.sInput.ucDispPllConfig |=
9f998ad7
AD		 594 DISPPLL_CONFIG_COHERENT_MODE;
595 else {
596 if (mode->clock > 165000)
597 args.v3.sInput.ucDispPllConfig |=
598 DISPPLL_CONFIG_DUAL_LINK;
599 }
bcc1c2a1
AD		 600 }
601 atom_execute_table(rdev->mode_info.atom_context,
602 index, (uint32_t *)&args);
603 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
604 if (args.v3.sOutput.ucRefDiv) {
605 pll->flags |= RADEON_PLL_USE_REF_DIV;
606 pll->reference_div = args.v3.sOutput.ucRefDiv;
607 }
608 if (args.v3.sOutput.ucPostDiv) {
609 pll->flags |= RADEON_PLL_USE_POST_DIV;
610 pll->post_div = args.v3.sOutput.ucPostDiv;
611 }
612 break;
4eaeca33
AD		 613 default:
614 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
615 return adjusted_clock;
616 }
617 break;
618 default:
619 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
620 return adjusted_clock;
621 }
d56ef9c8 622 }
4eaeca33
AD		 623 return adjusted_clock;
624}
625
626union set_pixel_clock {
627 SET_PIXEL_CLOCK_PS_ALLOCATION base;
628 PIXEL_CLOCK_PARAMETERS v1;
629 PIXEL_CLOCK_PARAMETERS_V2 v2;
630 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 631 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 632};
633
bcc1c2a1
AD		 634static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
635{
636 struct drm_device *dev = crtc->dev;
637 struct radeon_device *rdev = dev->dev_private;
638 u8 frev, crev;
639 int index;
640 union set_pixel_clock args;
641
642 memset(&args, 0, sizeof(args));
643
644 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 645 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
646 &crev))
647 return;
bcc1c2a1
AD		 648
649 switch (frev) {
650 case 1:
651 switch (crev) {
652 case 5:
653 /* if the default dcpll clock is specified,
654 * SetPixelClock provides the dividers
655 */
656 args.v5.ucCRTC = ATOM_CRTC_INVALID;
657 args.v5.usPixelClock = rdev->clock.default_dispclk;
658 args.v5.ucPpll = ATOM_DCPLL;
659 break;
660 default:
661 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
662 return;
663 }
664 break;
665 default:
666 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
667 return;
668 }
669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
670}
671
672static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
4eaeca33
AD		 673{
674 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
675 struct drm_device *dev = crtc->dev;
676 struct radeon_device *rdev = dev->dev_private;
677 struct drm_encoder *encoder = NULL;
678 struct radeon_encoder *radeon_encoder = NULL;
679 u8 frev, crev;
680 int index;
681 union set_pixel_clock args;
682 u32 pll_clock = mode->clock;
683 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
684 struct radeon_pll *pll;
685 u32 adjusted_clock;
bcc1c2a1 686 int encoder_mode = 0;
4eaeca33
AD		 687
688 memset(&args, 0, sizeof(args));
689
690 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
691 if (encoder->crtc == crtc) {
692 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 693 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 694 break;
695 }
696 }
697
698 if (!radeon_encoder)
699 return;
700
bcc1c2a1
AD		 701 switch (radeon_crtc->pll_id) {
702 case ATOM_PPLL1:
4eaeca33 703 pll = &rdev->clock.p1pll;
bcc1c2a1
AD		 704 break;
705 case ATOM_PPLL2:
4eaeca33 706 pll = &rdev->clock.p2pll;
bcc1c2a1
AD		 707 break;
708 case ATOM_DCPLL:
709 case ATOM_PPLL_INVALID:
710 pll = &rdev->clock.dcpll;
711 break;
712 }
4eaeca33
AD		 713
714 /* adjust pixel clock as needed */
715 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
2606c886 716
7c27f87d
AD		 717 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
718 &ref_div, &post_div);
771fe6b9 719
39deb2d6 720 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 721 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
722 &crev))
723 return;
771fe6b9
JG		 724
725 switch (frev) {
726 case 1:
727 switch (crev) {
728 case 1:
4eaeca33
AD		 729 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
730 args.v1.usRefDiv = cpu_to_le16(ref_div);
731 args.v1.usFbDiv = cpu_to_le16(fb_div);
732 args.v1.ucFracFbDiv = frac_fb_div;
733 args.v1.ucPostDiv = post_div;
bcc1c2a1 734 args.v1.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 735 args.v1.ucCRTC = radeon_crtc->crtc_id;
736 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 737 break;
738 case 2:
4eaeca33
AD		 739 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
740 args.v2.usRefDiv = cpu_to_le16(ref_div);
741 args.v2.usFbDiv = cpu_to_le16(fb_div);
742 args.v2.ucFracFbDiv = frac_fb_div;
743 args.v2.ucPostDiv = post_div;
bcc1c2a1 744 args.v2.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 745 args.v2.ucCRTC = radeon_crtc->crtc_id;
746 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 747 break;
748 case 3:
4eaeca33
AD		 749 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
750 args.v3.usRefDiv = cpu_to_le16(ref_div);
751 args.v3.usFbDiv = cpu_to_le16(fb_div);
752 args.v3.ucFracFbDiv = frac_fb_div;
753 args.v3.ucPostDiv = post_div;
bcc1c2a1
AD		 754 args.v3.ucPpll = radeon_crtc->pll_id;
755 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
4eaeca33 756 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
bcc1c2a1
AD		 757 args.v3.ucEncoderMode = encoder_mode;
758 break;
759 case 5:
760 args.v5.ucCRTC = radeon_crtc->crtc_id;
761 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
762 args.v5.ucRefDiv = ref_div;
763 args.v5.usFbDiv = cpu_to_le16(fb_div);
764 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
765 args.v5.ucPostDiv = post_div;
766 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
767 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
768 args.v5.ucEncoderMode = encoder_mode;
769 args.v5.ucPpll = radeon_crtc->pll_id;
771fe6b9
JG		 770 break;
771 default:
772 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
773 return;
774 }
775 break;
776 default:
777 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
778 return;
779 }
780
771fe6b9
JG		 781 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
782}
783
bcc1c2a1
AD		 784static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
785 struct drm_framebuffer *old_fb)
786{
787 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
788 struct drm_device *dev = crtc->dev;
789 struct radeon_device *rdev = dev->dev_private;
790 struct radeon_framebuffer *radeon_fb;
791 struct drm_gem_object *obj;
792 struct radeon_bo *rbo;
793 uint64_t fb_location;
794 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
795 int r;
796
797 /* no fb bound */
798 if (!crtc->fb) {
799 DRM_DEBUG("No FB bound\n");
800 return 0;
801 }
802
803 radeon_fb = to_radeon_framebuffer(crtc->fb);
804
805 /* Pin framebuffer & get tilling informations */
806 obj = radeon_fb->obj;
807 rbo = obj->driver_private;
808 r = radeon_bo_reserve(rbo, false);
809 if (unlikely(r != 0))
810 return r;
811 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
812 if (unlikely(r != 0)) {
813 radeon_bo_unreserve(rbo);
814 return -EINVAL;
815 }
816 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
817 radeon_bo_unreserve(rbo);
818
819 switch (crtc->fb->bits_per_pixel) {
820 case 8:
821 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
822 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
823 break;
824 case 15:
825 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
826 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
827 break;
828 case 16:
829 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
830 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
831 break;
832 case 24:
833 case 32:
834 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
835 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
836 break;
837 default:
838 DRM_ERROR("Unsupported screen depth %d\n",
839 crtc->fb->bits_per_pixel);
840 return -EINVAL;
841 }
842
843 switch (radeon_crtc->crtc_id) {
844 case 0:
845 WREG32(AVIVO_D1VGA_CONTROL, 0);
846 break;
847 case 1:
848 WREG32(AVIVO_D2VGA_CONTROL, 0);
849 break;
850 case 2:
851 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
852 break;
853 case 3:
854 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
855 break;
856 case 4:
857 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
858 break;
859 case 5:
860 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
861 break;
862 default:
863 break;
864 }
865
866 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
867 upper_32_bits(fb_location));
868 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
869 upper_32_bits(fb_location));
870 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
871 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
872 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
873 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
874 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
875
876 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
877 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
878 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
879 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
880 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
881 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
882
883 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
884 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
885 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
886
887 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
888 crtc->mode.vdisplay);
889 x &= ~3;
890 y &= ~1;
891 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
892 (x << 16) | y);
893 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
894 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
895
896 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
897 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
898 EVERGREEN_INTERLEAVE_EN);
899 else
900 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
901
902 if (old_fb && old_fb != crtc->fb) {
903 radeon_fb = to_radeon_framebuffer(old_fb);
904 rbo = radeon_fb->obj->driver_private;
905 r = radeon_bo_reserve(rbo, false);
906 if (unlikely(r != 0))
907 return r;
908 radeon_bo_unpin(rbo);
909 radeon_bo_unreserve(rbo);
910 }
911
912 /* Bytes per pixel may have changed */
913 radeon_bandwidth_update(rdev);
914
915 return 0;
916}
917
54f088a9
AD		 918static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
919 struct drm_framebuffer *old_fb)
771fe6b9
JG		 920{
921 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
922 struct drm_device *dev = crtc->dev;
923 struct radeon_device *rdev = dev->dev_private;
924 struct radeon_framebuffer *radeon_fb;
925 struct drm_gem_object *obj;
4c788679 926 struct radeon_bo *rbo;
771fe6b9 927 uint64_t fb_location;
e024e110 928 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 929 int r;
771fe6b9 930
2de3b484
JG		 931 /* no fb bound */
932 if (!crtc->fb) {
933 DRM_DEBUG("No FB bound\n");
934 return 0;
935 }
771fe6b9
JG		 936
937 radeon_fb = to_radeon_framebuffer(crtc->fb);
938
4c788679 939 /* Pin framebuffer & get tilling informations */
771fe6b9 940 obj = radeon_fb->obj;
4c788679
JG		 941 rbo = obj->driver_private;
942 r = radeon_bo_reserve(rbo, false);
943 if (unlikely(r != 0))
944 return r;
945 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
946 if (unlikely(r != 0)) {
947 radeon_bo_unreserve(rbo);
771fe6b9
JG		 948 return -EINVAL;
949 }
4c788679
JG		 950 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
951 radeon_bo_unreserve(rbo);
771fe6b9
JG		 952
953 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 954 case 8:
955 fb_format =
956 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
957 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
958 break;
771fe6b9
JG		 959 case 15:
960 fb_format =
961 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
962 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
963 break;
964 case 16:
965 fb_format =
966 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
967 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
968 break;
969 case 24:
970 case 32:
971 fb_format =
972 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
973 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
974 break;
975 default:
976 DRM_ERROR("Unsupported screen depth %d\n",
977 crtc->fb->bits_per_pixel);
978 return -EINVAL;
979 }
980
cf2f05d3
DA		 981 if (tiling_flags & RADEON_TILING_MACRO)
982 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
983
e024e110
DA		 984 if (tiling_flags & RADEON_TILING_MICRO)
985 fb_format |= AVIVO_D1GRPH_TILED;
986
771fe6b9
JG		 987 if (radeon_crtc->crtc_id == 0)
988 WREG32(AVIVO_D1VGA_CONTROL, 0);
989 else
990 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 991
992 if (rdev->family >= CHIP_RV770) {
993 if (radeon_crtc->crtc_id) {
994 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
995 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
996 } else {
997 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
998 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
999 }
1000 }
771fe6b9
JG		 1001 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1002 (u32) fb_location);
1003 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1004 radeon_crtc->crtc_offset, (u32) fb_location);
1005 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1006
1007 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1008 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1009 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1010 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1011 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1012 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1013
1014 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1015 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1016 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1017
1018 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1019 crtc->mode.vdisplay);
1020 x &= ~3;
1021 y &= ~1;
1022 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1023 (x << 16) | y);
1024 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1025 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1026
1027 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1028 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1029 AVIVO_D1MODE_INTERLEAVE_EN);
1030 else
1031 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1032
1033 if (old_fb && old_fb != crtc->fb) {
1034 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1035 rbo = radeon_fb->obj->driver_private;
1036 r = radeon_bo_reserve(rbo, false);
1037 if (unlikely(r != 0))
1038 return r;
1039 radeon_bo_unpin(rbo);
1040 radeon_bo_unreserve(rbo);
771fe6b9 1041 }
f30f37de
MD		 1042
1043 /* Bytes per pixel may have changed */
1044 radeon_bandwidth_update(rdev);
1045
771fe6b9
JG		 1046 return 0;
1047}
1048
54f088a9
AD		 1049int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1050 struct drm_framebuffer *old_fb)
1051{
1052 struct drm_device *dev = crtc->dev;
1053 struct radeon_device *rdev = dev->dev_private;
1054
bcc1c2a1
AD		 1055 if (ASIC_IS_DCE4(rdev))
1056 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1057 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1058 return avivo_crtc_set_base(crtc, x, y, old_fb);
1059 else
1060 return radeon_crtc_set_base(crtc, x, y, old_fb);
1061}
1062
615e0cb6
AD		 1063/* properly set additional regs when using atombios */
1064static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1065{
1066 struct drm_device *dev = crtc->dev;
1067 struct radeon_device *rdev = dev->dev_private;
1068 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1069 u32 disp_merge_cntl;
1070
1071 switch (radeon_crtc->crtc_id) {
1072 case 0:
1073 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1074 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1075 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1076 break;
1077 case 1:
1078 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1079 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1080 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1081 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1082 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1083 break;
1084 }
1085}
1086
bcc1c2a1
AD		 1087static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1088{
1089 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1090 struct drm_device *dev = crtc->dev;
1091 struct radeon_device *rdev = dev->dev_private;
1092 struct drm_encoder *test_encoder;
1093 struct drm_crtc *test_crtc;
1094 uint32_t pll_in_use = 0;
1095
1096 if (ASIC_IS_DCE4(rdev)) {
1097 /* if crtc is driving DP and we have an ext clock, use that */
1098 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1099 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1100 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1101 if (rdev->clock.dp_extclk)
1102 return ATOM_PPLL_INVALID;
1103 }
1104 }
1105 }
1106
1107 /* otherwise, pick one of the plls */
1108 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1109 struct radeon_crtc *radeon_test_crtc;
1110
1111 if (crtc == test_crtc)
1112 continue;
1113
1114 radeon_test_crtc = to_radeon_crtc(test_crtc);
1115 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1116 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1117 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1118 }
1119 if (!(pll_in_use & 1))
1120 return ATOM_PPLL1;
1121 return ATOM_PPLL2;
1122 } else
1123 return radeon_crtc->crtc_id;
1124
1125}
1126
771fe6b9
JG		 1127int atombios_crtc_mode_set(struct drm_crtc *crtc,
1128 struct drm_display_mode *mode,
1129 struct drm_display_mode *adjusted_mode,
1130 int x, int y, struct drm_framebuffer *old_fb)
1131{
1132 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1133 struct drm_device *dev = crtc->dev;
1134 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1135
1136 /* TODO color tiling */
771fe6b9 1137
b792210e 1138 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1139 /* always set DCPLL */
1140 if (ASIC_IS_DCE4(rdev))
1141 atombios_crtc_set_dcpll(crtc);
771fe6b9 1142 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1143 atombios_enable_ss(crtc);
771fe6b9 1144
bcc1c2a1
AD		 1145 if (ASIC_IS_DCE4(rdev))
1146 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1147 else if (ASIC_IS_AVIVO(rdev))
1148 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9 1149 else {
bcc1c2a1 1150 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1151 if (radeon_crtc->crtc_id == 0)
1152 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1153 radeon_legacy_atom_fixup(crtc);
771fe6b9 1154 }
bcc1c2a1 1155 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1156 atombios_overscan_setup(crtc, mode, adjusted_mode);
1157 atombios_scaler_setup(crtc);
771fe6b9
JG		 1158 return 0;
1159}
1160
1161static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1162 struct drm_display_mode *mode,
1163 struct drm_display_mode *adjusted_mode)
1164{
03214bd5
AD		 1165 struct drm_device *dev = crtc->dev;
1166 struct radeon_device *rdev = dev->dev_private;
1167
1168 /* adjust pm to upcoming mode change */
1169 radeon_pm_compute_clocks(rdev);
1170
c93bb85b
JG		 1171 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1172 return false;
771fe6b9
JG		 1173 return true;
1174}
1175
1176static void atombios_crtc_prepare(struct drm_crtc *crtc)
1177{
267364ac
AD		 1178 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1179
1180 /* pick pll */
1181 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1182
37b4390e 1183 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1184 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1185}
1186
1187static void atombios_crtc_commit(struct drm_crtc *crtc)
1188{
1189 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1190 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1191}
1192
1193static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1194 .dpms = atombios_crtc_dpms,
1195 .mode_fixup = atombios_crtc_mode_fixup,
1196 .mode_set = atombios_crtc_mode_set,
1197 .mode_set_base = atombios_crtc_set_base,
1198 .prepare = atombios_crtc_prepare,
1199 .commit = atombios_crtc_commit,
068143d3 1200 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 1201};
1202
1203void radeon_atombios_init_crtc(struct drm_device *dev,
1204 struct radeon_crtc *radeon_crtc)
1205{
bcc1c2a1
AD		 1206 struct radeon_device *rdev = dev->dev_private;
1207
1208 if (ASIC_IS_DCE4(rdev)) {
1209 switch (radeon_crtc->crtc_id) {
1210 case 0:
1211 default:
12d7798f 1212 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1213 break;
1214 case 1:
12d7798f 1215 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1216 break;
1217 case 2:
12d7798f 1218 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1219 break;
1220 case 3:
12d7798f 1221 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1222 break;
1223 case 4:
12d7798f 1224 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1225 break;
1226 case 5:
12d7798f 1227 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1228 break;
1229 }
1230 } else {
1231 if (radeon_crtc->crtc_id == 1)
1232 radeon_crtc->crtc_offset =
1233 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1234 else
1235 radeon_crtc->crtc_offset = 0;
1236 }
1237 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1238 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1239}
Linux kernel - Deliverables
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