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drm/radeon/kms: DCE6 disp eng pll updates
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
fef9f91f
AD		 234static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
235{
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237 struct drm_device *dev = crtc->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
240 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
241
242 memset(&args, 0, sizeof(args));
243
244 args.ucDispPipeId = radeon_crtc->crtc_id;
245 args.ucEnable = state;
246
247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
248}
249
771fe6b9
JG		 250void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
251{
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
500b7587 254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 255
256 switch (mode) {
257 case DRM_MODE_DPMS_ON:
d7311171
AD		 258 radeon_crtc->enabled = true;
259 /* adjust pm to dpms changes BEFORE enabling crtcs */
260 radeon_pm_compute_clocks(rdev);
fef9f91f
AD		 261 /* disable crtc pair power gating before programming */
262 if (ASIC_IS_DCE6(rdev))
263 atombios_powergate_crtc(crtc, ATOM_DISABLE);
37b4390e 264 atombios_enable_crtc(crtc, ATOM_ENABLE);
79f17c64 265 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 266 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
267 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 268 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 269 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 270 break;
271 case DRM_MODE_DPMS_STANDBY:
272 case DRM_MODE_DPMS_SUSPEND:
273 case DRM_MODE_DPMS_OFF:
45f9a39b 274 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 275 if (radeon_crtc->enabled)
276 atombios_blank_crtc(crtc, ATOM_ENABLE);
79f17c64 277 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 278 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
279 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 280 radeon_crtc->enabled = false;
fef9f91f
AD		 281 /* power gating is per-pair */
282 if (ASIC_IS_DCE6(rdev)) {
283 struct drm_crtc *other_crtc;
284 struct radeon_crtc *other_radeon_crtc;
285 list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
286 other_radeon_crtc = to_radeon_crtc(other_crtc);
287 if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
288 ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
289 ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
290 ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
291 ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
292 ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
293 /* if both crtcs in the pair are off, enable power gating */
294 if (other_radeon_crtc->enabled == false)
295 atombios_powergate_crtc(crtc, ATOM_ENABLE);
296 break;
297 }
298 }
299 }
d7311171
AD		 300 /* adjust pm to dpms changes AFTER disabling crtcs */
301 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 302 break;
303 }
771fe6b9
JG		 304}
305
306static void
307atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 308 struct drm_display_mode *mode)
771fe6b9 309{
5a9bcacc 310 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 311 struct drm_device *dev = crtc->dev;
312 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 313 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 314 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 315 u16 misc = 0;
771fe6b9 316
5a9bcacc 317 memset(&args, 0, sizeof(args));
5b1714d3 318 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 319 args.usH_Blanking_Time =
5b1714d3
AD		 320 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
321 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 322 args.usV_Blanking_Time =
5b1714d3 323 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 324 args.usH_SyncOffset =
5b1714d3 325 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 326 args.usH_SyncWidth =
327 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
328 args.usV_SyncOffset =
5b1714d3 329 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 330 args.usV_SyncWidth =
331 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 332 args.ucH_Border = radeon_crtc->h_border;
333 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 334
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
345
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 348
5a9bcacc 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 350}
351
5a9bcacc
AD		 352static void atombios_crtc_set_timing(struct drm_crtc *crtc,
353 struct drm_display_mode *mode)
771fe6b9 354{
5a9bcacc 355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 356 struct drm_device *dev = crtc->dev;
357 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 358 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 359 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 360 u16 misc = 0;
771fe6b9 361
5a9bcacc
AD		 362 memset(&args, 0, sizeof(args));
363 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
364 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
365 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
366 args.usH_SyncWidth =
367 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
368 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
369 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
370 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
371 args.usV_SyncWidth =
372 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
373
54bfe496
AD		 374 args.ucOverscanRight = radeon_crtc->h_border;
375 args.ucOverscanLeft = radeon_crtc->h_border;
376 args.ucOverscanBottom = radeon_crtc->v_border;
377 args.ucOverscanTop = radeon_crtc->v_border;
378
5a9bcacc
AD		 379 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
380 misc |= ATOM_VSYNC_POLARITY;
381 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
382 misc |= ATOM_HSYNC_POLARITY;
383 if (mode->flags & DRM_MODE_FLAG_CSYNC)
384 misc |= ATOM_COMPOSITESYNC;
385 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
386 misc |= ATOM_INTERLACE;
387 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
388 misc |= ATOM_DOUBLE_CLOCK_MODE;
389
390 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
391 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 392
5a9bcacc 393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 394}
395
3fa47d9e 396static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
b792210e 397{
b792210e
AD		 398 u32 ss_cntl;
399
400 if (ASIC_IS_DCE4(rdev)) {
3fa47d9e 401 switch (pll_id) {
b792210e
AD		 402 case ATOM_PPLL1:
403 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
404 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
405 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
406 break;
407 case ATOM_PPLL2:
408 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
409 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
410 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
411 break;
412 case ATOM_DCPLL:
413 case ATOM_PPLL_INVALID:
414 return;
415 }
416 } else if (ASIC_IS_AVIVO(rdev)) {
3fa47d9e 417 switch (pll_id) {
b792210e
AD		 418 case ATOM_PPLL1:
419 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
420 ss_cntl &= ~1;
421 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
422 break;
423 case ATOM_PPLL2:
424 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
425 ss_cntl &= ~1;
426 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
427 break;
428 case ATOM_DCPLL:
429 case ATOM_PPLL_INVALID:
430 return;
431 }
432 }
433}
434
435
26b9fc3a 436union atom_enable_ss {
ba032a58
AD		 437 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
438 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 439 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 441 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 442};
443
3fa47d9e 444static void atombios_crtc_program_ss(struct radeon_device *rdev,
ba032a58
AD		 445 int enable,
446 int pll_id,
447 struct radeon_atom_ss *ss)
ebbe1cb9 448{
ebbe1cb9 449 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 450 union atom_enable_ss args;
ebbe1cb9 451
ba032a58 452 memset(&args, 0, sizeof(args));
bcc1c2a1 453
a572eaa3 454 if (ASIC_IS_DCE5(rdev)) {
4589433c 455 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
8e8e523d 456 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
a572eaa3
AD		 457 switch (pll_id) {
458 case ATOM_PPLL1:
459 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 460 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
461 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 462 break;
463 case ATOM_PPLL2:
464 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 465 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
466 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 467 break;
468 case ATOM_DCPLL:
469 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 470 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
471 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 472 break;
473 case ATOM_PPLL_INVALID:
474 return;
475 }
d0ae3e89 476 args.v3.ucEnable = enable;
8e8e523d
AD		 477 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
478 args.v3.ucEnable = ATOM_DISABLE;
a572eaa3 479 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58 480 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 481 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 482 switch (pll_id) {
483 case ATOM_PPLL1:
484 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 485 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
486 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 487 break;
488 case ATOM_PPLL2:
489 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 490 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
491 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 492 break;
ba032a58
AD		 493 case ATOM_DCPLL:
494 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 495 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
496 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 497 break;
498 case ATOM_PPLL_INVALID:
499 return;
ebbe1cb9 500 }
ba032a58 501 args.v2.ucEnable = enable;
09cc6506 502 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
8e8e523d 503 args.v2.ucEnable = ATOM_DISABLE;
ba032a58
AD		 504 } else if (ASIC_IS_DCE3(rdev)) {
505 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 506 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 507 args.v1.ucSpreadSpectrumStep = ss->step;
508 args.v1.ucSpreadSpectrumDelay = ss->delay;
509 args.v1.ucSpreadSpectrumRange = ss->range;
510 args.v1.ucPpll = pll_id;
511 args.v1.ucEnable = enable;
512 } else if (ASIC_IS_AVIVO(rdev)) {
8e8e523d
AD		 513 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
514 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 515 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 516 return;
517 }
518 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 519 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 520 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
521 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
522 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
523 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 524 } else {
8e8e523d
AD		 525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 527 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 528 return;
529 }
530 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 531 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 532 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
533 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
534 args.lvds_ss.ucEnable = enable;
ebbe1cb9 535 }
26b9fc3a 536 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 537}
538
4eaeca33
AD		 539union adjust_pixel_clock {
540 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 541 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 542};
543
544static u32 atombios_adjust_pll(struct drm_crtc *crtc,
545 struct drm_display_mode *mode,
ba032a58
AD		 546 struct radeon_pll *pll,
547 bool ss_enabled,
548 struct radeon_atom_ss *ss)
771fe6b9 549{
771fe6b9
JG		 550 struct drm_device *dev = crtc->dev;
551 struct radeon_device *rdev = dev->dev_private;
552 struct drm_encoder *encoder = NULL;
553 struct radeon_encoder *radeon_encoder = NULL;
df271bec 554 struct drm_connector *connector = NULL;
4eaeca33 555 u32 adjusted_clock = mode->clock;
bcc1c2a1 556 int encoder_mode = 0;
fbee67a6
AD		 557 u32 dp_clock = mode->clock;
558 int bpc = 8;
9aa59993 559 bool is_duallink = false;
fc10332b 560
4eaeca33
AD		 561 /* reset the pll flags */
562 pll->flags = 0;
771fe6b9
JG		 563
564 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 565 if ((rdev->family == CHIP_RS600) ||
566 (rdev->family == CHIP_RS690) ||
567 (rdev->family == CHIP_RS740))
2ff776cf 568 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 569 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 570
571 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
572 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
573 else
574 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 575
5785e53f 576 if (rdev->family < CHIP_RV770)
9bb09fa1 577 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
5480f727 578 } else {
fc10332b 579 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 580
5480f727
DA		 581 if (mode->clock > 200000) /* range limits??? */
582 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
583 else
584 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 585 }
586
771fe6b9
JG		 587 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
588 if (encoder->crtc == crtc) {
4eaeca33 589 radeon_encoder = to_radeon_encoder(encoder);
df271bec 590 connector = radeon_get_connector_for_encoder(encoder);
06e4cd64 591 if (connector && connector->display_info.bpc)
df271bec 592 bpc = connector->display_info.bpc;
bcc1c2a1 593 encoder_mode = atombios_get_encoder_mode(encoder);
9aa59993 594 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
eac4dff6 595 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
1d33e1fc 596 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
fbee67a6
AD		 597 if (connector) {
598 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
599 struct radeon_connector_atom_dig *dig_connector =
600 radeon_connector->con_priv;
601
602 dp_clock = dig_connector->dp_clock;
603 }
604 }
5b40ddf8 605
ba032a58
AD		 606 /* use recommended ref_div for ss */
607 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
608 if (ss_enabled) {
609 if (ss->refdiv) {
610 pll->flags |= RADEON_PLL_USE_REF_DIV;
611 pll->reference_div = ss->refdiv;
5b40ddf8
AD		 612 if (ASIC_IS_AVIVO(rdev))
613 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
ba032a58
AD		 614 }
615 }
616 }
5b40ddf8 617
4eaeca33
AD		 618 if (ASIC_IS_AVIVO(rdev)) {
619 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
620 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
621 adjusted_clock = mode->clock * 2;
48dfaaeb 622 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 623 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
5b40ddf8
AD		 624 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
625 pll->flags |= RADEON_PLL_IS_LCD;
4eaeca33
AD		 626 } else {
627 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 628 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 629 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 630 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 631 }
3ce0a23d 632 break;
771fe6b9
JG		 633 }
634 }
635
2606c886
AD		 636 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
637 * accordingly based on the encoder/transmitter to work around
638 * special hw requirements.
639 */
640 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 641 union adjust_pixel_clock args;
4eaeca33
AD		 642 u8 frev, crev;
643 int index;
2606c886 644
2606c886 645 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 646 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
647 &crev))
648 return adjusted_clock;
4eaeca33
AD		 649
650 memset(&args, 0, sizeof(args));
651
652 switch (frev) {
653 case 1:
654 switch (crev) {
655 case 1:
656 case 2:
657 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
658 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 659 args.v1.ucEncodeMode = encoder_mode;
8e8e523d 660 if (ss_enabled && ss->percentage)
fbee67a6
AD		 661 args.v1.ucConfig |=
662 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 663
664 atom_execute_table(rdev->mode_info.atom_context,
665 index, (uint32_t *)&args);
666 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
667 break;
bcc1c2a1
AD		 668 case 3:
669 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
670 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
671 args.v3.sInput.ucEncodeMode = encoder_mode;
672 args.v3.sInput.ucDispPllConfig = 0;
8e8e523d 673 if (ss_enabled && ss->percentage)
b526ce22
AD		 674 args.v3.sInput.ucDispPllConfig |=
675 DISPPLL_CONFIG_SS_ENABLE;
996d5c59 676 if (ENCODER_MODE_IS_DP(encoder_mode)) {
b4f15f80
AD		 677 args.v3.sInput.ucDispPllConfig |=
678 DISPPLL_CONFIG_COHERENT_MODE;
679 /* 16200 or 27000 */
680 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
681 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
bcc1c2a1 682 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b4f15f80
AD		 683 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
684 /* deep color support */
685 args.v3.sInput.usPixelClock =
686 cpu_to_le16((mode->clock * bpc / 8) / 10);
687 if (dig->coherent_mode)
bcc1c2a1
AD		 688 args.v3.sInput.ucDispPllConfig |=
689 DISPPLL_CONFIG_COHERENT_MODE;
9aa59993 690 if (is_duallink)
bcc1c2a1 691 args.v3.sInput.ucDispPllConfig |=
b4f15f80 692 DISPPLL_CONFIG_DUAL_LINK;
bcc1c2a1 693 }
1d33e1fc
AD		 694 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
695 ENCODER_OBJECT_ID_NONE)
696 args.v3.sInput.ucExtTransmitterID =
697 radeon_encoder_get_dp_bridge_encoder_id(encoder);
698 else
cc9f67a0
AD		 699 args.v3.sInput.ucExtTransmitterID = 0;
700
bcc1c2a1
AD		 701 atom_execute_table(rdev->mode_info.atom_context,
702 index, (uint32_t *)&args);
703 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
704 if (args.v3.sOutput.ucRefDiv) {
9f4283f4 705 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 706 pll->flags |= RADEON_PLL_USE_REF_DIV;
707 pll->reference_div = args.v3.sOutput.ucRefDiv;
708 }
709 if (args.v3.sOutput.ucPostDiv) {
9f4283f4 710 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 711 pll->flags |= RADEON_PLL_USE_POST_DIV;
712 pll->post_div = args.v3.sOutput.ucPostDiv;
713 }
714 break;
4eaeca33
AD		 715 default:
716 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
717 return adjusted_clock;
718 }
719 break;
720 default:
721 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
722 return adjusted_clock;
723 }
d56ef9c8 724 }
4eaeca33
AD		 725 return adjusted_clock;
726}
727
728union set_pixel_clock {
729 SET_PIXEL_CLOCK_PS_ALLOCATION base;
730 PIXEL_CLOCK_PARAMETERS v1;
731 PIXEL_CLOCK_PARAMETERS_V2 v2;
732 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 733 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 734 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 735};
736
f82b3ddc
AD		 737/* on DCE5, make sure the voltage is high enough to support the
738 * required disp clk.
739 */
f3f1f03e 740static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
f82b3ddc 741 u32 dispclk)
bcc1c2a1 742{
bcc1c2a1
AD		 743 u8 frev, crev;
744 int index;
745 union set_pixel_clock args;
746
747 memset(&args, 0, sizeof(args));
748
749 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 750 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
751 &crev))
752 return;
bcc1c2a1
AD		 753
754 switch (frev) {
755 case 1:
756 switch (crev) {
757 case 5:
758 /* if the default dcpll clock is specified,
759 * SetPixelClock provides the dividers
760 */
761 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 762 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 763 args.v5.ucPpll = ATOM_DCPLL;
764 break;
f82b3ddc
AD		 765 case 6:
766 /* if the default dcpll clock is specified,
767 * SetPixelClock provides the dividers
768 */
265aa6c8 769 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
f3f1f03e
AD		 770 if (ASIC_IS_DCE6(rdev))
771 args.v6.ucPpll = ATOM_PPLL0;
772 else
773 args.v6.ucPpll = ATOM_DCPLL;
f82b3ddc 774 break;
bcc1c2a1
AD		 775 default:
776 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
777 return;
778 }
779 break;
780 default:
781 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
782 return;
783 }
784 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
785}
786
37f9003b 787static void atombios_crtc_program_pll(struct drm_crtc *crtc,
f1bece7f 788 u32 crtc_id,
37f9003b
AD		 789 int pll_id,
790 u32 encoder_mode,
791 u32 encoder_id,
792 u32 clock,
793 u32 ref_div,
794 u32 fb_div,
795 u32 frac_fb_div,
df271bec 796 u32 post_div,
8e8e523d
AD		 797 int bpc,
798 bool ss_enabled,
799 struct radeon_atom_ss *ss)
4eaeca33 800{
4eaeca33
AD		 801 struct drm_device *dev = crtc->dev;
802 struct radeon_device *rdev = dev->dev_private;
4eaeca33 803 u8 frev, crev;
37f9003b 804 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 805 union set_pixel_clock args;
4eaeca33
AD		 806
807 memset(&args, 0, sizeof(args));
808
a084e6ee
AD		 809 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
810 &crev))
811 return;
771fe6b9
JG		 812
813 switch (frev) {
814 case 1:
815 switch (crev) {
816 case 1:
37f9003b
AD		 817 if (clock == ATOM_DISABLE)
818 return;
819 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 820 args.v1.usRefDiv = cpu_to_le16(ref_div);
821 args.v1.usFbDiv = cpu_to_le16(fb_div);
822 args.v1.ucFracFbDiv = frac_fb_div;
823 args.v1.ucPostDiv = post_div;
37f9003b
AD		 824 args.v1.ucPpll = pll_id;
825 args.v1.ucCRTC = crtc_id;
4eaeca33 826 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 827 break;
828 case 2:
37f9003b 829 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 830 args.v2.usRefDiv = cpu_to_le16(ref_div);
831 args.v2.usFbDiv = cpu_to_le16(fb_div);
832 args.v2.ucFracFbDiv = frac_fb_div;
833 args.v2.ucPostDiv = post_div;
37f9003b
AD		 834 args.v2.ucPpll = pll_id;
835 args.v2.ucCRTC = crtc_id;
4eaeca33 836 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 837 break;
838 case 3:
37f9003b 839 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 840 args.v3.usRefDiv = cpu_to_le16(ref_div);
841 args.v3.usFbDiv = cpu_to_le16(fb_div);
842 args.v3.ucFracFbDiv = frac_fb_div;
843 args.v3.ucPostDiv = post_div;
37f9003b
AD		 844 args.v3.ucPpll = pll_id;
845 args.v3.ucMiscInfo = (pll_id << 2);
6f15c506
AD		 846 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
847 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
37f9003b 848 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 849 args.v3.ucEncoderMode = encoder_mode;
850 break;
851 case 5:
37f9003b
AD		 852 args.v5.ucCRTC = crtc_id;
853 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 854 args.v5.ucRefDiv = ref_div;
855 args.v5.usFbDiv = cpu_to_le16(fb_div);
856 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
857 args.v5.ucPostDiv = post_div;
858 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 859 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
860 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
df271bec
AD		 861 switch (bpc) {
862 case 8:
863 default:
864 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
865 break;
866 case 10:
867 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
868 break;
869 }
37f9003b 870 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 871 args.v5.ucEncoderMode = encoder_mode;
37f9003b 872 args.v5.ucPpll = pll_id;
771fe6b9 873 break;
f82b3ddc 874 case 6:
f1bece7f 875 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
f82b3ddc
AD		 876 args.v6.ucRefDiv = ref_div;
877 args.v6.usFbDiv = cpu_to_le16(fb_div);
878 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
879 args.v6.ucPostDiv = post_div;
880 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 881 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
882 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
df271bec
AD		 883 switch (bpc) {
884 case 8:
885 default:
886 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
887 break;
888 case 10:
889 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
890 break;
891 case 12:
892 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
893 break;
894 case 16:
895 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
896 break;
897 }
f82b3ddc
AD		 898 args.v6.ucTransmitterID = encoder_id;
899 args.v6.ucEncoderMode = encoder_mode;
900 args.v6.ucPpll = pll_id;
901 break;
771fe6b9
JG		 902 default:
903 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
904 return;
905 }
906 break;
907 default:
908 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
909 return;
910 }
911
771fe6b9
JG		 912 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
913}
914
37f9003b
AD		 915static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
916{
917 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
918 struct drm_device *dev = crtc->dev;
919 struct radeon_device *rdev = dev->dev_private;
920 struct drm_encoder *encoder = NULL;
921 struct radeon_encoder *radeon_encoder = NULL;
922 u32 pll_clock = mode->clock;
923 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
924 struct radeon_pll *pll;
925 u32 adjusted_clock;
926 int encoder_mode = 0;
ba032a58
AD		 927 struct radeon_atom_ss ss;
928 bool ss_enabled = false;
df271bec 929 int bpc = 8;
37f9003b
AD		 930
931 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
932 if (encoder->crtc == crtc) {
933 radeon_encoder = to_radeon_encoder(encoder);
934 encoder_mode = atombios_get_encoder_mode(encoder);
935 break;
936 }
937 }
938
939 if (!radeon_encoder)
940 return;
941
942 switch (radeon_crtc->pll_id) {
943 case ATOM_PPLL1:
944 pll = &rdev->clock.p1pll;
945 break;
946 case ATOM_PPLL2:
947 pll = &rdev->clock.p2pll;
948 break;
949 case ATOM_DCPLL:
950 case ATOM_PPLL_INVALID:
951 default:
952 pll = &rdev->clock.dcpll;
953 break;
954 }
955
ba032a58
AD		 956 if (radeon_encoder->active_device &
957 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
959 struct drm_connector *connector =
960 radeon_get_connector_for_encoder(encoder);
961 struct radeon_connector *radeon_connector =
962 to_radeon_connector(connector);
963 struct radeon_connector_atom_dig *dig_connector =
964 radeon_connector->con_priv;
965 int dp_clock;
df271bec 966 bpc = connector->display_info.bpc;
ba032a58
AD		 967
968 switch (encoder_mode) {
996d5c59 969 case ATOM_ENCODER_MODE_DP_MST:
ba032a58
AD		 970 case ATOM_ENCODER_MODE_DP:
971 /* DP/eDP */
972 dp_clock = dig_connector->dp_clock / 10;
2307790f
AD		 973 if (ASIC_IS_DCE4(rdev))
974 ss_enabled =
975 radeon_atombios_get_asic_ss_info(rdev, &ss,
976 ASIC_INTERNAL_SS_ON_DP,
977 dp_clock);
978 else {
979 if (dp_clock == 16200) {
ba032a58 980 ss_enabled =
2307790f
AD		 981 radeon_atombios_get_ppll_ss_info(rdev, &ss,
982 ATOM_DP_SS_ID2);
8e8e523d
AD		 983 if (!ss_enabled)
984 ss_enabled =
2307790f
AD		 985 radeon_atombios_get_ppll_ss_info(rdev, &ss,
986 ATOM_DP_SS_ID1);
8e8e523d 987 } else
ba032a58
AD		 988 ss_enabled =
989 radeon_atombios_get_ppll_ss_info(rdev, &ss,
2307790f 990 ATOM_DP_SS_ID1);
ba032a58
AD		 991 }
992 break;
993 case ATOM_ENCODER_MODE_LVDS:
994 if (ASIC_IS_DCE4(rdev))
995 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
996 dig->lcd_ss_id,
997 mode->clock / 10);
998 else
999 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
1000 dig->lcd_ss_id);
1001 break;
1002 case ATOM_ENCODER_MODE_DVI:
1003 if (ASIC_IS_DCE4(rdev))
1004 ss_enabled =
1005 radeon_atombios_get_asic_ss_info(rdev, &ss,
1006 ASIC_INTERNAL_SS_ON_TMDS,
1007 mode->clock / 10);
1008 break;
1009 case ATOM_ENCODER_MODE_HDMI:
1010 if (ASIC_IS_DCE4(rdev))
1011 ss_enabled =
1012 radeon_atombios_get_asic_ss_info(rdev, &ss,
1013 ASIC_INTERNAL_SS_ON_HDMI,
1014 mode->clock / 10);
1015 break;
1016 default:
1017 break;
1018 }
1019 }
1020
37f9003b 1021 /* adjust pixel clock as needed */
ba032a58 1022 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 1023
64146f8b
AD		 1024 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1025 /* TV seems to prefer the legacy algo on some boards */
1026 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1027 &ref_div, &post_div);
1028 else if (ASIC_IS_AVIVO(rdev))
619efb10
AD		 1029 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1030 &ref_div, &post_div);
1031 else
1032 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1033 &ref_div, &post_div);
37f9003b 1034
3fa47d9e 1035 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
ba032a58 1036
37f9003b
AD		 1037 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1038 encoder_mode, radeon_encoder->encoder_id, mode->clock,
8e8e523d 1039 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
37f9003b 1040
ba032a58
AD		 1041 if (ss_enabled) {
1042 /* calculate ss amount and step size */
1043 if (ASIC_IS_DCE4(rdev)) {
1044 u32 step_size;
1045 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1046 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
8e8e523d 1047 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ba032a58
AD		 1048 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1049 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1050 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1051 (125 * 25 * pll->reference_freq / 100);
1052 else
1053 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1054 (125 * 25 * pll->reference_freq / 100);
1055 ss.step = step_size;
1056 }
1057
3fa47d9e 1058 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
ba032a58 1059 }
37f9003b
AD		 1060}
1061
c9417bdd
AD		 1062static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1063 struct drm_framebuffer *fb,
1064 int x, int y, int atomic)
bcc1c2a1
AD		 1065{
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1067 struct drm_device *dev = crtc->dev;
1068 struct radeon_device *rdev = dev->dev_private;
1069 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1070 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1071 struct drm_gem_object *obj;
1072 struct radeon_bo *rbo;
1073 uint64_t fb_location;
1074 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
285484e2 1075 unsigned bankw, bankh, mtaspect, tile_split;
fa6bee46 1076 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
adcfde51 1077 u32 tmp, viewport_w, viewport_h;
bcc1c2a1
AD		 1078 int r;
1079
1080 /* no fb bound */
4dd19b0d 1081 if (!atomic && !crtc->fb) {
d9fdaafb 1082 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1083 return 0;
1084 }
1085
4dd19b0d
CB		 1086 if (atomic) {
1087 radeon_fb = to_radeon_framebuffer(fb);
1088 target_fb = fb;
1089 }
1090 else {
1091 radeon_fb = to_radeon_framebuffer(crtc->fb);
1092 target_fb = crtc->fb;
1093 }
bcc1c2a1 1094
4dd19b0d
CB		 1095 /* If atomic, assume fb object is pinned & idle & fenced and
1096 * just update base pointers
1097 */
bcc1c2a1 1098 obj = radeon_fb->obj;
7e4d15d9 1099 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1100 r = radeon_bo_reserve(rbo, false);
1101 if (unlikely(r != 0))
1102 return r;
4dd19b0d
CB		 1103
1104 if (atomic)
1105 fb_location = radeon_bo_gpu_offset(rbo);
1106 else {
1107 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1108 if (unlikely(r != 0)) {
1109 radeon_bo_unreserve(rbo);
1110 return -EINVAL;
1111 }
bcc1c2a1 1112 }
4dd19b0d 1113
bcc1c2a1
AD		 1114 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1115 radeon_bo_unreserve(rbo);
1116
4dd19b0d 1117 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1118 case 8:
1119 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1120 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1121 break;
1122 case 15:
1123 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1124 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1125 break;
1126 case 16:
1127 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1128 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1129#ifdef __BIG_ENDIAN
1130 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1131#endif
bcc1c2a1
AD		 1132 break;
1133 case 24:
1134 case 32:
1135 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1136 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1137#ifdef __BIG_ENDIAN
1138 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1139#endif
bcc1c2a1
AD		 1140 break;
1141 default:
1142 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1143 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1144 return -EINVAL;
1145 }
1146
392e3722
AD		 1147 if (tiling_flags & RADEON_TILING_MACRO) {
1148 if (rdev->family >= CHIP_CAYMAN)
1149 tmp = rdev->config.cayman.tile_config;
1150 else
1151 tmp = rdev->config.evergreen.tile_config;
1152
1153 switch ((tmp & 0xf0) >> 4) {
1154 case 0: /* 4 banks */
1155 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1156 break;
1157 case 1: /* 8 banks */
1158 default:
1159 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1160 break;
1161 case 2: /* 16 banks */
1162 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1163 break;
1164 }
1165
97d66328 1166 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
285484e2
JG		 1167
1168 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1169 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1170 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1171 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1172 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
392e3722 1173 } else if (tiling_flags & RADEON_TILING_MICRO)
97d66328
AD		 1174 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1175
bcc1c2a1
AD		 1176 switch (radeon_crtc->crtc_id) {
1177 case 0:
1178 WREG32(AVIVO_D1VGA_CONTROL, 0);
1179 break;
1180 case 1:
1181 WREG32(AVIVO_D2VGA_CONTROL, 0);
1182 break;
1183 case 2:
1184 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1185 break;
1186 case 3:
1187 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1188 break;
1189 case 4:
1190 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1191 break;
1192 case 5:
1193 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1194 break;
1195 default:
1196 break;
1197 }
1198
1199 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1200 upper_32_bits(fb_location));
1201 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1202 upper_32_bits(fb_location));
1203 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1204 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1205 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1206 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1207 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1208 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1209
1210 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1211 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1212 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1213 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1214 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1215 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1216
01f2c773 1217 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1218 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1219 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1220
1221 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1222 target_fb->height);
bcc1c2a1
AD		 1223 x &= ~3;
1224 y &= ~1;
1225 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1226 (x << 16) | y);
adcfde51
AD		 1227 viewport_w = crtc->mode.hdisplay;
1228 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
bcc1c2a1 1229 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1230 (viewport_w << 16) | viewport_h);
bcc1c2a1 1231
fb9674bd
AD		 1232 /* pageflip setup */
1233 /* make sure flip is at vb rather than hb */
1234 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1235 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1236 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1237
1238 /* set pageflip to happen anywhere in vblank interval */
1239 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1240
4dd19b0d
CB		 1241 if (!atomic && fb && fb != crtc->fb) {
1242 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1243 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1246 return r;
1247 radeon_bo_unpin(rbo);
1248 radeon_bo_unreserve(rbo);
1249 }
1250
1251 /* Bytes per pixel may have changed */
1252 radeon_bandwidth_update(rdev);
1253
1254 return 0;
1255}
1256
4dd19b0d
CB		 1257static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1258 struct drm_framebuffer *fb,
1259 int x, int y, int atomic)
771fe6b9
JG		 1260{
1261 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1262 struct drm_device *dev = crtc->dev;
1263 struct radeon_device *rdev = dev->dev_private;
1264 struct radeon_framebuffer *radeon_fb;
1265 struct drm_gem_object *obj;
4c788679 1266 struct radeon_bo *rbo;
4dd19b0d 1267 struct drm_framebuffer *target_fb;
771fe6b9 1268 uint64_t fb_location;
e024e110 1269 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1270 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
adcfde51 1271 u32 tmp, viewport_w, viewport_h;
4c788679 1272 int r;
771fe6b9 1273
2de3b484 1274 /* no fb bound */
4dd19b0d 1275 if (!atomic && !crtc->fb) {
d9fdaafb 1276 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1277 return 0;
1278 }
771fe6b9 1279
4dd19b0d
CB		 1280 if (atomic) {
1281 radeon_fb = to_radeon_framebuffer(fb);
1282 target_fb = fb;
1283 }
1284 else {
1285 radeon_fb = to_radeon_framebuffer(crtc->fb);
1286 target_fb = crtc->fb;
1287 }
771fe6b9
JG		 1288
1289 obj = radeon_fb->obj;
7e4d15d9 1290 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1291 r = radeon_bo_reserve(rbo, false);
1292 if (unlikely(r != 0))
1293 return r;
4dd19b0d
CB		 1294
1295 /* If atomic, assume fb object is pinned & idle & fenced and
1296 * just update base pointers
1297 */
1298 if (atomic)
1299 fb_location = radeon_bo_gpu_offset(rbo);
1300 else {
1301 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1302 if (unlikely(r != 0)) {
1303 radeon_bo_unreserve(rbo);
1304 return -EINVAL;
1305 }
771fe6b9 1306 }
4c788679
JG		 1307 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1308 radeon_bo_unreserve(rbo);
771fe6b9 1309
4dd19b0d 1310 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1311 case 8:
1312 fb_format =
1313 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1314 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1315 break;
771fe6b9
JG		 1316 case 15:
1317 fb_format =
1318 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1319 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1320 break;
1321 case 16:
1322 fb_format =
1323 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1324 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1325#ifdef __BIG_ENDIAN
1326 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1327#endif
771fe6b9
JG		 1328 break;
1329 case 24:
1330 case 32:
1331 fb_format =
1332 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1333 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1334#ifdef __BIG_ENDIAN
1335 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1336#endif
771fe6b9
JG		 1337 break;
1338 default:
1339 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1340 target_fb->bits_per_pixel);
771fe6b9
JG		 1341 return -EINVAL;
1342 }
1343
40c4ac1c
AD		 1344 if (rdev->family >= CHIP_R600) {
1345 if (tiling_flags & RADEON_TILING_MACRO)
1346 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1347 else if (tiling_flags & RADEON_TILING_MICRO)
1348 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1349 } else {
1350 if (tiling_flags & RADEON_TILING_MACRO)
1351 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1352
40c4ac1c
AD		 1353 if (tiling_flags & RADEON_TILING_MICRO)
1354 fb_format |= AVIVO_D1GRPH_TILED;
1355 }
e024e110 1356
771fe6b9
JG		 1357 if (radeon_crtc->crtc_id == 0)
1358 WREG32(AVIVO_D1VGA_CONTROL, 0);
1359 else
1360 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1361
1362 if (rdev->family >= CHIP_RV770) {
1363 if (radeon_crtc->crtc_id) {
95347871
AD		 1364 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1365 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1366 } else {
95347871
AD		 1367 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1368 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1369 }
1370 }
771fe6b9
JG		 1371 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1372 (u32) fb_location);
1373 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1374 radeon_crtc->crtc_offset, (u32) fb_location);
1375 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1376 if (rdev->family >= CHIP_R600)
1377 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1378
1379 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1380 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1381 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1382 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1383 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1384 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1385
01f2c773 1386 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1387 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1388 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1389
1390 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1391 target_fb->height);
771fe6b9
JG		 1392 x &= ~3;
1393 y &= ~1;
1394 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1395 (x << 16) | y);
adcfde51
AD		 1396 viewport_w = crtc->mode.hdisplay;
1397 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
771fe6b9 1398 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1399 (viewport_w << 16) | viewport_h);
771fe6b9 1400
fb9674bd
AD		 1401 /* pageflip setup */
1402 /* make sure flip is at vb rather than hb */
1403 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1404 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1405 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1406
1407 /* set pageflip to happen anywhere in vblank interval */
1408 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1409
4dd19b0d
CB		 1410 if (!atomic && fb && fb != crtc->fb) {
1411 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1412 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1413 r = radeon_bo_reserve(rbo, false);
1414 if (unlikely(r != 0))
1415 return r;
1416 radeon_bo_unpin(rbo);
1417 radeon_bo_unreserve(rbo);
771fe6b9 1418 }
f30f37de
MD		 1419
1420 /* Bytes per pixel may have changed */
1421 radeon_bandwidth_update(rdev);
1422
771fe6b9
JG		 1423 return 0;
1424}
1425
54f088a9
AD		 1426int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1427 struct drm_framebuffer *old_fb)
1428{
1429 struct drm_device *dev = crtc->dev;
1430 struct radeon_device *rdev = dev->dev_private;
1431
bcc1c2a1 1432 if (ASIC_IS_DCE4(rdev))
c9417bdd 1433 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1434 else if (ASIC_IS_AVIVO(rdev))
1435 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1436 else
1437 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1438}
1439
1440int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1441 struct drm_framebuffer *fb,
21c74a8e 1442 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1443{
1444 struct drm_device *dev = crtc->dev;
1445 struct radeon_device *rdev = dev->dev_private;
1446
1447 if (ASIC_IS_DCE4(rdev))
c9417bdd 1448 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1449 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1450 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1451 else
4dd19b0d 1452 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1453}
1454
615e0cb6
AD		 1455/* properly set additional regs when using atombios */
1456static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1457{
1458 struct drm_device *dev = crtc->dev;
1459 struct radeon_device *rdev = dev->dev_private;
1460 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1461 u32 disp_merge_cntl;
1462
1463 switch (radeon_crtc->crtc_id) {
1464 case 0:
1465 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1466 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1467 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1468 break;
1469 case 1:
1470 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1471 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1472 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1473 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1474 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1475 break;
1476 }
1477}
1478
bcc1c2a1
AD		 1479static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1480{
1481 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1482 struct drm_device *dev = crtc->dev;
1483 struct radeon_device *rdev = dev->dev_private;
1484 struct drm_encoder *test_encoder;
1485 struct drm_crtc *test_crtc;
1486 uint32_t pll_in_use = 0;
1487
1488 if (ASIC_IS_DCE4(rdev)) {
bcc1c2a1
AD		 1489 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1490 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
86a94def
AD		 1491 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1492 * depending on the asic:
1493 * DCE4: PPLL or ext clock
1494 * DCE5: DCPLL or ext clock
1495 *
1496 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1497 * PPLL/DCPLL programming and only program the DP DTO for the
1498 * crtc virtual pixel clock.
1499 */
996d5c59 1500 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
86a94def 1501 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
bcc1c2a1
AD		 1502 return ATOM_PPLL_INVALID;
1503 }
1504 }
1505 }
1506
1507 /* otherwise, pick one of the plls */
1508 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1509 struct radeon_crtc *radeon_test_crtc;
1510
1511 if (crtc == test_crtc)
1512 continue;
1513
1514 radeon_test_crtc = to_radeon_crtc(test_crtc);
1515 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1516 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1517 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1518 }
1519 if (!(pll_in_use & 1))
1520 return ATOM_PPLL1;
1521 return ATOM_PPLL2;
1522 } else
1523 return radeon_crtc->crtc_id;
1524
1525}
1526
f3f1f03e 1527void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
3fa47d9e
AD		 1528{
1529 /* always set DCPLL */
f3f1f03e
AD		 1530 if (ASIC_IS_DCE6(rdev))
1531 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1532 else if (ASIC_IS_DCE4(rdev)) {
3fa47d9e
AD		 1533 struct radeon_atom_ss ss;
1534 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1535 ASIC_INTERNAL_SS_ON_DCPLL,
1536 rdev->clock.default_dispclk);
1537 if (ss_enabled)
1538 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
1539 /* XXX: DCE5, make sure voltage, dispclk is high enough */
f3f1f03e 1540 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
3fa47d9e
AD		 1541 if (ss_enabled)
1542 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
1543 }
1544
1545}
1546
771fe6b9
JG		 1547int atombios_crtc_mode_set(struct drm_crtc *crtc,
1548 struct drm_display_mode *mode,
1549 struct drm_display_mode *adjusted_mode,
1550 int x, int y, struct drm_framebuffer *old_fb)
1551{
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553 struct drm_device *dev = crtc->dev;
1554 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1555 struct drm_encoder *encoder;
1556 bool is_tvcv = false;
771fe6b9 1557
54bfe496
AD		 1558 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1559 /* find tv std */
1560 if (encoder->crtc == crtc) {
1561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1562 if (radeon_encoder->active_device &
1563 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1564 is_tvcv = true;
1565 }
1566 }
771fe6b9
JG		 1567
1568 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1569
54bfe496 1570 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1571 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1572 else if (ASIC_IS_AVIVO(rdev)) {
1573 if (is_tvcv)
1574 atombios_crtc_set_timing(crtc, adjusted_mode);
1575 else
1576 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1577 } else {
bcc1c2a1 1578 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1579 if (radeon_crtc->crtc_id == 0)
1580 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1581 radeon_legacy_atom_fixup(crtc);
771fe6b9 1582 }
bcc1c2a1 1583 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1584 atombios_overscan_setup(crtc, mode, adjusted_mode);
1585 atombios_scaler_setup(crtc);
771fe6b9
JG		 1586 return 0;
1587}
1588
1589static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1590 struct drm_display_mode *mode,
1591 struct drm_display_mode *adjusted_mode)
1592{
c93bb85b
JG		 1593 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1594 return false;
771fe6b9
JG		 1595 return true;
1596}
1597
1598static void atombios_crtc_prepare(struct drm_crtc *crtc)
1599{
267364ac
AD		 1600 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1601
1602 /* pick pll */
1603 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1604
37b4390e 1605 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1606 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1607}
1608
1609static void atombios_crtc_commit(struct drm_crtc *crtc)
1610{
1611 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1612 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1613}
1614
37f9003b
AD		 1615static void atombios_crtc_disable(struct drm_crtc *crtc)
1616{
1617 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
8e8e523d
AD		 1618 struct radeon_atom_ss ss;
1619
37f9003b
AD		 1620 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1621
1622 switch (radeon_crtc->pll_id) {
1623 case ATOM_PPLL1:
1624 case ATOM_PPLL2:
1625 /* disable the ppll */
1626 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
8e8e523d 1627 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
37f9003b
AD		 1628 break;
1629 default:
1630 break;
1631 }
1632 radeon_crtc->pll_id = -1;
1633}
1634
771fe6b9
JG		 1635static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1636 .dpms = atombios_crtc_dpms,
1637 .mode_fixup = atombios_crtc_mode_fixup,
1638 .mode_set = atombios_crtc_mode_set,
1639 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1640 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1641 .prepare = atombios_crtc_prepare,
1642 .commit = atombios_crtc_commit,
068143d3 1643 .load_lut = radeon_crtc_load_lut,
37f9003b 1644 .disable = atombios_crtc_disable,
771fe6b9
JG		 1645};
1646
1647void radeon_atombios_init_crtc(struct drm_device *dev,
1648 struct radeon_crtc *radeon_crtc)
1649{
bcc1c2a1
AD		 1650 struct radeon_device *rdev = dev->dev_private;
1651
1652 if (ASIC_IS_DCE4(rdev)) {
1653 switch (radeon_crtc->crtc_id) {
1654 case 0:
1655 default:
12d7798f 1656 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1657 break;
1658 case 1:
12d7798f 1659 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1660 break;
1661 case 2:
12d7798f 1662 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1663 break;
1664 case 3:
12d7798f 1665 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1666 break;
1667 case 4:
12d7798f 1668 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1669 break;
1670 case 5:
12d7798f 1671 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1672 break;
1673 }
1674 } else {
1675 if (radeon_crtc->crtc_id == 1)
1676 radeon_crtc->crtc_offset =
1677 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1678 else
1679 radeon_crtc->crtc_offset = 0;
1680 }
1681 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1682 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1683}
Linux kernel - Deliverables
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