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746c1aa4 DA |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
8d1c702a | 25 | * Jerome Glisse |
746c1aa4 | 26 | */ |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
746c1aa4 DA |
29 | #include "radeon.h" |
30 | ||
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
760285e7 | 33 | #include <drm/drm_dp_helper.h> |
746c1aa4 | 34 | |
f92a8b67 | 35 | /* move these to drm_dp_helper.c/h */ |
5801ead6 | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
1a644cd4 | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
5801ead6 AD |
38 | |
39 | static char *voltage_names[] = { | |
40 | "0.4V", "0.6V", "0.8V", "1.2V" | |
41 | }; | |
42 | static char *pre_emph_names[] = { | |
43 | "0dB", "3.5dB", "6dB", "9.5dB" | |
44 | }; | |
f92a8b67 | 45 | |
224d94b1 | 46 | /***** radeon AUX functions *****/ |
34be8c9a AD |
47 | |
48 | /* Atom needs data in little endian format | |
49 | * so swap as appropriate when copying data to | |
50 | * or from atom. Note that atom operates on | |
51 | * dw units. | |
52 | */ | |
4543eda5 | 53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
34be8c9a AD |
54 | { |
55 | #ifdef __BIG_ENDIAN | |
56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ | |
57 | u32 *dst32, *src32; | |
58 | int i; | |
59 | ||
60 | memcpy(src_tmp, src, num_bytes); | |
61 | src32 = (u32 *)src_tmp; | |
62 | dst32 = (u32 *)dst_tmp; | |
63 | if (to_le) { | |
64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
65 | dst32[i] = cpu_to_le32(src32[i]); | |
66 | memcpy(dst, dst_tmp, num_bytes); | |
67 | } else { | |
68 | u8 dws = num_bytes & ~3; | |
69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
70 | dst32[i] = le32_to_cpu(src32[i]); | |
71 | memcpy(dst, dst_tmp, dws); | |
72 | if (num_bytes % 4) { | |
73 | for (i = 0; i < (num_bytes % 4); i++) | |
74 | dst[dws+i] = dst_tmp[dws+i]; | |
75 | } | |
76 | } | |
77 | #else | |
78 | memcpy(dst, src, num_bytes); | |
79 | #endif | |
80 | } | |
81 | ||
224d94b1 AD |
82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; | |
84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; | |
f92a8b67 AD |
85 | }; |
86 | ||
224d94b1 AD |
87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, | |
89 | u8 *recv, int recv_size, | |
90 | u8 delay, u8 *ack) | |
91 | { | |
92 | struct drm_device *dev = chan->dev; | |
93 | struct radeon_device *rdev = dev->dev_private; | |
94 | union aux_channel_transaction args; | |
95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); | |
96 | unsigned char *base; | |
97 | int recv_bytes; | |
98 | ||
99 | memset(&args, 0, sizeof(args)); | |
f92a8b67 | 100 | |
97412a7a | 101 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
224d94b1 | 102 | |
4543eda5 | 103 | radeon_atom_copy_swap(base, send, send_bytes, true); |
224d94b1 | 104 | |
34be8c9a AD |
105 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
106 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); | |
224d94b1 AD |
107 | args.v1.ucDataOutLen = 0; |
108 | args.v1.ucChannelID = chan->rec.i2c_id; | |
109 | args.v1.ucDelay = delay / 10; | |
110 | if (ASIC_IS_DCE4(rdev)) | |
111 | args.v2.ucHPD_ID = chan->rec.hpd; | |
112 | ||
113 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
114 | ||
115 | *ack = args.v1.ucReplyStatus; | |
116 | ||
117 | /* timeout */ | |
118 | if (args.v1.ucReplyStatus == 1) { | |
119 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); | |
120 | return -ETIMEDOUT; | |
121 | } | |
122 | ||
123 | /* flags not zero */ | |
124 | if (args.v1.ucReplyStatus == 2) { | |
125 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); | |
126 | return -EBUSY; | |
127 | } | |
128 | ||
129 | /* error */ | |
130 | if (args.v1.ucReplyStatus == 3) { | |
131 | DRM_DEBUG_KMS("dp_aux_ch error\n"); | |
132 | return -EIO; | |
133 | } | |
134 | ||
135 | recv_bytes = args.v1.ucDataOutLen; | |
136 | if (recv_bytes > recv_size) | |
137 | recv_bytes = recv_size; | |
138 | ||
139 | if (recv && recv_size) | |
4543eda5 | 140 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
224d94b1 AD |
141 | |
142 | return recv_bytes; | |
143 | } | |
144 | ||
145 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, | |
146 | u16 address, u8 *send, u8 send_bytes, u8 delay) | |
f92a8b67 | 147 | { |
224d94b1 AD |
148 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
149 | int ret; | |
150 | u8 msg[20]; | |
151 | int msg_bytes = send_bytes + 4; | |
152 | u8 ack; | |
6375bda0 | 153 | unsigned retry; |
5801ead6 | 154 | |
224d94b1 AD |
155 | if (send_bytes > 16) |
156 | return -1; | |
5801ead6 | 157 | |
224d94b1 AD |
158 | msg[0] = address; |
159 | msg[1] = address >> 8; | |
6b27f7f0 | 160 | msg[2] = DP_AUX_NATIVE_WRITE << 4; |
224d94b1 AD |
161 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
162 | memcpy(&msg[4], send, send_bytes); | |
f92a8b67 | 163 | |
2138681b | 164 | for (retry = 0; retry < 7; retry++) { |
224d94b1 AD |
165 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
166 | msg, msg_bytes, NULL, 0, delay, &ack); | |
4f332844 AD |
167 | if (ret == -EBUSY) |
168 | continue; | |
169 | else if (ret < 0) | |
224d94b1 | 170 | return ret; |
6b27f7f0 TR |
171 | ack >>= 4; |
172 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) | |
6375bda0 | 173 | return send_bytes; |
6b27f7f0 | 174 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
224d94b1 AD |
175 | udelay(400); |
176 | else | |
177 | return -EIO; | |
f92a8b67 AD |
178 | } |
179 | ||
6375bda0 | 180 | return -EIO; |
f92a8b67 AD |
181 | } |
182 | ||
224d94b1 AD |
183 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
184 | u16 address, u8 *recv, int recv_bytes, u8 delay) | |
f92a8b67 | 185 | { |
224d94b1 AD |
186 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
187 | u8 msg[4]; | |
188 | int msg_bytes = 4; | |
189 | u8 ack; | |
190 | int ret; | |
6375bda0 | 191 | unsigned retry; |
5801ead6 | 192 | |
224d94b1 AD |
193 | msg[0] = address; |
194 | msg[1] = address >> 8; | |
6b27f7f0 | 195 | msg[2] = DP_AUX_NATIVE_READ << 4; |
224d94b1 | 196 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
5801ead6 | 197 | |
2138681b | 198 | for (retry = 0; retry < 7; retry++) { |
224d94b1 AD |
199 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
200 | msg, msg_bytes, recv, recv_bytes, delay, &ack); | |
4f332844 AD |
201 | if (ret == -EBUSY) |
202 | continue; | |
203 | else if (ret < 0) | |
224d94b1 | 204 | return ret; |
6b27f7f0 TR |
205 | ack >>= 4; |
206 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) | |
224d94b1 | 207 | return ret; |
6b27f7f0 | 208 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
224d94b1 | 209 | udelay(400); |
109bc10d AD |
210 | else if (ret == 0) |
211 | return -EPROTO; | |
224d94b1 AD |
212 | else |
213 | return -EIO; | |
214 | } | |
6375bda0 AD |
215 | |
216 | return -EIO; | |
224d94b1 | 217 | } |
f92a8b67 | 218 | |
224d94b1 AD |
219 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
220 | u16 reg, u8 val) | |
221 | { | |
222 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); | |
223 | } | |
224 | ||
225 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, | |
226 | u16 reg) | |
227 | { | |
228 | u8 val = 0; | |
229 | ||
230 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); | |
231 | ||
232 | return val; | |
233 | } | |
234 | ||
235 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |
236 | u8 write_byte, u8 *read_byte) | |
237 | { | |
238 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
239 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; | |
240 | u16 address = algo_data->address; | |
241 | u8 msg[5]; | |
242 | u8 reply[2]; | |
243 | unsigned retry; | |
244 | int msg_bytes; | |
245 | int reply_bytes = 1; | |
246 | int ret; | |
247 | u8 ack; | |
248 | ||
249 | /* Set up the command byte */ | |
250 | if (mode & MODE_I2C_READ) | |
6b27f7f0 | 251 | msg[2] = DP_AUX_I2C_READ << 4; |
224d94b1 | 252 | else |
6b27f7f0 | 253 | msg[2] = DP_AUX_I2C_WRITE << 4; |
224d94b1 AD |
254 | |
255 | if (!(mode & MODE_I2C_STOP)) | |
6b27f7f0 | 256 | msg[2] |= DP_AUX_I2C_MOT << 4; |
224d94b1 AD |
257 | |
258 | msg[0] = address; | |
259 | msg[1] = address >> 8; | |
260 | ||
261 | switch (mode) { | |
262 | case MODE_I2C_WRITE: | |
263 | msg_bytes = 5; | |
264 | msg[3] = msg_bytes << 4; | |
265 | msg[4] = write_byte; | |
266 | break; | |
267 | case MODE_I2C_READ: | |
268 | msg_bytes = 4; | |
269 | msg[3] = msg_bytes << 4; | |
270 | break; | |
f92a8b67 | 271 | default: |
224d94b1 AD |
272 | msg_bytes = 4; |
273 | msg[3] = 3 << 4; | |
f92a8b67 | 274 | break; |
f92a8b67 AD |
275 | } |
276 | ||
2138681b | 277 | for (retry = 0; retry < 7; retry++) { |
224d94b1 AD |
278 | ret = radeon_process_aux_ch(auxch, |
279 | msg, msg_bytes, reply, reply_bytes, 0, &ack); | |
4f332844 AD |
280 | if (ret == -EBUSY) |
281 | continue; | |
282 | else if (ret < 0) { | |
224d94b1 AD |
283 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
284 | return ret; | |
285 | } | |
f92a8b67 | 286 | |
6b27f7f0 TR |
287 | switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
288 | case DP_AUX_NATIVE_REPLY_ACK: | |
224d94b1 AD |
289 | /* I2C-over-AUX Reply field is only valid |
290 | * when paired with AUX ACK. | |
291 | */ | |
292 | break; | |
6b27f7f0 | 293 | case DP_AUX_NATIVE_REPLY_NACK: |
224d94b1 AD |
294 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
295 | return -EREMOTEIO; | |
6b27f7f0 | 296 | case DP_AUX_NATIVE_REPLY_DEFER: |
224d94b1 AD |
297 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
298 | udelay(400); | |
299 | continue; | |
300 | default: | |
301 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); | |
302 | return -EREMOTEIO; | |
303 | } | |
5801ead6 | 304 | |
6b27f7f0 TR |
305 | switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { |
306 | case DP_AUX_I2C_REPLY_ACK: | |
224d94b1 AD |
307 | if (mode == MODE_I2C_READ) |
308 | *read_byte = reply[0]; | |
309 | return ret; | |
6b27f7f0 | 310 | case DP_AUX_I2C_REPLY_NACK: |
224d94b1 AD |
311 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
312 | return -EREMOTEIO; | |
6b27f7f0 | 313 | case DP_AUX_I2C_REPLY_DEFER: |
224d94b1 AD |
314 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
315 | udelay(400); | |
316 | break; | |
317 | default: | |
318 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); | |
319 | return -EREMOTEIO; | |
320 | } | |
321 | } | |
5801ead6 | 322 | |
091264f0 | 323 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
224d94b1 | 324 | return -EREMOTEIO; |
5801ead6 AD |
325 | } |
326 | ||
224d94b1 AD |
327 | /***** general DP utility functions *****/ |
328 | ||
5801ead6 | 329 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
224d94b1 | 330 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
5801ead6 AD |
331 | |
332 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |
333 | int lane_count, | |
334 | u8 train_set[4]) | |
335 | { | |
336 | u8 v = 0; | |
337 | u8 p = 0; | |
338 | int lane; | |
339 | ||
340 | for (lane = 0; lane < lane_count; lane++) { | |
0f037bde DV |
341 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
342 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
5801ead6 | 343 | |
d9fdaafb | 344 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
53c1e09f AD |
345 | lane, |
346 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | |
347 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
348 | |
349 | if (this_v > v) | |
350 | v = this_v; | |
351 | if (this_p > p) | |
352 | p = this_p; | |
353 | } | |
354 | ||
355 | if (v >= DP_VOLTAGE_MAX) | |
224d94b1 | 356 | v |= DP_TRAIN_MAX_SWING_REACHED; |
5801ead6 | 357 | |
224d94b1 AD |
358 | if (p >= DP_PRE_EMPHASIS_MAX) |
359 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
5801ead6 | 360 | |
d9fdaafb | 361 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
53c1e09f AD |
362 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
363 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
364 | |
365 | for (lane = 0; lane < 4; lane++) | |
366 | train_set[lane] = v | p; | |
367 | } | |
368 | ||
224d94b1 AD |
369 | /* convert bits per color to bits per pixel */ |
370 | /* get bpc from the EDID */ | |
371 | static int convert_bpc_to_bpp(int bpc) | |
746c1aa4 | 372 | { |
224d94b1 AD |
373 | if (bpc == 0) |
374 | return 24; | |
375 | else | |
376 | return bpc * 3; | |
377 | } | |
746c1aa4 | 378 | |
224d94b1 AD |
379 | /* get the max pix clock supported by the link rate and lane num */ |
380 | static int dp_get_max_dp_pix_clock(int link_rate, | |
381 | int lane_num, | |
382 | int bpp) | |
383 | { | |
384 | return (link_rate * lane_num * 8) / bpp; | |
385 | } | |
834b2904 | 386 | |
224d94b1 | 387 | /***** radeon specific DP functions *****/ |
746c1aa4 | 388 | |
224d94b1 AD |
389 | /* First get the min lane# when low rate is used according to pixel clock |
390 | * (prefer low rate), second check max lane# supported by DP panel, | |
391 | * if the max lane# < low rate lane# then use max lane# instead. | |
392 | */ | |
393 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, | |
394 | u8 dpcd[DP_DPCD_SIZE], | |
395 | int pix_clock) | |
396 | { | |
eccea792 | 397 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
3b5c662e | 398 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
397fe157 | 399 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
224d94b1 AD |
400 | int lane_num; |
401 | int max_dp_pix_clock; | |
402 | ||
403 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { | |
404 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); | |
405 | if (pix_clock <= max_dp_pix_clock) | |
406 | break; | |
834b2904 | 407 | } |
746c1aa4 | 408 | |
224d94b1 | 409 | return lane_num; |
746c1aa4 DA |
410 | } |
411 | ||
224d94b1 AD |
412 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
413 | u8 dpcd[DP_DPCD_SIZE], | |
414 | int pix_clock) | |
746c1aa4 | 415 | { |
eccea792 | 416 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
417 | int lane_num, max_pix_clock; |
418 | ||
fdca78c3 AD |
419 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
420 | ENCODER_OBJECT_ID_NUTMEG) | |
224d94b1 AD |
421 | return 270000; |
422 | ||
423 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); | |
424 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); | |
425 | if (pix_clock <= max_pix_clock) | |
426 | return 162000; | |
427 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); | |
428 | if (pix_clock <= max_pix_clock) | |
429 | return 270000; | |
430 | if (radeon_connector_is_dp12_capable(connector)) { | |
431 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); | |
432 | if (pix_clock <= max_pix_clock) | |
433 | return 540000; | |
834b2904 | 434 | } |
224d94b1 | 435 | |
3b5c662e | 436 | return drm_dp_max_link_rate(dpcd); |
746c1aa4 DA |
437 | } |
438 | ||
834b2904 AD |
439 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
440 | int action, int dp_clock, | |
224d94b1 | 441 | u8 ucconfig, u8 lane_num) |
5801ead6 AD |
442 | { |
443 | DP_ENCODER_SERVICE_PARAMETERS args; | |
444 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
445 | ||
446 | memset(&args, 0, sizeof(args)); | |
447 | args.ucLinkClock = dp_clock / 10; | |
448 | args.ucConfig = ucconfig; | |
449 | args.ucAction = action; | |
450 | args.ucLaneNum = lane_num; | |
451 | args.ucStatus = 0; | |
452 | ||
453 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
454 | return args.ucStatus; | |
455 | } | |
456 | ||
457 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) | |
458 | { | |
459 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
460 | struct drm_device *dev = radeon_connector->base.dev; | |
461 | struct radeon_device *rdev = dev->dev_private; | |
462 | ||
463 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, | |
464 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); | |
465 | } | |
466 | ||
40c5d876 AJ |
467 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
468 | { | |
469 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
470 | u8 buf[3]; | |
471 | ||
472 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
473 | return; | |
474 | ||
475 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) | |
476 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
477 | buf[0], buf[1], buf[2]); | |
478 | ||
479 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) | |
480 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
481 | buf[0], buf[1], buf[2]); | |
482 | } | |
483 | ||
9fa05c98 | 484 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
746c1aa4 | 485 | { |
5801ead6 | 486 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
1a644cd4 | 487 | u8 msg[DP_DPCD_SIZE]; |
224d94b1 | 488 | int ret, i; |
746c1aa4 | 489 | |
1a644cd4 DV |
490 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, |
491 | DP_DPCD_SIZE, 0); | |
834b2904 | 492 | if (ret > 0) { |
1a644cd4 | 493 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
224d94b1 | 494 | DRM_DEBUG_KMS("DPCD: "); |
1a644cd4 | 495 | for (i = 0; i < DP_DPCD_SIZE; i++) |
224d94b1 AD |
496 | DRM_DEBUG_KMS("%02x ", msg[i]); |
497 | DRM_DEBUG_KMS("\n"); | |
40c5d876 AJ |
498 | |
499 | radeon_dp_probe_oui(radeon_connector); | |
500 | ||
9fa05c98 | 501 | return true; |
746c1aa4 | 502 | } |
5801ead6 | 503 | dig_connector->dpcd[0] = 0; |
9fa05c98 | 504 | return false; |
746c1aa4 DA |
505 | } |
506 | ||
386d4d75 AD |
507 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
508 | struct drm_connector *connector) | |
224d94b1 AD |
509 | { |
510 | struct drm_device *dev = encoder->dev; | |
511 | struct radeon_device *rdev = dev->dev_private; | |
00dfb8df | 512 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
224d94b1 | 513 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
0ceb996c AD |
514 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
515 | u8 tmp; | |
224d94b1 AD |
516 | |
517 | if (!ASIC_IS_DCE4(rdev)) | |
386d4d75 | 518 | return panel_mode; |
224d94b1 | 519 | |
0ceb996c AD |
520 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
521 | /* DP bridge chips */ | |
522 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
523 | if (tmp & 1) | |
524 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
525 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || | |
526 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) | |
304a4840 AD |
527 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
528 | else | |
0ceb996c | 529 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
304a4840 | 530 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
0ceb996c AD |
531 | /* eDP */ |
532 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
00dfb8df AD |
533 | if (tmp & 1) |
534 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
535 | } | |
224d94b1 | 536 | |
386d4d75 | 537 | return panel_mode; |
224d94b1 AD |
538 | } |
539 | ||
5801ead6 | 540 | void radeon_dp_set_link_config(struct drm_connector *connector, |
e811f5ae | 541 | const struct drm_display_mode *mode) |
5801ead6 | 542 | { |
224d94b1 | 543 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5801ead6 AD |
544 | struct radeon_connector_atom_dig *dig_connector; |
545 | ||
5801ead6 AD |
546 | if (!radeon_connector->con_priv) |
547 | return; | |
548 | dig_connector = radeon_connector->con_priv; | |
549 | ||
224d94b1 AD |
550 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
551 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { | |
552 | dig_connector->dp_clock = | |
553 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
554 | dig_connector->dp_lane_count = | |
555 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); | |
556 | } | |
5801ead6 AD |
557 | } |
558 | ||
224d94b1 | 559 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
560 | struct drm_display_mode *mode) |
561 | { | |
224d94b1 AD |
562 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
563 | struct radeon_connector_atom_dig *dig_connector; | |
564 | int dp_clock; | |
5801ead6 | 565 | |
224d94b1 AD |
566 | if (!radeon_connector->con_priv) |
567 | return MODE_CLOCK_HIGH; | |
568 | dig_connector = radeon_connector->con_priv; | |
569 | ||
570 | dp_clock = | |
571 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
572 | ||
573 | if ((dp_clock == 540000) && | |
574 | (!radeon_connector_is_dp12_capable(connector))) | |
575 | return MODE_CLOCK_HIGH; | |
576 | ||
577 | return MODE_OK; | |
5801ead6 AD |
578 | } |
579 | ||
224d94b1 AD |
580 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
581 | u8 link_status[DP_LINK_STATUS_SIZE]) | |
746c1aa4 DA |
582 | { |
583 | int ret; | |
834b2904 AD |
584 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
585 | link_status, DP_LINK_STATUS_SIZE, 100); | |
586 | if (ret <= 0) { | |
746c1aa4 DA |
587 | return false; |
588 | } | |
589 | ||
08fcd72b | 590 | DRM_DEBUG_KMS("link status %6ph\n", link_status); |
746c1aa4 DA |
591 | return true; |
592 | } | |
593 | ||
d5811e87 AD |
594 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
595 | { | |
596 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
597 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
598 | ||
599 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) | |
600 | return false; | |
1ffdff13 | 601 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
d5811e87 AD |
602 | return false; |
603 | return true; | |
604 | } | |
605 | ||
224d94b1 AD |
606 | struct radeon_dp_link_train_info { |
607 | struct radeon_device *rdev; | |
608 | struct drm_encoder *encoder; | |
609 | struct drm_connector *connector; | |
610 | struct radeon_connector *radeon_connector; | |
611 | int enc_id; | |
612 | int dp_clock; | |
613 | int dp_lane_count; | |
224d94b1 | 614 | bool tp3_supported; |
1a644cd4 | 615 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
224d94b1 AD |
616 | u8 train_set[4]; |
617 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
618 | u8 tries; | |
5a96a899 | 619 | bool use_dpencoder; |
224d94b1 | 620 | }; |
5801ead6 | 621 | |
224d94b1 | 622 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 623 | { |
224d94b1 AD |
624 | /* set the initial vs/emph on the source */ |
625 | atombios_dig_transmitter_setup(dp_info->encoder, | |
626 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, | |
627 | 0, dp_info->train_set[0]); /* sets all lanes at once */ | |
628 | ||
629 | /* set the vs/emph on the sink */ | |
630 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, | |
631 | dp_info->train_set, dp_info->dp_lane_count, 0); | |
5801ead6 AD |
632 | } |
633 | ||
224d94b1 | 634 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
746c1aa4 | 635 | { |
224d94b1 | 636 | int rtp = 0; |
746c1aa4 | 637 | |
224d94b1 | 638 | /* set training pattern on the source */ |
5a96a899 | 639 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
224d94b1 AD |
640 | switch (tp) { |
641 | case DP_TRAINING_PATTERN_1: | |
642 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; | |
643 | break; | |
644 | case DP_TRAINING_PATTERN_2: | |
645 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; | |
646 | break; | |
647 | case DP_TRAINING_PATTERN_3: | |
648 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; | |
649 | break; | |
650 | } | |
651 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); | |
652 | } else { | |
653 | switch (tp) { | |
654 | case DP_TRAINING_PATTERN_1: | |
655 | rtp = 0; | |
656 | break; | |
657 | case DP_TRAINING_PATTERN_2: | |
658 | rtp = 1; | |
659 | break; | |
660 | } | |
661 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, | |
662 | dp_info->dp_clock, dp_info->enc_id, rtp); | |
663 | } | |
746c1aa4 | 664 | |
224d94b1 AD |
665 | /* enable training pattern on the sink */ |
666 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); | |
746c1aa4 DA |
667 | } |
668 | ||
224d94b1 | 669 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 670 | { |
386d4d75 AD |
671 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
672 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
224d94b1 | 673 | u8 tmp; |
5801ead6 | 674 | |
224d94b1 AD |
675 | /* power up the sink */ |
676 | if (dp_info->dpcd[0] >= 0x11) | |
677 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
678 | DP_SET_POWER, DP_SET_POWER_D0); | |
679 | ||
680 | /* possibly enable downspread on the sink */ | |
681 | if (dp_info->dpcd[3] & 0x1) | |
682 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
683 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); | |
684 | else | |
685 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
686 | DP_DOWNSPREAD_CTRL, 0); | |
5801ead6 | 687 | |
386d4d75 AD |
688 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
689 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { | |
690 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); | |
691 | } | |
5801ead6 | 692 | |
224d94b1 AD |
693 | /* set the lane count on the sink */ |
694 | tmp = dp_info->dp_lane_count; | |
27f75dc6 | 695 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
224d94b1 AD |
696 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
697 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); | |
5801ead6 | 698 | |
224d94b1 | 699 | /* set the link rate on the sink */ |
3b5c662e | 700 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
224d94b1 | 701 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
5801ead6 | 702 | |
224d94b1 | 703 | /* start training on the source */ |
5a96a899 | 704 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
705 | atombios_dig_encoder_setup(dp_info->encoder, |
706 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); | |
5801ead6 | 707 | else |
224d94b1 AD |
708 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
709 | dp_info->dp_clock, dp_info->enc_id, 0); | |
5801ead6 | 710 | |
5801ead6 | 711 | /* disable the training pattern on the sink */ |
224d94b1 AD |
712 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
713 | DP_TRAINING_PATTERN_SET, | |
714 | DP_TRAINING_PATTERN_DISABLE); | |
715 | ||
716 | return 0; | |
717 | } | |
5801ead6 | 718 | |
224d94b1 AD |
719 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
720 | { | |
5801ead6 | 721 | udelay(400); |
5801ead6 | 722 | |
224d94b1 AD |
723 | /* disable the training pattern on the sink */ |
724 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
725 | DP_TRAINING_PATTERN_SET, | |
726 | DP_TRAINING_PATTERN_DISABLE); | |
727 | ||
728 | /* disable the training pattern on the source */ | |
5a96a899 | 729 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
730 | atombios_dig_encoder_setup(dp_info->encoder, |
731 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); | |
732 | else | |
733 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, | |
734 | dp_info->dp_clock, dp_info->enc_id, 0); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) | |
740 | { | |
741 | bool clock_recovery; | |
742 | u8 voltage; | |
743 | int i; | |
744 | ||
745 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); | |
746 | memset(dp_info->train_set, 0, 4); | |
747 | radeon_dp_update_vs_emph(dp_info); | |
748 | ||
749 | udelay(400); | |
5fbfce7f | 750 | |
5801ead6 AD |
751 | /* clock recovery loop */ |
752 | clock_recovery = false; | |
224d94b1 | 753 | dp_info->tries = 0; |
5801ead6 | 754 | voltage = 0xff; |
224d94b1 | 755 | while (1) { |
1a644cd4 | 756 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
224d94b1 | 757 | |
8d1c702a JG |
758 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
759 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 760 | break; |
8d1c702a | 761 | } |
5801ead6 | 762 | |
01916270 | 763 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
764 | clock_recovery = true; |
765 | break; | |
766 | } | |
767 | ||
224d94b1 AD |
768 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
769 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
5801ead6 AD |
770 | break; |
771 | } | |
224d94b1 | 772 | if (i == dp_info->dp_lane_count) { |
5801ead6 AD |
773 | DRM_ERROR("clock recovery reached max voltage\n"); |
774 | break; | |
775 | } | |
776 | ||
224d94b1 AD |
777 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
778 | ++dp_info->tries; | |
779 | if (dp_info->tries == 5) { | |
5801ead6 AD |
780 | DRM_ERROR("clock recovery tried 5 times\n"); |
781 | break; | |
782 | } | |
783 | } else | |
224d94b1 | 784 | dp_info->tries = 0; |
5801ead6 | 785 | |
224d94b1 | 786 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
5801ead6 AD |
787 | |
788 | /* Compute new train_set as requested by sink */ | |
224d94b1 AD |
789 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
790 | ||
791 | radeon_dp_update_vs_emph(dp_info); | |
5801ead6 | 792 | } |
224d94b1 | 793 | if (!clock_recovery) { |
5801ead6 | 794 | DRM_ERROR("clock recovery failed\n"); |
224d94b1 AD |
795 | return -1; |
796 | } else { | |
d9fdaafb | 797 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
798 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
799 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
53c1e09f | 800 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
801 | return 0; |
802 | } | |
803 | } | |
5801ead6 | 804 | |
224d94b1 AD |
805 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
806 | { | |
807 | bool channel_eq; | |
5801ead6 | 808 | |
224d94b1 AD |
809 | if (dp_info->tp3_supported) |
810 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); | |
bcc1c2a1 | 811 | else |
224d94b1 | 812 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
5801ead6 AD |
813 | |
814 | /* channel equalization loop */ | |
224d94b1 | 815 | dp_info->tries = 0; |
5801ead6 | 816 | channel_eq = false; |
224d94b1 | 817 | while (1) { |
1a644cd4 | 818 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
224d94b1 | 819 | |
8d1c702a JG |
820 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
821 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 822 | break; |
8d1c702a | 823 | } |
5801ead6 | 824 | |
1ffdff13 | 825 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
826 | channel_eq = true; |
827 | break; | |
828 | } | |
829 | ||
830 | /* Try 5 times */ | |
224d94b1 | 831 | if (dp_info->tries > 5) { |
5801ead6 AD |
832 | DRM_ERROR("channel eq failed: 5 tries\n"); |
833 | break; | |
834 | } | |
835 | ||
836 | /* Compute new train_set as requested by sink */ | |
224d94b1 | 837 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
5801ead6 | 838 | |
224d94b1 AD |
839 | radeon_dp_update_vs_emph(dp_info); |
840 | dp_info->tries++; | |
5801ead6 AD |
841 | } |
842 | ||
224d94b1 | 843 | if (!channel_eq) { |
5801ead6 | 844 | DRM_ERROR("channel eq failed\n"); |
224d94b1 AD |
845 | return -1; |
846 | } else { | |
d9fdaafb | 847 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
848 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
849 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | |
53c1e09f | 850 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
851 | return 0; |
852 | } | |
5801ead6 AD |
853 | } |
854 | ||
224d94b1 AD |
855 | void radeon_dp_link_train(struct drm_encoder *encoder, |
856 | struct drm_connector *connector) | |
746c1aa4 | 857 | { |
224d94b1 AD |
858 | struct drm_device *dev = encoder->dev; |
859 | struct radeon_device *rdev = dev->dev_private; | |
860 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
861 | struct radeon_encoder_atom_dig *dig; | |
862 | struct radeon_connector *radeon_connector; | |
863 | struct radeon_connector_atom_dig *dig_connector; | |
864 | struct radeon_dp_link_train_info dp_info; | |
5a96a899 JG |
865 | int index; |
866 | u8 tmp, frev, crev; | |
746c1aa4 | 867 | |
224d94b1 AD |
868 | if (!radeon_encoder->enc_priv) |
869 | return; | |
870 | dig = radeon_encoder->enc_priv; | |
746c1aa4 | 871 | |
224d94b1 AD |
872 | radeon_connector = to_radeon_connector(connector); |
873 | if (!radeon_connector->con_priv) | |
874 | return; | |
875 | dig_connector = radeon_connector->con_priv; | |
834b2904 | 876 | |
224d94b1 AD |
877 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
878 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) | |
879 | return; | |
746c1aa4 | 880 | |
5a96a899 JG |
881 | /* DPEncoderService newer than 1.1 can't program properly the |
882 | * training pattern. When facing such version use the | |
883 | * DIGXEncoderControl (X== 1 | 2) | |
884 | */ | |
885 | dp_info.use_dpencoder = true; | |
886 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
887 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { | |
888 | if (crev > 1) { | |
889 | dp_info.use_dpencoder = false; | |
890 | } | |
891 | } | |
892 | ||
224d94b1 AD |
893 | dp_info.enc_id = 0; |
894 | if (dig->dig_encoder) | |
895 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; | |
896 | else | |
897 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; | |
898 | if (dig->linkb) | |
899 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; | |
900 | else | |
901 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; | |
834b2904 | 902 | |
224d94b1 AD |
903 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
904 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) | |
905 | dp_info.tp3_supported = true; | |
906 | else | |
907 | dp_info.tp3_supported = false; | |
908 | ||
1a644cd4 | 909 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
224d94b1 AD |
910 | dp_info.rdev = rdev; |
911 | dp_info.encoder = encoder; | |
912 | dp_info.connector = connector; | |
913 | dp_info.radeon_connector = radeon_connector; | |
914 | dp_info.dp_lane_count = dig_connector->dp_lane_count; | |
915 | dp_info.dp_clock = dig_connector->dp_clock; | |
916 | ||
917 | if (radeon_dp_link_train_init(&dp_info)) | |
918 | goto done; | |
919 | if (radeon_dp_link_train_cr(&dp_info)) | |
920 | goto done; | |
921 | if (radeon_dp_link_train_ce(&dp_info)) | |
922 | goto done; | |
923 | done: | |
924 | if (radeon_dp_link_train_finish(&dp_info)) | |
925 | return; | |
746c1aa4 | 926 | } |