Commit | Line | Data |
---|---|---|
746c1aa4 DA |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
8d1c702a | 25 | * Jerome Glisse |
746c1aa4 | 26 | */ |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
746c1aa4 DA |
29 | #include "radeon.h" |
30 | ||
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
760285e7 | 33 | #include <drm/drm_dp_helper.h> |
746c1aa4 | 34 | |
f92a8b67 | 35 | /* move these to drm_dp_helper.c/h */ |
5801ead6 | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
1a644cd4 | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
5801ead6 AD |
38 | |
39 | static char *voltage_names[] = { | |
40 | "0.4V", "0.6V", "0.8V", "1.2V" | |
41 | }; | |
42 | static char *pre_emph_names[] = { | |
43 | "0dB", "3.5dB", "6dB", "9.5dB" | |
44 | }; | |
f92a8b67 | 45 | |
224d94b1 AD |
46 | /***** radeon AUX functions *****/ |
47 | union aux_channel_transaction { | |
48 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; | |
49 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; | |
f92a8b67 AD |
50 | }; |
51 | ||
224d94b1 AD |
52 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
53 | u8 *send, int send_bytes, | |
54 | u8 *recv, int recv_size, | |
55 | u8 delay, u8 *ack) | |
56 | { | |
57 | struct drm_device *dev = chan->dev; | |
58 | struct radeon_device *rdev = dev->dev_private; | |
59 | union aux_channel_transaction args; | |
60 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); | |
61 | unsigned char *base; | |
62 | int recv_bytes; | |
63 | ||
64 | memset(&args, 0, sizeof(args)); | |
f92a8b67 | 65 | |
97412a7a | 66 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
224d94b1 AD |
67 | |
68 | memcpy(base, send, send_bytes); | |
69 | ||
97412a7a AD |
70 | args.v1.lpAuxRequest = 0 + 4; |
71 | args.v1.lpDataOut = 16 + 4; | |
224d94b1 AD |
72 | args.v1.ucDataOutLen = 0; |
73 | args.v1.ucChannelID = chan->rec.i2c_id; | |
74 | args.v1.ucDelay = delay / 10; | |
75 | if (ASIC_IS_DCE4(rdev)) | |
76 | args.v2.ucHPD_ID = chan->rec.hpd; | |
77 | ||
78 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
79 | ||
80 | *ack = args.v1.ucReplyStatus; | |
81 | ||
82 | /* timeout */ | |
83 | if (args.v1.ucReplyStatus == 1) { | |
84 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); | |
85 | return -ETIMEDOUT; | |
86 | } | |
87 | ||
88 | /* flags not zero */ | |
89 | if (args.v1.ucReplyStatus == 2) { | |
90 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); | |
91 | return -EBUSY; | |
92 | } | |
93 | ||
94 | /* error */ | |
95 | if (args.v1.ucReplyStatus == 3) { | |
96 | DRM_DEBUG_KMS("dp_aux_ch error\n"); | |
97 | return -EIO; | |
98 | } | |
99 | ||
100 | recv_bytes = args.v1.ucDataOutLen; | |
101 | if (recv_bytes > recv_size) | |
102 | recv_bytes = recv_size; | |
103 | ||
104 | if (recv && recv_size) | |
105 | memcpy(recv, base + 16, recv_bytes); | |
106 | ||
107 | return recv_bytes; | |
108 | } | |
109 | ||
110 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, | |
111 | u16 address, u8 *send, u8 send_bytes, u8 delay) | |
f92a8b67 | 112 | { |
224d94b1 AD |
113 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
114 | int ret; | |
115 | u8 msg[20]; | |
116 | int msg_bytes = send_bytes + 4; | |
117 | u8 ack; | |
6375bda0 | 118 | unsigned retry; |
5801ead6 | 119 | |
224d94b1 AD |
120 | if (send_bytes > 16) |
121 | return -1; | |
5801ead6 | 122 | |
224d94b1 AD |
123 | msg[0] = address; |
124 | msg[1] = address >> 8; | |
125 | msg[2] = AUX_NATIVE_WRITE << 4; | |
126 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); | |
127 | memcpy(&msg[4], send, send_bytes); | |
f92a8b67 | 128 | |
6375bda0 | 129 | for (retry = 0; retry < 4; retry++) { |
224d94b1 AD |
130 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
131 | msg, msg_bytes, NULL, 0, delay, &ack); | |
4f332844 AD |
132 | if (ret == -EBUSY) |
133 | continue; | |
134 | else if (ret < 0) | |
224d94b1 AD |
135 | return ret; |
136 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
6375bda0 | 137 | return send_bytes; |
224d94b1 AD |
138 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
139 | udelay(400); | |
140 | else | |
141 | return -EIO; | |
f92a8b67 AD |
142 | } |
143 | ||
6375bda0 | 144 | return -EIO; |
f92a8b67 AD |
145 | } |
146 | ||
224d94b1 AD |
147 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
148 | u16 address, u8 *recv, int recv_bytes, u8 delay) | |
f92a8b67 | 149 | { |
224d94b1 AD |
150 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
151 | u8 msg[4]; | |
152 | int msg_bytes = 4; | |
153 | u8 ack; | |
154 | int ret; | |
6375bda0 | 155 | unsigned retry; |
5801ead6 | 156 | |
224d94b1 AD |
157 | msg[0] = address; |
158 | msg[1] = address >> 8; | |
159 | msg[2] = AUX_NATIVE_READ << 4; | |
160 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); | |
5801ead6 | 161 | |
6375bda0 | 162 | for (retry = 0; retry < 4; retry++) { |
224d94b1 AD |
163 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
164 | msg, msg_bytes, recv, recv_bytes, delay, &ack); | |
4f332844 AD |
165 | if (ret == -EBUSY) |
166 | continue; | |
167 | else if (ret < 0) | |
224d94b1 AD |
168 | return ret; |
169 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
170 | return ret; | |
171 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
172 | udelay(400); | |
109bc10d AD |
173 | else if (ret == 0) |
174 | return -EPROTO; | |
224d94b1 AD |
175 | else |
176 | return -EIO; | |
177 | } | |
6375bda0 AD |
178 | |
179 | return -EIO; | |
224d94b1 | 180 | } |
f92a8b67 | 181 | |
224d94b1 AD |
182 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
183 | u16 reg, u8 val) | |
184 | { | |
185 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); | |
186 | } | |
187 | ||
188 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, | |
189 | u16 reg) | |
190 | { | |
191 | u8 val = 0; | |
192 | ||
193 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); | |
194 | ||
195 | return val; | |
196 | } | |
197 | ||
198 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |
199 | u8 write_byte, u8 *read_byte) | |
200 | { | |
201 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
202 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; | |
203 | u16 address = algo_data->address; | |
204 | u8 msg[5]; | |
205 | u8 reply[2]; | |
206 | unsigned retry; | |
207 | int msg_bytes; | |
208 | int reply_bytes = 1; | |
209 | int ret; | |
210 | u8 ack; | |
211 | ||
212 | /* Set up the command byte */ | |
213 | if (mode & MODE_I2C_READ) | |
214 | msg[2] = AUX_I2C_READ << 4; | |
215 | else | |
216 | msg[2] = AUX_I2C_WRITE << 4; | |
217 | ||
218 | if (!(mode & MODE_I2C_STOP)) | |
219 | msg[2] |= AUX_I2C_MOT << 4; | |
220 | ||
221 | msg[0] = address; | |
222 | msg[1] = address >> 8; | |
223 | ||
224 | switch (mode) { | |
225 | case MODE_I2C_WRITE: | |
226 | msg_bytes = 5; | |
227 | msg[3] = msg_bytes << 4; | |
228 | msg[4] = write_byte; | |
229 | break; | |
230 | case MODE_I2C_READ: | |
231 | msg_bytes = 4; | |
232 | msg[3] = msg_bytes << 4; | |
233 | break; | |
f92a8b67 | 234 | default: |
224d94b1 AD |
235 | msg_bytes = 4; |
236 | msg[3] = 3 << 4; | |
f92a8b67 | 237 | break; |
f92a8b67 AD |
238 | } |
239 | ||
224d94b1 AD |
240 | for (retry = 0; retry < 4; retry++) { |
241 | ret = radeon_process_aux_ch(auxch, | |
242 | msg, msg_bytes, reply, reply_bytes, 0, &ack); | |
4f332844 AD |
243 | if (ret == -EBUSY) |
244 | continue; | |
245 | else if (ret < 0) { | |
224d94b1 AD |
246 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
247 | return ret; | |
248 | } | |
f92a8b67 | 249 | |
224d94b1 AD |
250 | switch (ack & AUX_NATIVE_REPLY_MASK) { |
251 | case AUX_NATIVE_REPLY_ACK: | |
252 | /* I2C-over-AUX Reply field is only valid | |
253 | * when paired with AUX ACK. | |
254 | */ | |
255 | break; | |
256 | case AUX_NATIVE_REPLY_NACK: | |
257 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
258 | return -EREMOTEIO; | |
259 | case AUX_NATIVE_REPLY_DEFER: | |
260 | DRM_DEBUG_KMS("aux_ch native defer\n"); | |
261 | udelay(400); | |
262 | continue; | |
263 | default: | |
264 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); | |
265 | return -EREMOTEIO; | |
266 | } | |
5801ead6 | 267 | |
224d94b1 AD |
268 | switch (ack & AUX_I2C_REPLY_MASK) { |
269 | case AUX_I2C_REPLY_ACK: | |
270 | if (mode == MODE_I2C_READ) | |
271 | *read_byte = reply[0]; | |
272 | return ret; | |
273 | case AUX_I2C_REPLY_NACK: | |
274 | DRM_DEBUG_KMS("aux_i2c nack\n"); | |
275 | return -EREMOTEIO; | |
276 | case AUX_I2C_REPLY_DEFER: | |
277 | DRM_DEBUG_KMS("aux_i2c defer\n"); | |
278 | udelay(400); | |
279 | break; | |
280 | default: | |
281 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); | |
282 | return -EREMOTEIO; | |
283 | } | |
284 | } | |
5801ead6 | 285 | |
091264f0 | 286 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
224d94b1 | 287 | return -EREMOTEIO; |
5801ead6 AD |
288 | } |
289 | ||
224d94b1 AD |
290 | /***** general DP utility functions *****/ |
291 | ||
5801ead6 | 292 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
224d94b1 | 293 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
5801ead6 AD |
294 | |
295 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |
296 | int lane_count, | |
297 | u8 train_set[4]) | |
298 | { | |
299 | u8 v = 0; | |
300 | u8 p = 0; | |
301 | int lane; | |
302 | ||
303 | for (lane = 0; lane < lane_count; lane++) { | |
0f037bde DV |
304 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
305 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
5801ead6 | 306 | |
d9fdaafb | 307 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
53c1e09f AD |
308 | lane, |
309 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | |
310 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
311 | |
312 | if (this_v > v) | |
313 | v = this_v; | |
314 | if (this_p > p) | |
315 | p = this_p; | |
316 | } | |
317 | ||
318 | if (v >= DP_VOLTAGE_MAX) | |
224d94b1 | 319 | v |= DP_TRAIN_MAX_SWING_REACHED; |
5801ead6 | 320 | |
224d94b1 AD |
321 | if (p >= DP_PRE_EMPHASIS_MAX) |
322 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
5801ead6 | 323 | |
d9fdaafb | 324 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
53c1e09f AD |
325 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
326 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
327 | |
328 | for (lane = 0; lane < 4; lane++) | |
329 | train_set[lane] = v | p; | |
330 | } | |
331 | ||
224d94b1 AD |
332 | /* convert bits per color to bits per pixel */ |
333 | /* get bpc from the EDID */ | |
334 | static int convert_bpc_to_bpp(int bpc) | |
746c1aa4 | 335 | { |
224d94b1 AD |
336 | if (bpc == 0) |
337 | return 24; | |
338 | else | |
339 | return bpc * 3; | |
340 | } | |
746c1aa4 | 341 | |
224d94b1 AD |
342 | /* get the max pix clock supported by the link rate and lane num */ |
343 | static int dp_get_max_dp_pix_clock(int link_rate, | |
344 | int lane_num, | |
345 | int bpp) | |
346 | { | |
347 | return (link_rate * lane_num * 8) / bpp; | |
348 | } | |
834b2904 | 349 | |
224d94b1 | 350 | static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) |
746c1aa4 | 351 | { |
224d94b1 AD |
352 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
353 | } | |
834b2904 | 354 | |
224d94b1 | 355 | /***** radeon specific DP functions *****/ |
746c1aa4 | 356 | |
224d94b1 AD |
357 | /* First get the min lane# when low rate is used according to pixel clock |
358 | * (prefer low rate), second check max lane# supported by DP panel, | |
359 | * if the max lane# < low rate lane# then use max lane# instead. | |
360 | */ | |
361 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, | |
362 | u8 dpcd[DP_DPCD_SIZE], | |
363 | int pix_clock) | |
364 | { | |
eccea792 | 365 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
3b5c662e | 366 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
224d94b1 AD |
367 | int max_lane_num = dp_get_max_lane_number(dpcd); |
368 | int lane_num; | |
369 | int max_dp_pix_clock; | |
370 | ||
371 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { | |
372 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); | |
373 | if (pix_clock <= max_dp_pix_clock) | |
374 | break; | |
834b2904 | 375 | } |
746c1aa4 | 376 | |
224d94b1 | 377 | return lane_num; |
746c1aa4 DA |
378 | } |
379 | ||
224d94b1 AD |
380 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
381 | u8 dpcd[DP_DPCD_SIZE], | |
382 | int pix_clock) | |
746c1aa4 | 383 | { |
eccea792 | 384 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
385 | int lane_num, max_pix_clock; |
386 | ||
fdca78c3 AD |
387 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
388 | ENCODER_OBJECT_ID_NUTMEG) | |
224d94b1 AD |
389 | return 270000; |
390 | ||
391 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); | |
392 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); | |
393 | if (pix_clock <= max_pix_clock) | |
394 | return 162000; | |
395 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); | |
396 | if (pix_clock <= max_pix_clock) | |
397 | return 270000; | |
398 | if (radeon_connector_is_dp12_capable(connector)) { | |
399 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); | |
400 | if (pix_clock <= max_pix_clock) | |
401 | return 540000; | |
834b2904 | 402 | } |
224d94b1 | 403 | |
3b5c662e | 404 | return drm_dp_max_link_rate(dpcd); |
746c1aa4 DA |
405 | } |
406 | ||
834b2904 AD |
407 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
408 | int action, int dp_clock, | |
224d94b1 | 409 | u8 ucconfig, u8 lane_num) |
5801ead6 AD |
410 | { |
411 | DP_ENCODER_SERVICE_PARAMETERS args; | |
412 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
413 | ||
414 | memset(&args, 0, sizeof(args)); | |
415 | args.ucLinkClock = dp_clock / 10; | |
416 | args.ucConfig = ucconfig; | |
417 | args.ucAction = action; | |
418 | args.ucLaneNum = lane_num; | |
419 | args.ucStatus = 0; | |
420 | ||
421 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
422 | return args.ucStatus; | |
423 | } | |
424 | ||
425 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) | |
426 | { | |
427 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
428 | struct drm_device *dev = radeon_connector->base.dev; | |
429 | struct radeon_device *rdev = dev->dev_private; | |
430 | ||
431 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, | |
432 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); | |
433 | } | |
434 | ||
40c5d876 AJ |
435 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
436 | { | |
437 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
438 | u8 buf[3]; | |
439 | ||
440 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
441 | return; | |
442 | ||
443 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) | |
444 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
445 | buf[0], buf[1], buf[2]); | |
446 | ||
447 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) | |
448 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
449 | buf[0], buf[1], buf[2]); | |
450 | } | |
451 | ||
9fa05c98 | 452 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
746c1aa4 | 453 | { |
5801ead6 | 454 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
1a644cd4 | 455 | u8 msg[DP_DPCD_SIZE]; |
224d94b1 | 456 | int ret, i; |
746c1aa4 | 457 | |
1a644cd4 DV |
458 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, |
459 | DP_DPCD_SIZE, 0); | |
834b2904 | 460 | if (ret > 0) { |
1a644cd4 | 461 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
224d94b1 | 462 | DRM_DEBUG_KMS("DPCD: "); |
1a644cd4 | 463 | for (i = 0; i < DP_DPCD_SIZE; i++) |
224d94b1 AD |
464 | DRM_DEBUG_KMS("%02x ", msg[i]); |
465 | DRM_DEBUG_KMS("\n"); | |
40c5d876 AJ |
466 | |
467 | radeon_dp_probe_oui(radeon_connector); | |
468 | ||
9fa05c98 | 469 | return true; |
746c1aa4 | 470 | } |
5801ead6 | 471 | dig_connector->dpcd[0] = 0; |
9fa05c98 | 472 | return false; |
746c1aa4 DA |
473 | } |
474 | ||
386d4d75 AD |
475 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
476 | struct drm_connector *connector) | |
224d94b1 AD |
477 | { |
478 | struct drm_device *dev = encoder->dev; | |
479 | struct radeon_device *rdev = dev->dev_private; | |
00dfb8df | 480 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
224d94b1 | 481 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
0ceb996c AD |
482 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
483 | u8 tmp; | |
224d94b1 AD |
484 | |
485 | if (!ASIC_IS_DCE4(rdev)) | |
386d4d75 | 486 | return panel_mode; |
224d94b1 | 487 | |
0ceb996c AD |
488 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
489 | /* DP bridge chips */ | |
490 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
491 | if (tmp & 1) | |
492 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
493 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || | |
494 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) | |
304a4840 AD |
495 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
496 | else | |
0ceb996c | 497 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
304a4840 | 498 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
0ceb996c AD |
499 | /* eDP */ |
500 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
00dfb8df AD |
501 | if (tmp & 1) |
502 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
503 | } | |
224d94b1 | 504 | |
386d4d75 | 505 | return panel_mode; |
224d94b1 AD |
506 | } |
507 | ||
5801ead6 | 508 | void radeon_dp_set_link_config(struct drm_connector *connector, |
e811f5ae | 509 | const struct drm_display_mode *mode) |
5801ead6 | 510 | { |
224d94b1 | 511 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5801ead6 AD |
512 | struct radeon_connector_atom_dig *dig_connector; |
513 | ||
5801ead6 AD |
514 | if (!radeon_connector->con_priv) |
515 | return; | |
516 | dig_connector = radeon_connector->con_priv; | |
517 | ||
224d94b1 AD |
518 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
519 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { | |
520 | dig_connector->dp_clock = | |
521 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
522 | dig_connector->dp_lane_count = | |
523 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); | |
524 | } | |
5801ead6 AD |
525 | } |
526 | ||
224d94b1 | 527 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
528 | struct drm_display_mode *mode) |
529 | { | |
224d94b1 AD |
530 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
531 | struct radeon_connector_atom_dig *dig_connector; | |
532 | int dp_clock; | |
5801ead6 | 533 | |
224d94b1 AD |
534 | if (!radeon_connector->con_priv) |
535 | return MODE_CLOCK_HIGH; | |
536 | dig_connector = radeon_connector->con_priv; | |
537 | ||
538 | dp_clock = | |
539 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
540 | ||
541 | if ((dp_clock == 540000) && | |
542 | (!radeon_connector_is_dp12_capable(connector))) | |
543 | return MODE_CLOCK_HIGH; | |
544 | ||
545 | return MODE_OK; | |
5801ead6 AD |
546 | } |
547 | ||
224d94b1 AD |
548 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
549 | u8 link_status[DP_LINK_STATUS_SIZE]) | |
746c1aa4 DA |
550 | { |
551 | int ret; | |
834b2904 AD |
552 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
553 | link_status, DP_LINK_STATUS_SIZE, 100); | |
554 | if (ret <= 0) { | |
746c1aa4 DA |
555 | return false; |
556 | } | |
557 | ||
9a6a4b47 | 558 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
746c1aa4 DA |
559 | return true; |
560 | } | |
561 | ||
d5811e87 AD |
562 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
563 | { | |
564 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
565 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
566 | ||
567 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) | |
568 | return false; | |
1ffdff13 | 569 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
d5811e87 AD |
570 | return false; |
571 | return true; | |
572 | } | |
573 | ||
224d94b1 AD |
574 | struct radeon_dp_link_train_info { |
575 | struct radeon_device *rdev; | |
576 | struct drm_encoder *encoder; | |
577 | struct drm_connector *connector; | |
578 | struct radeon_connector *radeon_connector; | |
579 | int enc_id; | |
580 | int dp_clock; | |
581 | int dp_lane_count; | |
224d94b1 | 582 | bool tp3_supported; |
1a644cd4 | 583 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
224d94b1 AD |
584 | u8 train_set[4]; |
585 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
586 | u8 tries; | |
5a96a899 | 587 | bool use_dpencoder; |
224d94b1 | 588 | }; |
5801ead6 | 589 | |
224d94b1 | 590 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 591 | { |
224d94b1 AD |
592 | /* set the initial vs/emph on the source */ |
593 | atombios_dig_transmitter_setup(dp_info->encoder, | |
594 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, | |
595 | 0, dp_info->train_set[0]); /* sets all lanes at once */ | |
596 | ||
597 | /* set the vs/emph on the sink */ | |
598 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, | |
599 | dp_info->train_set, dp_info->dp_lane_count, 0); | |
5801ead6 AD |
600 | } |
601 | ||
224d94b1 | 602 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
746c1aa4 | 603 | { |
224d94b1 | 604 | int rtp = 0; |
746c1aa4 | 605 | |
224d94b1 | 606 | /* set training pattern on the source */ |
5a96a899 | 607 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
224d94b1 AD |
608 | switch (tp) { |
609 | case DP_TRAINING_PATTERN_1: | |
610 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; | |
611 | break; | |
612 | case DP_TRAINING_PATTERN_2: | |
613 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; | |
614 | break; | |
615 | case DP_TRAINING_PATTERN_3: | |
616 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; | |
617 | break; | |
618 | } | |
619 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); | |
620 | } else { | |
621 | switch (tp) { | |
622 | case DP_TRAINING_PATTERN_1: | |
623 | rtp = 0; | |
624 | break; | |
625 | case DP_TRAINING_PATTERN_2: | |
626 | rtp = 1; | |
627 | break; | |
628 | } | |
629 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, | |
630 | dp_info->dp_clock, dp_info->enc_id, rtp); | |
631 | } | |
746c1aa4 | 632 | |
224d94b1 AD |
633 | /* enable training pattern on the sink */ |
634 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); | |
746c1aa4 DA |
635 | } |
636 | ||
224d94b1 | 637 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 638 | { |
386d4d75 AD |
639 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
640 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
224d94b1 | 641 | u8 tmp; |
5801ead6 | 642 | |
224d94b1 AD |
643 | /* power up the sink */ |
644 | if (dp_info->dpcd[0] >= 0x11) | |
645 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
646 | DP_SET_POWER, DP_SET_POWER_D0); | |
647 | ||
648 | /* possibly enable downspread on the sink */ | |
649 | if (dp_info->dpcd[3] & 0x1) | |
650 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
651 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); | |
652 | else | |
653 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
654 | DP_DOWNSPREAD_CTRL, 0); | |
5801ead6 | 655 | |
386d4d75 AD |
656 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
657 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { | |
658 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); | |
659 | } | |
5801ead6 | 660 | |
224d94b1 AD |
661 | /* set the lane count on the sink */ |
662 | tmp = dp_info->dp_lane_count; | |
abc8113f DA |
663 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
664 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) | |
224d94b1 AD |
665 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
666 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); | |
5801ead6 | 667 | |
224d94b1 | 668 | /* set the link rate on the sink */ |
3b5c662e | 669 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
224d94b1 | 670 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
5801ead6 | 671 | |
224d94b1 | 672 | /* start training on the source */ |
5a96a899 | 673 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
674 | atombios_dig_encoder_setup(dp_info->encoder, |
675 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); | |
5801ead6 | 676 | else |
224d94b1 AD |
677 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
678 | dp_info->dp_clock, dp_info->enc_id, 0); | |
5801ead6 | 679 | |
5801ead6 | 680 | /* disable the training pattern on the sink */ |
224d94b1 AD |
681 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
682 | DP_TRAINING_PATTERN_SET, | |
683 | DP_TRAINING_PATTERN_DISABLE); | |
684 | ||
685 | return 0; | |
686 | } | |
5801ead6 | 687 | |
224d94b1 AD |
688 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
689 | { | |
5801ead6 | 690 | udelay(400); |
5801ead6 | 691 | |
224d94b1 AD |
692 | /* disable the training pattern on the sink */ |
693 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
694 | DP_TRAINING_PATTERN_SET, | |
695 | DP_TRAINING_PATTERN_DISABLE); | |
696 | ||
697 | /* disable the training pattern on the source */ | |
5a96a899 | 698 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
699 | atombios_dig_encoder_setup(dp_info->encoder, |
700 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); | |
701 | else | |
702 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, | |
703 | dp_info->dp_clock, dp_info->enc_id, 0); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) | |
709 | { | |
710 | bool clock_recovery; | |
711 | u8 voltage; | |
712 | int i; | |
713 | ||
714 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); | |
715 | memset(dp_info->train_set, 0, 4); | |
716 | radeon_dp_update_vs_emph(dp_info); | |
717 | ||
718 | udelay(400); | |
5fbfce7f | 719 | |
5801ead6 AD |
720 | /* clock recovery loop */ |
721 | clock_recovery = false; | |
224d94b1 | 722 | dp_info->tries = 0; |
5801ead6 | 723 | voltage = 0xff; |
224d94b1 | 724 | while (1) { |
1a644cd4 | 725 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
224d94b1 | 726 | |
8d1c702a JG |
727 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
728 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 729 | break; |
8d1c702a | 730 | } |
5801ead6 | 731 | |
01916270 | 732 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
733 | clock_recovery = true; |
734 | break; | |
735 | } | |
736 | ||
224d94b1 AD |
737 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
738 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
5801ead6 AD |
739 | break; |
740 | } | |
224d94b1 | 741 | if (i == dp_info->dp_lane_count) { |
5801ead6 AD |
742 | DRM_ERROR("clock recovery reached max voltage\n"); |
743 | break; | |
744 | } | |
745 | ||
224d94b1 AD |
746 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
747 | ++dp_info->tries; | |
748 | if (dp_info->tries == 5) { | |
5801ead6 AD |
749 | DRM_ERROR("clock recovery tried 5 times\n"); |
750 | break; | |
751 | } | |
752 | } else | |
224d94b1 | 753 | dp_info->tries = 0; |
5801ead6 | 754 | |
224d94b1 | 755 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
5801ead6 AD |
756 | |
757 | /* Compute new train_set as requested by sink */ | |
224d94b1 AD |
758 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
759 | ||
760 | radeon_dp_update_vs_emph(dp_info); | |
5801ead6 | 761 | } |
224d94b1 | 762 | if (!clock_recovery) { |
5801ead6 | 763 | DRM_ERROR("clock recovery failed\n"); |
224d94b1 AD |
764 | return -1; |
765 | } else { | |
d9fdaafb | 766 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
767 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
768 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
53c1e09f | 769 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
770 | return 0; |
771 | } | |
772 | } | |
5801ead6 | 773 | |
224d94b1 AD |
774 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
775 | { | |
776 | bool channel_eq; | |
5801ead6 | 777 | |
224d94b1 AD |
778 | if (dp_info->tp3_supported) |
779 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); | |
bcc1c2a1 | 780 | else |
224d94b1 | 781 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
5801ead6 AD |
782 | |
783 | /* channel equalization loop */ | |
224d94b1 | 784 | dp_info->tries = 0; |
5801ead6 | 785 | channel_eq = false; |
224d94b1 | 786 | while (1) { |
1a644cd4 | 787 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
224d94b1 | 788 | |
8d1c702a JG |
789 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
790 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 791 | break; |
8d1c702a | 792 | } |
5801ead6 | 793 | |
1ffdff13 | 794 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
795 | channel_eq = true; |
796 | break; | |
797 | } | |
798 | ||
799 | /* Try 5 times */ | |
224d94b1 | 800 | if (dp_info->tries > 5) { |
5801ead6 AD |
801 | DRM_ERROR("channel eq failed: 5 tries\n"); |
802 | break; | |
803 | } | |
804 | ||
805 | /* Compute new train_set as requested by sink */ | |
224d94b1 | 806 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
5801ead6 | 807 | |
224d94b1 AD |
808 | radeon_dp_update_vs_emph(dp_info); |
809 | dp_info->tries++; | |
5801ead6 AD |
810 | } |
811 | ||
224d94b1 | 812 | if (!channel_eq) { |
5801ead6 | 813 | DRM_ERROR("channel eq failed\n"); |
224d94b1 AD |
814 | return -1; |
815 | } else { | |
d9fdaafb | 816 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
817 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
818 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | |
53c1e09f | 819 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
820 | return 0; |
821 | } | |
5801ead6 AD |
822 | } |
823 | ||
224d94b1 AD |
824 | void radeon_dp_link_train(struct drm_encoder *encoder, |
825 | struct drm_connector *connector) | |
746c1aa4 | 826 | { |
224d94b1 AD |
827 | struct drm_device *dev = encoder->dev; |
828 | struct radeon_device *rdev = dev->dev_private; | |
829 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
830 | struct radeon_encoder_atom_dig *dig; | |
831 | struct radeon_connector *radeon_connector; | |
832 | struct radeon_connector_atom_dig *dig_connector; | |
833 | struct radeon_dp_link_train_info dp_info; | |
5a96a899 JG |
834 | int index; |
835 | u8 tmp, frev, crev; | |
746c1aa4 | 836 | |
224d94b1 AD |
837 | if (!radeon_encoder->enc_priv) |
838 | return; | |
839 | dig = radeon_encoder->enc_priv; | |
746c1aa4 | 840 | |
224d94b1 AD |
841 | radeon_connector = to_radeon_connector(connector); |
842 | if (!radeon_connector->con_priv) | |
843 | return; | |
844 | dig_connector = radeon_connector->con_priv; | |
834b2904 | 845 | |
224d94b1 AD |
846 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
847 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) | |
848 | return; | |
746c1aa4 | 849 | |
5a96a899 JG |
850 | /* DPEncoderService newer than 1.1 can't program properly the |
851 | * training pattern. When facing such version use the | |
852 | * DIGXEncoderControl (X== 1 | 2) | |
853 | */ | |
854 | dp_info.use_dpencoder = true; | |
855 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
856 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { | |
857 | if (crev > 1) { | |
858 | dp_info.use_dpencoder = false; | |
859 | } | |
860 | } | |
861 | ||
224d94b1 AD |
862 | dp_info.enc_id = 0; |
863 | if (dig->dig_encoder) | |
864 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; | |
865 | else | |
866 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; | |
867 | if (dig->linkb) | |
868 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; | |
869 | else | |
870 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; | |
834b2904 | 871 | |
224d94b1 AD |
872 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
873 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) | |
874 | dp_info.tp3_supported = true; | |
875 | else | |
876 | dp_info.tp3_supported = false; | |
877 | ||
1a644cd4 | 878 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
224d94b1 AD |
879 | dp_info.rdev = rdev; |
880 | dp_info.encoder = encoder; | |
881 | dp_info.connector = connector; | |
882 | dp_info.radeon_connector = radeon_connector; | |
883 | dp_info.dp_lane_count = dig_connector->dp_lane_count; | |
884 | dp_info.dp_clock = dig_connector->dp_clock; | |
885 | ||
886 | if (radeon_dp_link_train_init(&dp_info)) | |
887 | goto done; | |
888 | if (radeon_dp_link_train_cr(&dp_info)) | |
889 | goto done; | |
890 | if (radeon_dp_link_train_ce(&dp_info)) | |
891 | goto done; | |
892 | done: | |
893 | if (radeon_dp_link_train_finish(&dp_info)) | |
894 | return; | |
746c1aa4 | 895 | } |