projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms/dp: fix return in dpcd retrival.
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "drm_dp_helper.h"
33
f92a8b67 34/* move these to drm_dp_helper.c/h */
5801ead6
AD		 35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
45static char *link_train_names[] = {
46 "pattern 1", "pattern 2", "idle", "off"
47};
f92a8b67
AD		 48
49static const int dp_clocks[] = {
50 54000, // 1 lane, 1.62 Ghz
51 90000, // 1 lane, 2.70 Ghz
52 108000, // 2 lane, 1.62 Ghz
53 180000, // 2 lane, 2.70 Ghz
54 216000, // 4 lane, 1.62 Ghz
55 360000, // 4 lane, 2.70 Ghz
56};
57
58static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
59
5801ead6
AD		 60/* common helper functions */
61static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 62{
63 int i;
5801ead6
AD		 64 u8 max_link_bw;
65 u8 max_lane_count;
66
67 if (!dpcd)
68 return 0;
69
70 max_link_bw = dpcd[DP_MAX_LINK_RATE];
71 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 72
73 switch (max_link_bw) {
74 case DP_LINK_BW_1_62:
75 default:
76 for (i = 0; i < num_dp_clocks; i++) {
77 if (i % 2)
78 continue;
5801ead6
AD		 79 switch (max_lane_count) {
80 case 1:
81 if (i > 1)
82 return 0;
83 break;
84 case 2:
85 if (i > 3)
86 return 0;
87 break;
88 case 4:
89 default:
90 break;
91 }
f92a8b67
AD		 92 if (dp_clocks[i] > mode_clock) {
93 if (i < 2)
94 return 1;
95 else if (i < 4)
96 return 2;
97 else
98 return 4;
99 }
100 }
101 break;
102 case DP_LINK_BW_2_7:
103 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 104 switch (max_lane_count) {
105 case 1:
106 if (i > 1)
107 return 0;
108 break;
109 case 2:
110 if (i > 3)
111 return 0;
112 break;
113 case 4:
114 default:
115 break;
116 }
f92a8b67
AD		 117 if (dp_clocks[i] > mode_clock) {
118 if (i < 2)
119 return 1;
120 else if (i < 4)
121 return 2;
122 else
123 return 4;
124 }
125 }
126 break;
127 }
128
129 return 0;
130}
131
5801ead6 132static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 133{
134 int i;
5801ead6
AD		 135 u8 max_link_bw;
136 u8 max_lane_count;
137
138 if (!dpcd)
139 return 0;
140
141 max_link_bw = dpcd[DP_MAX_LINK_RATE];
142 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 143
144 switch (max_link_bw) {
145 case DP_LINK_BW_1_62:
146 default:
5801ead6
AD		 147 for (i = 0; i < num_dp_clocks; i++) {
148 if (i % 2)
149 continue;
150 switch (max_lane_count) {
151 case 1:
152 if (i > 1)
153 return 0;
154 break;
155 case 2:
156 if (i > 3)
157 return 0;
158 break;
159 case 4:
160 default:
161 break;
162 }
163 if (dp_clocks[i] > mode_clock)
164 return 162000;
165 }
f92a8b67
AD		 166 break;
167 case DP_LINK_BW_2_7:
168 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 169 switch (max_lane_count) {
170 case 1:
171 if (i > 1)
172 return 0;
173 break;
174 case 2:
175 if (i > 3)
176 return 0;
177 break;
178 case 4:
179 default:
180 break;
181 }
f92a8b67
AD		 182 if (dp_clocks[i] > mode_clock)
183 return (i % 2) ? 270000 : 162000;
184 }
185 }
186
187 return 0;
188}
189
5801ead6
AD		 190int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
191{
192 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
193 int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
194
195 if ((lanes == 0) || (bw == 0))
196 return MODE_CLOCK_HIGH;
197
198 return MODE_OK;
199}
200
201static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
202{
203 return link_status[r - DP_LANE0_1_STATUS];
204}
205
206static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
207 int lane)
208{
209 int i = DP_LANE0_1_STATUS + (lane >> 1);
210 int s = (lane & 1) * 4;
211 u8 l = dp_link_status(link_status, i);
212 return (l >> s) & 0xf;
213}
214
215static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
216 int lane_count)
217{
218 int lane;
219 u8 lane_status;
220
221 for (lane = 0; lane < lane_count; lane++) {
222 lane_status = dp_get_lane_status(link_status, lane);
223 if ((lane_status & DP_LANE_CR_DONE) == 0)
224 return false;
225 }
226 return true;
227}
228
229static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
230 int lane_count)
231{
232 u8 lane_align;
233 u8 lane_status;
234 int lane;
235
236 lane_align = dp_link_status(link_status,
237 DP_LANE_ALIGN_STATUS_UPDATED);
238 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
239 return false;
240 for (lane = 0; lane < lane_count; lane++) {
241 lane_status = dp_get_lane_status(link_status, lane);
242 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
243 return false;
244 }
245 return true;
246}
247
248static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
249 int lane)
250
251{
252 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
253 int s = ((lane & 1) ?
254 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
255 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
256 u8 l = dp_link_status(link_status, i);
257
258 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
259}
260
261static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
262 int lane)
263{
264 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
265 int s = ((lane & 1) ?
266 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
267 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
268 u8 l = dp_link_status(link_status, i);
269
270 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
271}
272
273/* XXX fix me -- chip specific */
274#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
275static u8 dp_pre_emphasis_max(u8 voltage_swing)
276{
277 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
278 case DP_TRAIN_VOLTAGE_SWING_400:
279 return DP_TRAIN_PRE_EMPHASIS_6;
280 case DP_TRAIN_VOLTAGE_SWING_600:
281 return DP_TRAIN_PRE_EMPHASIS_6;
282 case DP_TRAIN_VOLTAGE_SWING_800:
283 return DP_TRAIN_PRE_EMPHASIS_3_5;
284 case DP_TRAIN_VOLTAGE_SWING_1200:
285 default:
286 return DP_TRAIN_PRE_EMPHASIS_0;
287 }
288}
289
290static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
291 int lane_count,
292 u8 train_set[4])
293{
294 u8 v = 0;
295 u8 p = 0;
296 int lane;
297
298 for (lane = 0; lane < lane_count; lane++) {
299 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
300 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
301
302 DRM_INFO("requested signal parameters: lane %d voltage %s pre_emph %s\n",
303 lane,
304 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
305 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
306
307 if (this_v > v)
308 v = this_v;
309 if (this_p > p)
310 p = this_p;
311 }
312
313 if (v >= DP_VOLTAGE_MAX)
314 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
315
316 if (p >= dp_pre_emphasis_max(v))
317 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
318
319 DRM_INFO("using signal parameters: voltage %s pre_emph %s\n",
320 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
321 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
322
323 for (lane = 0; lane < 4; lane++)
324 train_set[lane] = v | p;
325}
326
327
328/* radeon aux chan functions */
746c1aa4 329bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
1a66c95a 330 int num_bytes, u8 *read_byte,
746c1aa4
DA		 331 u8 read_buf_len, u8 delay)
332{
333 struct drm_device *dev = chan->dev;
334 struct radeon_device *rdev = dev->dev_private;
335 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
336 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
337 unsigned char *base;
1a66c95a 338
746c1aa4 339 memset(&args, 0, sizeof(args));
1a66c95a 340
746c1aa4
DA		 341 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
342
343 memcpy(base, req_bytes, num_bytes);
344
345 args.lpAuxRequest = 0;
346 args.lpDataOut = 16;
347 args.ucDataOutLen = 0;
6a93cb25 348 args.ucChannelID = chan->rec.i2c_id;
1a66c95a 349 args.ucDelay = delay / 10;
746c1aa4
DA		 350
351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352
353 if (args.ucReplyStatus) {
354 DRM_ERROR("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
355 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
6a93cb25 356 chan->rec.i2c_id, args.ucReplyStatus);
746c1aa4
DA		 357 return false;
358 }
359
360 if (args.ucDataOutLen && read_byte && read_buf_len) {
361 if (read_buf_len < args.ucDataOutLen) {
362 DRM_ERROR("Buffer to small for return answer %d %d\n",
363 read_buf_len, args.ucDataOutLen);
364 return false;
365 }
366 {
367 int len = min(read_buf_len, args.ucDataOutLen);
368 memcpy(read_byte, base + 16, len);
369 }
370 }
371 return true;
372}
373
746c1aa4
DA		 374bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
375 uint8_t send_bytes, uint8_t *send)
376{
5801ead6 377 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 378 u8 msg[20];
379 u8 msg_len, dp_msg_len;
380 bool ret;
381
382 dp_msg_len = 4;
383 msg[0] = address;
384 msg[1] = address >> 8;
385 msg[2] = AUX_NATIVE_WRITE << 4;
386 dp_msg_len += send_bytes;
387 msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
388
389 if (send_bytes > 16)
390 return false;
391
392 memcpy(&msg[4], send, send_bytes);
393 msg_len = 4 + send_bytes;
5801ead6 394 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
746c1aa4
DA		 395 return ret;
396}
397
398bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
399 uint8_t delay, uint8_t expected_bytes,
400 uint8_t *read_p)
401{
5801ead6 402 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 403 u8 msg[20];
404 u8 msg_len, dp_msg_len;
405 bool ret = false;
406 msg_len = 4;
407 dp_msg_len = 4;
408 msg[0] = address;
409 msg[1] = address >> 8;
410 msg[2] = AUX_NATIVE_READ << 4;
411 msg[3] = (dp_msg_len) << 4;
412 msg[3] |= expected_bytes - 1;
413
5801ead6 414 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
746c1aa4
DA		 415 return ret;
416}
417
5801ead6
AD		 418/* radeon dp functions */
419static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
420 uint8_t ucconfig, uint8_t lane_num)
421{
422 DP_ENCODER_SERVICE_PARAMETERS args;
423 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
424
425 memset(&args, 0, sizeof(args));
426 args.ucLinkClock = dp_clock / 10;
427 args.ucConfig = ucconfig;
428 args.ucAction = action;
429 args.ucLaneNum = lane_num;
430 args.ucStatus = 0;
431
432 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
433 return args.ucStatus;
434}
435
436u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
437{
438 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
439 struct drm_device *dev = radeon_connector->base.dev;
440 struct radeon_device *rdev = dev->dev_private;
441
442 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
443 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
444}
445
1a66c95a 446void radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 447{
5801ead6 448 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 449 u8 msg[25];
450 int ret;
451
1a66c95a 452 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
746c1aa4 453 if (ret) {
5801ead6 454 memcpy(dig_connector->dpcd, msg, 8);
1a66c95a 455 {
746c1aa4 456 int i;
1a66c95a 457 printk("DPCD: ");
746c1aa4
DA		 458 for (i = 0; i < 8; i++)
459 printk("%02x ", msg[i]);
460 printk("\n");
461 }
54d9cb47 462 return;
746c1aa4 463 }
5801ead6 464 dig_connector->dpcd[0] = 0;
746c1aa4
DA		 465 return;
466}
467
5801ead6
AD		 468void radeon_dp_set_link_config(struct drm_connector *connector,
469 struct drm_display_mode *mode)
470{
471 struct radeon_connector *radeon_connector;
472 struct radeon_connector_atom_dig *dig_connector;
473
474 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
475 return;
476
477 radeon_connector = to_radeon_connector(connector);
478 if (!radeon_connector->con_priv)
479 return;
480 dig_connector = radeon_connector->con_priv;
481
482 dig_connector->dp_clock =
483 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
484 dig_connector->dp_lane_count =
485 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
486}
487
488int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
489 struct drm_display_mode *mode)
490{
491 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
492
493 return dp_mode_valid(dig_connector->dpcd, mode->clock);
494}
495
746c1aa4
DA		 496static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
497 u8 link_status[DP_LINK_STATUS_SIZE])
498{
499 int ret;
500 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
501 DP_LINK_STATUS_SIZE, link_status);
502 if (!ret) {
503 DRM_ERROR("displayport link status failed\n");
504 return false;
505 }
506
507 DRM_INFO("link status %02x %02x %02x %02x %02x %02x\n",
508 link_status[0], link_status[1], link_status[2],
509 link_status[3], link_status[4], link_status[5]);
510 return true;
511}
512
513static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
514{
5801ead6
AD		 515 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
516
517 if (dig_connector->dpcd[0] >= 0x11) {
1a66c95a 518 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
746c1aa4
DA		 519 &power_state);
520 }
521}
522
5801ead6
AD		 523static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
524{
525 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
526 &downspread);
527}
528
529static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
530 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
531{
532 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
533 link_configuration);
534}
535
746c1aa4 536static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
5801ead6 537 struct drm_encoder *encoder,
746c1aa4
DA		 538 u8 train_set[4])
539{
5801ead6
AD		 540 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
541 int i;
542
543 for (i = 0; i < dig_connector->dp_lane_count; i++)
544 atombios_dig_transmitter_setup(encoder,
545 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
546 i, train_set[i]);
746c1aa4 547
746c1aa4 548 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
5801ead6 549 dig_connector->dp_lane_count, train_set);
746c1aa4
DA		 550}
551
552static void dp_set_training(struct radeon_connector *radeon_connector,
553 u8 training)
554{
555 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
556 1, &training);
557}
558
5801ead6
AD		 559void dp_link_train(struct drm_encoder *encoder,
560 struct drm_connector *connector)
561{
562 struct drm_device *dev = encoder->dev;
563 struct radeon_device *rdev = dev->dev_private;
564 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
565 struct radeon_encoder_atom_dig *dig;
566 struct radeon_connector *radeon_connector;
567 struct radeon_connector_atom_dig *dig_connector;
568 int enc_id = 0;
569 bool clock_recovery, channel_eq;
570 u8 link_status[DP_LINK_STATUS_SIZE];
571 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
572 u8 tries, voltage;
573 u8 train_set[4];
574 int i;
575
576 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
577 return;
578
579 if (!radeon_encoder->enc_priv)
580 return;
581 dig = radeon_encoder->enc_priv;
582
583 radeon_connector = to_radeon_connector(connector);
584 if (!radeon_connector->con_priv)
585 return;
586 dig_connector = radeon_connector->con_priv;
587
588 if (ASIC_IS_DCE32(rdev)) {
589 if (dig->dig_block)
590 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
591 else
592 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
593 if (dig_connector->linkb)
594 enc_id |= ATOM_DP_CONFIG_LINK_B;
595 else
596 enc_id |= ATOM_DP_CONFIG_LINK_A;
597 } else {
598 if (dig_connector->linkb)
599 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
600 else
601 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
602 }
603
604 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
605 if (dig_connector->dp_clock == 270000)
606 link_configuration[0] = DP_LINK_BW_2_7;
607 else
608 link_configuration[0] = DP_LINK_BW_1_62;
609 link_configuration[1] = dig_connector->dp_lane_count;
610 if (dig_connector->dpcd[0] >= 0x11)
611 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
612
613 /* power up the sink */
614 dp_set_power(radeon_connector, DP_SET_POWER_D0);
615 /* disable the training pattern on the sink */
616 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
617 /* set link bw and lanes on the sink */
618 dp_set_link_bw_lanes(radeon_connector, link_configuration);
619 /* disable downspread on the sink */
620 dp_set_downspread(radeon_connector, 0);
621 /* start training on the source */
622 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
623 dig_connector->dp_clock, enc_id, 0);
624 /* set training pattern 1 on the source */
625 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
626 dig_connector->dp_clock, enc_id, 0);
627
628 /* set initial vs/emph */
629 memset(train_set, 0, 4);
630 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
631 udelay(400);
632 /* set training pattern 1 on the sink */
633 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
634
635 /* clock recovery loop */
636 clock_recovery = false;
637 tries = 0;
638 voltage = 0xff;
639 for (;;) {
640 udelay(100);
641 if (!atom_dp_get_link_status(radeon_connector, link_status))
642 break;
643
644 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
645 clock_recovery = true;
646 break;
647 }
648
649 for (i = 0; i < dig_connector->dp_lane_count; i++) {
650 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
651 break;
652 }
653 if (i == dig_connector->dp_lane_count) {
654 DRM_ERROR("clock recovery reached max voltage\n");
655 break;
656 }
657
658 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
659 ++tries;
660 if (tries == 5) {
661 DRM_ERROR("clock recovery tried 5 times\n");
662 break;
663 }
664 } else
665 tries = 0;
666
667 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
668
669 /* Compute new train_set as requested by sink */
670 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
671 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
672 }
673 if (!clock_recovery)
674 DRM_ERROR("clock recovery failed\n");
675 else
676 DRM_INFO("clock recovery at voltage %d pre-emphasis %d\n",
677 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
678 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
679 DP_TRAIN_PRE_EMPHASIS_SHIFT);
680
681
682 /* set training pattern 2 on the sink */
683 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
684 /* set training pattern 2 on the source */
685 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
686 dig_connector->dp_clock, enc_id, 1);
687
688 /* channel equalization loop */
689 tries = 0;
690 channel_eq = false;
691 for (;;) {
692 udelay(400);
693 if (!atom_dp_get_link_status(radeon_connector, link_status))
694 break;
695
696 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
697 channel_eq = true;
698 break;
699 }
700
701 /* Try 5 times */
702 if (tries > 5) {
703 DRM_ERROR("channel eq failed: 5 tries\n");
704 break;
705 }
706
707 /* Compute new train_set as requested by sink */
708 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
709 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
710
711 tries++;
712 }
713
714 if (!channel_eq)
715 DRM_ERROR("channel eq failed\n");
716 else
717 DRM_INFO("channel eq at voltage %d pre-emphasis %d\n",
718 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
719 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
720 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
721
722 /* disable the training pattern on the sink */
723 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
724
725 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
726 dig_connector->dp_clock, enc_id, 0);
727}
728
746c1aa4
DA		 729int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
730 uint8_t write_byte, uint8_t *read_byte)
731{
732 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
733 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
734 int ret = 0;
735 uint16_t address = algo_data->address;
736 uint8_t msg[5];
737 uint8_t reply[2];
738 int msg_len, dp_msg_len;
739 int reply_bytes;
740
741 /* Set up the command byte */
742 if (mode & MODE_I2C_READ)
743 msg[2] = AUX_I2C_READ << 4;
744 else
745 msg[2] = AUX_I2C_WRITE << 4;
746
747 if (!(mode & MODE_I2C_STOP))
748 msg[2] |= AUX_I2C_MOT << 4;
749
750 msg[0] = address;
751 msg[1] = address >> 8;
752
753 reply_bytes = 1;
754
755 msg_len = 4;
756 dp_msg_len = 3;
757 switch (mode) {
758 case MODE_I2C_WRITE:
759 msg[4] = write_byte;
760 msg_len++;
761 dp_msg_len += 2;
762 break;
763 case MODE_I2C_READ:
764 dp_msg_len += 1;
765 break;
766 default:
767 break;
768 }
769
770 msg[3] = (dp_msg_len) << 4;
771 ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
772
773 if (ret) {
774 if (read_byte)
775 *read_byte = reply[0];
776 return reply_bytes;
777 }
778 return -EREMOTEIO;
779}
5801ead6 780
Linux kernel - Deliverables
This page took 0.141062 seconds and 5 git commands to generate.